DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c

   1 /*++
   2
   3 Copyright (c) 2005 - 2012, Intel Corporation. All rights reserved.<BR>
   4 This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 Module Name:
  13
  14   PciEnumeratorSupport.c
  15
  16 Abstract:
  17
  18   PCI Bus Driver
  19
  20 Revision History
  21
  22 --*/
  23
  24 #include "PciBus.h"
  25
  26 EFI_STATUS
  27 InitializePPB (
  28   IN PCI_IO_DEVICE *PciIoDevice
  29 );
  30
  31 EFI_STATUS
  32 InitializeP2C (
  33   IN PCI_IO_DEVICE *PciIoDevice
  34 );
  35
  36 PCI_IO_DEVICE*
  37 CreatePciIoDevice (
  38   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *PciRootBridgeIo,
  39   IN PCI_TYPE00                       *Pci,
  40   UINT8                               Bus,
  41   UINT8                               Device,
  42   UINT8                               Func
  43 );
  44
  45
  46 PCI_IO_DEVICE*
  47 GatherP2CInfo (
  48   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *PciRootBridgeIo,
  49   IN PCI_TYPE00                       *Pci,
  50   UINT8                               Bus,
  51   UINT8                               Device,
  52   UINT8                               Func
  53 );
  54
  55 UINTN
  56 PciParseBar (
  57   IN PCI_IO_DEVICE  *PciIoDevice,
  58   IN UINTN          Offset,
  59   IN UINTN          BarIndex
  60 );
  61
  62
  63 EFI_STATUS
  64 PciSearchDevice (
  65   IN PCI_IO_DEVICE                      *Bridge,
  66   PCI_TYPE00                            *Pci,
  67   UINT8                                 Bus,
  68   UINT8                                 Device,
  69   UINT8                                 Func,
  70   PCI_IO_DEVICE                         **PciDevice
  71 );
  72
  73
  74 EFI_STATUS
  75 DetermineDeviceAttribute (
  76   IN PCI_IO_DEVICE                      *PciIoDevice
  77 );
  78
  79 EFI_STATUS
  80 BarExisted (
  81   IN PCI_IO_DEVICE *PciIoDevice,
  82   IN UINTN         Offset,
  83   OUT UINT32       *BarLengthValue,
  84   OUT UINT32       *OriginalBarValue
  85   );
  86
  87
  88
  89 EFI_DEVICE_PATH_PROTOCOL*
  90 CreatePciDevicePath(
  91   IN  EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
  92   IN  PCI_IO_DEVICE            *PciIoDevice
  93 );
  94
  95 PCI_IO_DEVICE*
  96 GatherDeviceInfo (
  97   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *PciRootBridgeIo,
  98   IN PCI_TYPE00                       *Pci,
  99   UINT8                               Bus,
 100   UINT8                               Device,
 101   UINT8                               Func
 102 );
 103
 104 PCI_IO_DEVICE*
 105 GatherPPBInfo (
 106   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *PciRootBridgeIo,
 107   IN PCI_TYPE00                       *Pci,
 108   UINT8                               Bus,
 109   UINT8                               Device,
 110   UINT8                               Func
 111 );
 112
 113 EFI_STATUS
 114 PciDevicePresent (
 115   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *PciRootBridgeIo,
 116   PCI_TYPE00                          *Pci,
 117   UINT8                               Bus,
 118   UINT8                               Device,
 119   UINT8                               Func
 120   )
 121 /*++
 122
 123 Routine Description:
 124
 125   This routine is used to check whether the pci device is present
 126
 127 Arguments:
 128
 129 Returns:
 130
 131   None
 132
 133 --*/
 134 {
 135   UINT64      Address;
 136   EFI_STATUS  Status;
 137
 138   //
 139   // Create PCI address map in terms of Bus, Device and Func
 140   //
 141   Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);
 142
 143   //
 144   // Read the Vendor Id register
 145   //
 146   Status = PciRootBridgeIo->Pci.Read (
 147                                   PciRootBridgeIo,
 148                                   EfiPciWidthUint32,
 149                                   Address,
 150                                   1,
 151                                   Pci
 152                                   );
 153
 154   if (!EFI_ERROR (Status) && (Pci->Hdr).VendorId != 0xffff) {
 155
 156     //
 157     // Read the entire config header for the device
 158     //
 159
 160     Status = PciRootBridgeIo->Pci.Read (
 161                                     PciRootBridgeIo,
 162                                     EfiPciWidthUint32,
 163                                     Address,
 164                                     sizeof (PCI_TYPE00) / sizeof (UINT32),
 165                                     Pci
 166                                     );
 167
 168     return EFI_SUCCESS;
 169   }
 170
 171   return EFI_NOT_FOUND;
 172 }
 173
 174 EFI_STATUS
 175 PciPciDeviceInfoCollector (
 176   IN PCI_IO_DEVICE                      *Bridge,
 177   UINT8                                 StartBusNumber
 178   )
 179 /*++
 180
 181 Routine Description:
 182
 183 Arguments:
 184
 185 Returns:
 186
 187   None
 188
 189 --*/
 190 {
 191   EFI_STATUS          Status;
 192   PCI_TYPE00          Pci;
 193   UINT8               Device;
 194   UINT8               Func;
 195   UINT8               SecBus;
 196   PCI_IO_DEVICE       *PciIoDevice;
 197   EFI_PCI_IO_PROTOCOL *PciIo;
 198
 199   Status  = EFI_SUCCESS;
 200   SecBus  = 0;
 201
 202   for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
 203
 204     for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
 205
 206       //
 207       // Check to see whether PCI device is present
 208       //
 209
 210       Status = PciDevicePresent (
 211                 Bridge->PciRootBridgeIo,
 212                 &Pci,
 213                 (UINT8) StartBusNumber,
 214                 (UINT8) Device,
 215                 (UINT8) Func
 216                 );
 217
 218       if (!EFI_ERROR (Status)) {
 219
 220         //
 221         // Collect all the information about the PCI device discovered
 222         //
 223         Status = PciSearchDevice (
 224                   Bridge,
 225                   &Pci,
 226                   (UINT8) StartBusNumber,
 227                   Device,
 228                   Func,
 229                   &PciIoDevice
 230                   );
 231
 232         //
 233         // Recursively scan PCI busses on the other side of PCI-PCI bridges
 234         //
 235         //
 236
 237         if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {
 238
 239           //
 240           // If it is PPB, we need to get the secondary bus to continue the enumeration
 241           //
 242           PciIo   = &(PciIoDevice->PciIo);
 243
 244           Status  = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &SecBus);
 245
 246           if (EFI_ERROR (Status)) {
 247             return Status;
 248           }
 249
 250           //
 251           // Deep enumerate the next level bus
 252           //
 253           Status = PciPciDeviceInfoCollector (
 254                     PciIoDevice,
 255                     (UINT8) (SecBus)
 256                     );
 257
 258         }
 259
 260         if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
 261
 262           //
 263           // Skip sub functions, this is not a multi function device
 264           //
 265           Func = PCI_MAX_FUNC;
 266         }
 267       }
 268
 269     }
 270   }
 271
 272   return EFI_SUCCESS;
 273 }
 274
 275 EFI_STATUS
 276 PciSearchDevice (
 277   IN  PCI_IO_DEVICE                         *Bridge,
 278   IN  PCI_TYPE00                            *Pci,
 279   IN  UINT8                                 Bus,
 280   IN  UINT8                                 Device,
 281   IN  UINT8                                 Func,
 282   OUT PCI_IO_DEVICE                         **PciDevice
 283   )
 284 /*++
 285
 286 Routine Description:
 287
 288   Search required device.
 289
 290 Arguments:
 291
 292   Bridge     - A pointer to the PCI_IO_DEVICE.
 293   Pci        - A pointer to the PCI_TYPE00.
 294   Bus        - Bus number.
 295   Device     - Device number.
 296   Func       - Function number.
 297   PciDevice  - The Required pci device.
 298
 299 Returns:
 300
 301   Status code.
 302
 303 --*/
 304 {
 305   PCI_IO_DEVICE *PciIoDevice;
 306
 307   PciIoDevice = NULL;
 308
 309   if (!IS_PCI_BRIDGE (Pci)) {
 310
 311     if (IS_CARDBUS_BRIDGE (Pci)) {
 312       PciIoDevice = GatherP2CInfo (
 313                       Bridge->PciRootBridgeIo,
 314                       Pci,
 315                       Bus,
 316                       Device,
 317                       Func
 318                       );
 319       if ((PciIoDevice != NULL) && (gFullEnumeration == TRUE)) {
 320         InitializeP2C (PciIoDevice);
 321       }
 322     } else {
 323
 324       //
 325       // Create private data for Pci Device
 326       //
 327       PciIoDevice = GatherDeviceInfo (
 328                       Bridge->PciRootBridgeIo,
 329                       Pci,
 330                       Bus,
 331                       Device,
 332                       Func
 333                       );
 334
 335     }
 336
 337   } else {
 338
 339     //
 340     // Create private data for PPB
 341     //
 342     PciIoDevice = GatherPPBInfo (
 343                     Bridge->PciRootBridgeIo,
 344                     Pci,
 345                     Bus,
 346                     Device,
 347                     Func
 348                     );
 349
 350     //
 351     // Special initialization for PPB including making the PPB quiet
 352     //
 353     if ((PciIoDevice != NULL) && (gFullEnumeration == TRUE)) {
 354       InitializePPB (PciIoDevice);
 355     }
 356   }
 357
 358   if (!PciIoDevice) {
 359     return EFI_OUT_OF_RESOURCES;
 360   }
 361
 362   //
 363   // Create a device path for this PCI device and store it into its private data
 364   //
 365   CreatePciDevicePath(
 366     Bridge->DevicePath,
 367     PciIoDevice
 368     );
 369
 370   //
 371   // Detect this function has option rom
 372   //
 373   if (gFullEnumeration) {
 374
 375     if (!IS_CARDBUS_BRIDGE (Pci)) {
 376
 377       GetOpRomInfo (PciIoDevice);
 378
 379     }
 380
 381     ResetPowerManagementFeature (PciIoDevice);
 382
 383   }
 384   else {
 385     PciRomGetRomResourceFromPciOptionRomTable (
 386       &gPciBusDriverBinding,
 387       PciIoDevice->PciRootBridgeIo,
 388       PciIoDevice
 389       );
 390   }
 391
 392
 393   //
 394   // Insert it into a global tree for future reference
 395   //
 396   InsertPciDevice (Bridge, PciIoDevice);
 397
 398   //
 399   // Determine PCI device attributes
 400   //
 401   DetermineDeviceAttribute (PciIoDevice);
 402
 403   if (PciDevice != NULL) {
 404     *PciDevice = PciIoDevice;
 405   }
 406
 407   return EFI_SUCCESS;
 408 }
 409
 410 PCI_IO_DEVICE *
 411 GatherDeviceInfo (
 412   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *PciRootBridgeIo,
 413   IN PCI_TYPE00                       *Pci,
 414   UINT8                               Bus,
 415   UINT8                               Device,
 416   UINT8                               Func
 417   )
 418 /*++
 419
 420 Routine Description:
 421
 422 Arguments:
 423
 424 Returns:
 425
 426   None
 427
 428 --*/
 429 {
 430   UINTN                           Offset;
 431   UINTN                           BarIndex;
 432   PCI_IO_DEVICE                   *PciIoDevice;
 433
 434   PciIoDevice = CreatePciIoDevice (
 435                   PciRootBridgeIo,
 436                   Pci,
 437                   Bus,
 438                   Device,
 439                   Func
 440                   );
 441
 442   if (!PciIoDevice) {
 443     return NULL;
 444   }
 445
 446   //
 447   // If it is a full enumeration, disconnect the device in advance
 448   //
 449   if (gFullEnumeration) {
 450
 451     PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
 452
 453   }
 454
 455   //
 456   // Start to parse the bars
 457   //
 458   for (Offset = 0x10, BarIndex = 0; Offset <= 0x24; BarIndex++) {
 459     Offset = PciParseBar (PciIoDevice, Offset, BarIndex);
 460   }
 461
 462   return PciIoDevice;
 463 }
 464
 465 PCI_IO_DEVICE *
 466 GatherPPBInfo (
 467   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *PciRootBridgeIo,
 468   IN PCI_TYPE00                       *Pci,
 469   UINT8                               Bus,
 470   UINT8                               Device,
 471   UINT8                               Func
 472   )
 473 /*++
 474
 475 Routine Description:
 476
 477 Arguments:
 478
 479 Returns:
 480
 481   None
 482
 483 --*/
 484 {
 485   PCI_IO_DEVICE                   *PciIoDevice;
 486   EFI_STATUS                      Status;
 487   UINT8                           Value;
 488   EFI_PCI_IO_PROTOCOL             *PciIo;
 489   UINT8                           Temp;
 490
 491   PciIoDevice = CreatePciIoDevice (
 492                   PciRootBridgeIo,
 493                   Pci,
 494                   Bus,
 495                   Device,
 496                   Func
 497                   );
 498
 499   if (!PciIoDevice) {
 500     return NULL;
 501   }
 502
 503   if (gFullEnumeration) {
 504     PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
 505
 506     //
 507     // Initalize the bridge control register
 508     //
 509     PciDisableBridgeControlRegister (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);
 510   }
 511
 512   PciIo = &PciIoDevice->PciIo;
 513
 514   //
 515   // Test whether it support 32 decode or not
 516   //
 517   PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
 518   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
 519   PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);
 520   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
 521
 522   if (Value) {
 523     if (Value & 0x01) {
 524       PciIoDevice->Decodes |= EFI_BRIDGE_IO32_DECODE_SUPPORTED;
 525     } else {
 526       PciIoDevice->Decodes |= EFI_BRIDGE_IO16_DECODE_SUPPORTED;
 527     }
 528   }
 529
 530   Status = BarExisted (
 531             PciIoDevice,
 532             0x24,
 533             NULL,
 534             NULL
 535             );
 536
 537   //
 538   // test if it supports 64 memory or not
 539   //
 540   if (!EFI_ERROR (Status)) {
 541
 542     Status = BarExisted (
 543               PciIoDevice,
 544               0x28,
 545               NULL,
 546               NULL
 547               );
 548
 549     if (!EFI_ERROR (Status)) {
 550       PciIoDevice->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;
 551       PciIoDevice->Decodes |= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED;
 552     } else {
 553       PciIoDevice->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;
 554     }
 555   }
 556
 557   //
 558   // Memory 32 code is required for ppb
 559   //
 560   PciIoDevice->Decodes |= EFI_BRIDGE_MEM32_DECODE_SUPPORTED;
 561
 562   return PciIoDevice;
 563 }
 564
 565 PCI_IO_DEVICE *
 566 GatherP2CInfo (
 567   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *PciRootBridgeIo,
 568   IN PCI_TYPE00                       *Pci,
 569   UINT8                               Bus,
 570   UINT8                               Device,
 571   UINT8                               Func
 572   )
 573 /*++
 574
 575 Routine Description:
 576
 577 Arguments:
 578
 579 Returns:
 580
 581   None
 582
 583 --*/
 584 {
 585   PCI_IO_DEVICE         *PciIoDevice;
 586
 587   PciIoDevice = CreatePciIoDevice (
 588                   PciRootBridgeIo,
 589                   Pci,
 590                   Bus,
 591                   Device,
 592                   Func
 593                   );
 594
 595   if (!PciIoDevice) {
 596     return NULL;
 597   }
 598
 599   if (gFullEnumeration) {
 600     PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
 601
 602     //
 603     // Initalize the bridge control register
 604     //
 605     PciDisableBridgeControlRegister (PciIoDevice, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED);
 606
 607   }
 608   //
 609   // P2C only has one bar that is in 0x10
 610   //
 611   PciParseBar(PciIoDevice, 0x10, 0);
 612
 613   PciIoDevice->Decodes = EFI_BRIDGE_MEM32_DECODE_SUPPORTED  |
 614                          EFI_BRIDGE_PMEM32_DECODE_SUPPORTED |
 615                          EFI_BRIDGE_IO32_DECODE_SUPPORTED;
 616
 617   return PciIoDevice;
 618 }
 619
 620 EFI_DEVICE_PATH_PROTOCOL *
 621 CreatePciDevicePath (
 622   IN  EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
 623   IN  PCI_IO_DEVICE            *PciIoDevice
 624   )
 625 /*++
 626
 627 Routine Description:
 628
 629 Arguments:
 630
 631 Returns:
 632
 633   None
 634
 635 --*/
 636 {
 637
 638   PCI_DEVICE_PATH PciNode;
 639
 640   //
 641   // Create PCI device path
 642   //
 643   PciNode.Header.Type     = HARDWARE_DEVICE_PATH;
 644   PciNode.Header.SubType  = HW_PCI_DP;
 645   SetDevicePathNodeLength (&PciNode.Header, sizeof (PciNode));
 646
 647   PciNode.Device          = PciIoDevice->DeviceNumber;
 648   PciNode.Function        = PciIoDevice->FunctionNumber;
 649   PciIoDevice->DevicePath = AppendDevicePathNode (ParentDevicePath, &PciNode.Header);
 650
 651   return PciIoDevice->DevicePath;
 652 }
 653
 654 EFI_STATUS
 655 BarExisted (
 656   IN PCI_IO_DEVICE *PciIoDevice,
 657   IN UINTN         Offset,
 658   OUT UINT32       *BarLengthValue,
 659   OUT UINT32       *OriginalBarValue
 660   )
 661 /*++
 662
 663 Routine Description:
 664
 665   Check the bar is existed or not.
 666
 667 Arguments:
 668
 669   PciIoDevice       - A pointer to the PCI_IO_DEVICE.
 670   Offset            - The offset.
 671   BarLengthValue    - The bar length value.
 672   OriginalBarValue  - The original bar value.
 673
 674 Returns:
 675
 676   EFI_NOT_FOUND     - The bar don't exist.
 677   EFI_SUCCESS       - The bar exist.
 678
 679 --*/
 680 {
 681   EFI_PCI_IO_PROTOCOL *PciIo;
 682   UINT32              OriginalValue;
 683   UINT32              Value;
 684   EFI_TPL             OldTpl;
 685
 686   PciIo = &PciIoDevice->PciIo;
 687
 688   //
 689   // Preserve the original value
 690   //
 691
 692   PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
 693
 694   //
 695   // Raise TPL to high level to disable timer interrupt while the BAR is probed
 696   //
 697   OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
 698
 699   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);
 700   PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);
 701
 702   //
 703   // Write back the original value
 704   //
 705   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
 706
 707   //
 708   // Restore TPL to its original level
 709   //
 710   gBS->RestoreTPL (OldTpl);
 711
 712   if (BarLengthValue != NULL) {
 713     *BarLengthValue = Value;
 714   }
 715
 716   if (OriginalBarValue != NULL) {
 717     *OriginalBarValue = OriginalValue;
 718   }
 719
 720   if (Value == 0) {
 721     return EFI_NOT_FOUND;
 722   } else {
 723     return EFI_SUCCESS;
 724   }
 725 }
 726
 727
 728 EFI_STATUS
 729 DetermineDeviceAttribute (
 730   IN PCI_IO_DEVICE                      *PciIoDevice
 731   )
 732 /*++
 733
 734 Routine Description:
 735
 736   Determine the related attributes of all devices under a Root Bridge
 737
 738 Arguments:
 739
 740 Returns:
 741
 742   None
 743
 744 --*/
 745 {
 746   UINT16          Command;
 747   UINT16          BridgeControl;
 748
 749   Command = 0;
 750
 751   PciIoDevice->Supports |= EFI_PCI_DEVICE_ENABLE;
 752   PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE;
 753
 754   if (IS_PCI_VGA (&(PciIoDevice->Pci))){
 755
 756     //
 757     // If the device is VGA, VGA related Attributes are supported
 758     //
 759     PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO ;
 760     PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY   ;
 761     PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_VGA_IO    ;
 762   }
 763
 764   if(IS_ISA_BRIDGE(&(PciIoDevice->Pci)) || IS_INTEL_ISA_BRIDGE(&(PciIoDevice->Pci))) {
 765     //
 766     // If the devie is a ISA Bridge, set the two attributes
 767     //
 768     PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO;
 769     PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_ISA_IO;
 770   }
 771
 772   if (IS_PCI_GFX (&(PciIoDevice->Pci))) {
 773
 774     //
 775     // If the device is GFX, then only set the EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
 776     // attribute
 777     //
 778     PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO    ;
 779   }
 780
 781
 782   //
 783   // If the device is IDE, IDE related attributes are supported
 784   //
 785   if (IS_PCI_IDE (&(PciIoDevice->Pci))) {
 786     PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO  ;
 787     PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO  ;
 788   }
 789
 790   PciReadCommandRegister(PciIoDevice, &Command);
 791
 792
 793   if (Command & EFI_PCI_COMMAND_IO_SPACE) {
 794     PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_IO;
 795   }
 796
 797   if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {
 798     PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_MEMORY;
 799   }
 800
 801   if (Command & EFI_PCI_COMMAND_BUS_MASTER) {
 802     PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_BUS_MASTER;
 803   }
 804
 805   if (IS_PCI_BRIDGE (&(PciIoDevice->Pci)) ||
 806       IS_CARDBUS_BRIDGE (&(PciIoDevice->Pci))){
 807
 808     //
 809     // If it is a PPB, read the Bridge Control Register to determine
 810     // the relevant attributes
 811     //
 812     BridgeControl = 0;
 813     PciReadBridgeControlRegister(PciIoDevice, &BridgeControl);
 814
 815     //
 816     // Determine whether the ISA bit is set
 817     // If ISA Enable on Bridge is set, the PPB
 818     // will block forwarding 0x100-0x3ff for each 1KB in the
 819     // first 64KB I/O range.
 820     //
 821     if ((BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA) != 0) {
 822       PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_IO;
 823     }
 824
 825     //
 826     // Determine whether the VGA bit is set
 827     // If it is set, the bridge is set to decode VGA memory range
 828     // and palette register range
 829     //
 830     if (IS_PCI_VGA (&(PciIoDevice->Pci)) &&BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA) {
 831       PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_IO;
 832       PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY;
 833       PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;
 834     }
 835
 836     //
 837     // if the palette snoop bit is set, then the brige is set to
 838     // decode palette IO write
 839     //
 840     if (Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) {
 841       PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;
 842     }
 843   }
 844
 845   return EFI_SUCCESS;
 846 }
 847
 848 UINTN
 849 PciParseBar (
 850   IN PCI_IO_DEVICE  *PciIoDevice,
 851   IN UINTN          Offset,
 852   IN UINTN          BarIndex
 853   )
 854 /*++
 855
 856 Routine Description:
 857
 858 Arguments:
 859
 860 Returns:
 861
 862   None
 863
 864 --*/
 865 {
 866   UINT32      Value;
 867   UINT32      OriginalValue;
 868   UINT32      Mask;
 869   EFI_STATUS  Status;
 870
 871   OriginalValue = 0;
 872   Value         = 0;
 873
 874   Status = BarExisted (
 875             PciIoDevice,
 876             Offset,
 877             &Value,
 878             &OriginalValue
 879             );
 880
 881   if (EFI_ERROR (Status)) {
 882     PciIoDevice->PciBar[BarIndex].BaseAddress = 0;
 883     PciIoDevice->PciBar[BarIndex].Length      = 0;
 884     PciIoDevice->PciBar[BarIndex].Alignment   = 0;
 885
 886     //
 887     // Some devices don't fully comply to PCI spec 2.2. So be to scan all the BARs anyway
 888     //
 889     PciIoDevice->PciBar[BarIndex].Offset = (UINT8) Offset;
 890     return Offset + 4;
 891   }
 892
 893   PciIoDevice->PciBar[BarIndex].Offset = (UINT8) Offset;
 894   if (Value & 0x01) {
 895     //
 896     // Device I/Os
 897     //
 898     Mask = 0xfffffffc;
 899
 900     if (Value & 0xFFFF0000) {
 901       //
 902       // It is a IO32 bar
 903       //
 904       PciIoDevice->PciBar[BarIndex].BarType   = PciBarTypeIo32;
 905       PciIoDevice->PciBar[BarIndex].Length    = ((~(Value & Mask)) + 1);
 906       PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
 907
 908     } else {
 909       //
 910       // It is a IO16 bar
 911       //
 912       PciIoDevice->PciBar[BarIndex].BarType   = PciBarTypeIo16;
 913       PciIoDevice->PciBar[BarIndex].Length    = 0x0000FFFF & ((~(Value & Mask)) + 1);
 914       PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
 915
 916     }
 917     //
 918     // Workaround. Some platforms inplement IO bar with 0 length
 919     // Need to treat it as no-bar
 920     //
 921     if (PciIoDevice->PciBar[BarIndex].Length == 0) {
 922       PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeUnknown;
 923     }
 924
 925     PciIoDevice->PciBar[BarIndex].Prefetchable  = FALSE;
 926     PciIoDevice->PciBar[BarIndex].BaseAddress   = OriginalValue & Mask;
 927
 928   } else {
 929
 930     Mask  = 0xfffffff0;
 931
 932     PciIoDevice->PciBar[BarIndex].BaseAddress = OriginalValue & Mask;
 933
 934     switch (Value & 0x07) {
 935
 936     //
 937     //memory space; anywhere in 32 bit address space
 938     //
 939     case 0x00:
 940       if (Value & 0x08) {
 941         PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem32;
 942       } else {
 943         PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem32;
 944       }
 945
 946       PciIoDevice->PciBar[BarIndex].Length    = (~(Value & Mask)) + 1;
 947       PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
 948
 949       break;
 950
 951     //
 952     // memory space; anywhere in 64 bit address space
 953     //
 954     case 0x04:
 955       if (Value & 0x08) {
 956         PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem64;
 957       } else {
 958         PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem64;
 959       }
 960
 961       //
 962       // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
 963       // is regarded as an extension for the first bar. As a result
 964       // the sizing will be conducted on combined 64 bit value
 965       // Here just store the masked first 32bit value for future size
 966       // calculation
 967       //
 968       PciIoDevice->PciBar[BarIndex].Length    = Value & Mask;
 969       PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
 970
 971       //
 972       // Increment the offset to point to next DWORD
 973       //
 974       Offset += 4;
 975
 976       Status = BarExisted (
 977                 PciIoDevice,
 978                 Offset,
 979                 &Value,
 980                 &OriginalValue
 981                 );
 982
 983       if (EFI_ERROR (Status)) {
 984         return Offset + 4;
 985       }
 986
 987       //
 988       // Fix the length to support some spefic 64 bit BAR
 989       //
 990       Value |= ((UINT32)(-1) << HighBitSet32 (Value));
 991
 992       //
 993       // Calculate the size of 64bit bar
 994       //
 995       PciIoDevice->PciBar[BarIndex].BaseAddress |= LShiftU64 ((UINT64) OriginalValue, 32);
 996
 997       PciIoDevice->PciBar[BarIndex].Length    = PciIoDevice->PciBar[BarIndex].Length | LShiftU64 ((UINT64) Value, 32);
 998       PciIoDevice->PciBar[BarIndex].Length    = (~(PciIoDevice->PciBar[BarIndex].Length)) + 1;
 999       PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
1000
1001       break;
1002
1003     //
1004     // reserved
1005     //
1006     default:
1007       PciIoDevice->PciBar[BarIndex].BarType   = PciBarTypeUnknown;
1008       PciIoDevice->PciBar[BarIndex].Length    = (~(Value & Mask)) + 1;
1009       PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
1010
1011       break;
1012     }
1013   }
1014
1015   //
1016   // Check the length again so as to keep compatible with some special bars
1017   //
1018   if (PciIoDevice->PciBar[BarIndex].Length == 0) {
1019     PciIoDevice->PciBar[BarIndex].BarType     = PciBarTypeUnknown;
1020     PciIoDevice->PciBar[BarIndex].BaseAddress = 0;
1021     PciIoDevice->PciBar[BarIndex].Alignment   = 0;
1022   }
1023
1024   //
1025   // Increment number of bar
1026   //
1027   return Offset + 4;
1028 }
1029
1030 EFI_STATUS
1031 InitializePPB (
1032   IN PCI_IO_DEVICE *PciIoDevice
1033   )
1034 /*++
1035
1036 Routine Description:
1037
1038 Arguments:
1039
1040 Returns:
1041
1042   None
1043
1044 --*/
1045 {
1046   EFI_PCI_IO_PROTOCOL *PciIo;
1047
1048   PciIo = &(PciIoDevice->PciIo);
1049
1050   //
1051   // Put all the resource apertures including IO16
1052   // Io32, pMem32, pMem64 to quiescent state
1053   // Resource base all ones, Resource limit all zeros
1054   //
1055   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
1056   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);
1057
1058   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);
1059   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);
1060
1061   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);
1062   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);
1063
1064   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);
1065   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);
1066
1067   //
1068   // don't support use io32 as for now
1069   //
1070   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);
1071   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);
1072
1073   return EFI_SUCCESS;
1074 }
1075
1076 EFI_STATUS
1077 InitializeP2C (
1078   IN PCI_IO_DEVICE *PciIoDevice
1079   )
1080 /*++
1081
1082 Routine Description:
1083
1084 Arguments:
1085
1086 Returns:
1087
1088   None
1089
1090 --*/
1091 {
1092   EFI_PCI_IO_PROTOCOL *PciIo;
1093
1094   PciIo = &(PciIoDevice->PciIo);
1095
1096   //
1097   // Put all the resource apertures including IO16
1098   // Io32, pMem32, pMem64 to quiescent state(
1099   // Resource base all ones, Resource limit all zeros
1100   //
1101   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);
1102   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);
1103
1104   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);
1105   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);
1106
1107   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);
1108   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);
1109
1110   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);
1111   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);
1112
1113   return EFI_SUCCESS;
1114 }
1115
1116 PCI_IO_DEVICE *
1117 CreatePciIoDevice (
1118   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *PciRootBridgeIo,
1119   IN PCI_TYPE00                       *Pci,
1120   UINT8                               Bus,
1121   UINT8                               Device,
1122   UINT8                               Func
1123   )
1124 /*++
1125
1126 Routine Description:
1127
1128 Arguments:
1129
1130 Returns:
1131
1132   None
1133
1134 --*/
1135 {
1136
1137   EFI_STATUS    Status;
1138   PCI_IO_DEVICE *PciIoDevice;
1139
1140   PciIoDevice = NULL;
1141
1142   Status = gBS->AllocatePool (
1143                   EfiBootServicesData,
1144                   sizeof (PCI_IO_DEVICE),
1145                   (VOID **) &PciIoDevice
1146                   );
1147
1148   if (EFI_ERROR (Status)) {
1149     return NULL;
1150   }
1151
1152   ZeroMem (PciIoDevice, sizeof (PCI_IO_DEVICE));
1153
1154   PciIoDevice->Signature        = PCI_IO_DEVICE_SIGNATURE;
1155   PciIoDevice->Handle           = NULL;
1156   PciIoDevice->PciRootBridgeIo  = PciRootBridgeIo;
1157   PciIoDevice->DevicePath       = NULL;
1158   PciIoDevice->BusNumber        = Bus;
1159   PciIoDevice->DeviceNumber     = Device;
1160   PciIoDevice->FunctionNumber   = Func;
1161   PciIoDevice->Decodes          = 0;
1162   if (gFullEnumeration) {
1163     PciIoDevice->Allocated = FALSE;
1164   } else {
1165     PciIoDevice->Allocated = TRUE;
1166   }
1167
1168   PciIoDevice->Attributes         = 0;
1169   PciIoDevice->Supports           = 0;
1170   PciIoDevice->BusOverride        = FALSE;
1171   PciIoDevice->IsPciExp           = FALSE;
1172
1173   CopyMem (&(PciIoDevice->Pci), Pci, sizeof (PCI_TYPE01));
1174
1175   //
1176   // Initialize the PCI I/O instance structure
1177   //
1178
1179   Status  = InitializePciIoInstance (PciIoDevice);
1180   Status  = InitializePciDriverOverrideInstance (PciIoDevice);
1181
1182   if (EFI_ERROR (Status)) {
1183     gBS->FreePool (PciIoDevice);
1184     return NULL;
1185   }
1186
1187   //
1188   // Initialize the reserved resource list
1189   //
1190   InitializeListHead (&PciIoDevice->ReservedResourceList);
1191
1192   //
1193   // Initialize the driver list
1194   //
1195   InitializeListHead (&PciIoDevice->OptionRomDriverList);
1196
1197   //
1198   // Initialize the child list
1199   //
1200   InitializeListHead (&PciIoDevice->ChildList);
1201
1202   return PciIoDevice;
1203 }
1204
1205 EFI_STATUS
1206 PciEnumeratorLight (
1207   IN EFI_HANDLE                    Controller
1208   )
1209 /*++
1210
1211 Routine Description:
1212
1213   This routine is used to enumerate entire pci bus system
1214   in a given platform
1215
1216 Arguments:
1217
1218 Returns:
1219
1220   None
1221
1222 --*/
1223 {
1224
1225   EFI_STATUS                        Status;
1226   EFI_DEVICE_PATH_PROTOCOL          *ParentDevicePath;
1227   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL   *PciRootBridgeIo;
1228   PCI_IO_DEVICE                     *RootBridgeDev;
1229   UINT16                            MinBus;
1230   UINT16                            MaxBus;
1231   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
1232
1233   MinBus      = 0;
1234   MaxBus      = PCI_MAX_BUS;
1235   Descriptors = NULL;
1236
1237   //
1238   // If this host bridge has been already enumerated, then return successfully
1239   //
1240   if (RootBridgeExisted (Controller)) {
1241     return EFI_SUCCESS;
1242   }
1243
1244   //
1245   // Open the IO Abstraction(s) needed to perform the supported test
1246   //
1247   Status = gBS->OpenProtocol (
1248                   Controller      ,
1249                   &gEfiDevicePathProtocolGuid,
1250                   (VOID **)&ParentDevicePath,
1251                   gPciBusDriverBinding.DriverBindingHandle,
1252                   Controller,
1253                   EFI_OPEN_PROTOCOL_BY_DRIVER
1254                   );
1255   if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {
1256     return Status;
1257   }
1258
1259   //
1260   // Open pci root bridge io protocol
1261   //
1262   Status = gBS->OpenProtocol (
1263                   Controller,
1264                   &gEfiPciRootBridgeIoProtocolGuid,
1265                   (VOID **) &PciRootBridgeIo,
1266                   gPciBusDriverBinding.DriverBindingHandle,
1267                   Controller,
1268                   EFI_OPEN_PROTOCOL_BY_DRIVER
1269                   );
1270   if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {
1271     return Status;
1272   }
1273
1274   //
1275   // Load all EFI Drivers from all PCI Option ROMs behind the PCI Root Bridge
1276   //
1277   Status = PciRomLoadEfiDriversFromOptionRomTable (&gPciBusDriverBinding, PciRootBridgeIo);
1278
1279   Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **) &Descriptors);
1280
1281   if (EFI_ERROR (Status)) {
1282     return Status;
1283   }
1284
1285   while (PciGetBusRange (&Descriptors, &MinBus, &MaxBus, NULL) == EFI_SUCCESS) {
1286
1287     //
1288     // Create a device node for root bridge device with a NULL host bridge controller handle
1289     //
1290     RootBridgeDev = CreateRootBridge (Controller);
1291
1292     //
1293     // Record the root bridge device path
1294     //
1295     RootBridgeDev->DevicePath = ParentDevicePath;
1296
1297     //
1298     // Record the root bridge io protocol
1299     //
1300     RootBridgeDev->PciRootBridgeIo = PciRootBridgeIo;
1301
1302     Status = PciPciDeviceInfoCollector (
1303               RootBridgeDev,
1304               (UINT8) MinBus
1305               );
1306
1307     if (!EFI_ERROR (Status)) {
1308
1309       //
1310       // If successfully, insert the node into device pool
1311       //
1312       InsertRootBridge (RootBridgeDev);
1313     } else {
1314
1315       //
1316       // If unsuccessly, destroy the entire node
1317       //
1318       DestroyRootBridge (RootBridgeDev);
1319     }
1320
1321     Descriptors++;
1322   }
1323
1324   return EFI_SUCCESS;
1325 }
1326
1327 EFI_STATUS
1328 PciGetBusRange (
1329   IN     EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  **Descriptors,
1330   OUT    UINT16                             *MinBus,
1331   OUT    UINT16                             *MaxBus,
1332   OUT    UINT16                             *BusRange
1333   )
1334 /*++
1335
1336 Routine Description:
1337
1338   Get the bus range.
1339
1340 Arguments:
1341
1342   Descriptors     - A pointer to the address space descriptor.
1343   MinBus          - The min bus.
1344   MaxBus          - The max bus.
1345   BusRange        - The bus range.
1346
1347 Returns:
1348
1349   Status Code.
1350
1351 --*/
1352 {
1353
1354   while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {
1355     if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {
1356       if (MinBus != NULL) {
1357         *MinBus = (UINT16)(*Descriptors)->AddrRangeMin;
1358       }
1359
1360       if (MaxBus != NULL) {
1361         *MaxBus = (UINT16)(*Descriptors)->AddrRangeMax;
1362       }
1363
1364       if (BusRange != NULL) {
1365         *BusRange = (UINT16)(*Descriptors)->AddrLen;
1366       }
1367       return EFI_SUCCESS;
1368     }
1369
1370     (*Descriptors)++;
1371   }
1372
1373   return EFI_NOT_FOUND;
1374 }
1375