3 Copyright (c) 2005 - 2008, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 EFI PC AT PCI Root Bridge Io Protocol
23 #include "PcatPciRootBridge.h"
25 BOOLEAN mPciOptionRomTableInstalled
= FALSE
;
26 EFI_PCI_OPTION_ROM_TABLE mPciOptionRomTable
= {0, NULL
};
30 PcatRootBridgeIoIoRead (
31 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
32 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
33 IN UINT64 UserAddress
,
35 IN OUT VOID
*UserBuffer
38 return gCpuIo
->Io
.Read (
40 (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
49 PcatRootBridgeIoIoWrite (
50 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
51 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
52 IN UINT64 UserAddress
,
54 IN OUT VOID
*UserBuffer
57 return gCpuIo
->Io
.Write (
59 (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
68 PcatRootBridgeIoGetIoPortMapping (
69 OUT EFI_PHYSICAL_ADDRESS
*IoPortMapping
,
70 OUT EFI_PHYSICAL_ADDRESS
*MemoryPortMapping
74 Get the IO Port Mapping. For IA-32 it is always 0.
79 *MemoryPortMapping
= 0;
85 PcatRootBridgeIoPciRW (
86 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
88 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
89 IN UINT64 UserAddress
,
91 IN OUT VOID
*UserBuffer
94 PCI_CONFIG_ACCESS_CF8 Pci
;
95 PCI_CONFIG_ACCESS_CF8 PciAligned
;
100 PCAT_PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
101 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress
;
102 UINT64 PciExpressRegAddr
;
103 BOOLEAN UsePciExpressAccess
;
105 if (Width
< 0 || Width
>= EfiPciWidthMaximum
) {
106 return EFI_INVALID_PARAMETER
;
109 if ((Width
& 0x03) >= EfiPciWidthUint64
) {
110 return EFI_INVALID_PARAMETER
;
113 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This
);
115 InStride
= 1 << (Width
& 0x03);
116 OutStride
= InStride
;
117 if (Width
>= EfiCpuIoWidthFifoUint8
&& Width
<= EfiCpuIoWidthFifoUint64
) {
121 if (Width
>= EfiCpuIoWidthFillUint8
&& Width
<= EfiCpuIoWidthFillUint64
) {
125 UsePciExpressAccess
= FALSE
;
127 CopyMem (&PciAddress
, &UserAddress
, sizeof(UINT64
));
129 if (PciAddress
.ExtendedRegister
> 0xFF) {
131 // Check PciExpressBaseAddress
133 if ((PrivateData
->PciExpressBaseAddress
== 0) ||
134 (PrivateData
->PciExpressBaseAddress
>= EFI_MAX_ADDRESS
)) {
135 return EFI_UNSUPPORTED
;
137 UsePciExpressAccess
= TRUE
;
140 if (PciAddress
.ExtendedRegister
!= 0) {
141 Pci
.Bits
.Reg
= PciAddress
.ExtendedRegister
& 0xFF;
143 Pci
.Bits
.Reg
= PciAddress
.Register
;
146 // Note: We can also use PciExpress access here, if wanted.
150 if (!UsePciExpressAccess
) {
151 Pci
.Bits
.Func
= PciAddress
.Function
;
152 Pci
.Bits
.Dev
= PciAddress
.Device
;
153 Pci
.Bits
.Bus
= PciAddress
.Bus
;
154 Pci
.Bits
.Reserved
= 0;
158 // PCI Config access are all 32-bit alligned, but by accessing the
159 // CONFIG_DATA_REGISTER (0xcfc) with different widths more cycle types
160 // are possible on PCI.
162 // To read a byte of PCI config space you load 0xcf8 and
163 // read 0xcfc, 0xcfd, 0xcfe, 0xcff
165 PciDataStride
= Pci
.Bits
.Reg
& 0x03;
169 PciAligned
.Bits
.Reg
&= 0xfc;
170 PciData
= (UINTN
)PrivateData
->PciData
+ PciDataStride
;
171 EfiAcquireLock(&PrivateData
->PciLock
);
172 This
->Io
.Write (This
, EfiPciWidthUint32
, PrivateData
->PciAddress
, 1, &PciAligned
);
174 This
->Io
.Write (This
, Width
, PciData
, 1, UserBuffer
);
176 This
->Io
.Read (This
, Width
, PciData
, 1, UserBuffer
);
178 EfiReleaseLock(&PrivateData
->PciLock
);
179 UserBuffer
= ((UINT8
*)UserBuffer
) + OutStride
;
180 PciDataStride
= (PciDataStride
+ InStride
) % 4;
181 Pci
.Bits
.Reg
+= InStride
;
186 // Access PCI-Express space by using memory mapped method.
188 PciExpressRegAddr
= (PrivateData
->PciExpressBaseAddress
) |
189 (PciAddress
.Bus
<< 20) |
190 (PciAddress
.Device
<< 15) |
191 (PciAddress
.Function
<< 12);
192 if (PciAddress
.ExtendedRegister
!= 0) {
193 PciExpressRegAddr
+= PciAddress
.ExtendedRegister
;
195 PciExpressRegAddr
+= PciAddress
.Register
;
199 This
->Mem
.Write (This
, Width
, (UINTN
) PciExpressRegAddr
, 1, UserBuffer
);
201 This
->Mem
.Read (This
, Width
, (UINTN
) PciExpressRegAddr
, 1, UserBuffer
);
204 UserBuffer
= ((UINT8
*) UserBuffer
) + OutStride
;
205 PciExpressRegAddr
+= InStride
;
215 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
222 EFI_PCI_BUS_SCAN_CALLBACK Callback
,
231 PCI_TYPE00 PciHeader
;
234 // Loop through all busses
236 for (Bus
= MinBus
; Bus
<= MaxBus
; Bus
++) {
238 // Loop 32 devices per bus
240 for (Device
= MinDevice
; Device
<= MaxDevice
; Device
++) {
242 // Loop through 8 functions per device
244 for (Func
= MinFunc
; Func
<= MaxFunc
; Func
++) {
247 // Compute the EFI Address required to access the PCI Configuration Header of this PCI Device
249 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
252 // Read the VendorID from this PCI Device's Confioguration Header
254 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, Address
, 1, &PciHeader
.Hdr
.VendorId
);
257 // If VendorId = 0xffff, there does not exist a device at this
258 // location. For each device, if there is any function on it,
259 // there must be 1 function at Function 0. So if Func = 0, there
260 // will be no more functions in the same device, so we can break
261 // loop to deal with the next device.
263 if (PciHeader
.Hdr
.VendorId
== 0xffff && Func
== 0) {
267 if (PciHeader
.Hdr
.VendorId
!= 0xffff) {
270 // Read the HeaderType to determine if this is a multi-function device
272 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint8
, Address
+ 0x0e, 1, &PciHeader
.Hdr
.HeaderType
);
275 // Call the callback function for the device that was found
280 MinDevice
, MaxDevice
,
289 // If this is not a multi-function device, we can leave the loop
290 // to deal with the next device.
292 if ((PciHeader
.Hdr
.HeaderType
& HEADER_TYPE_MULTI_FUNCTION
) == 0x00 && Func
== 0) {
303 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
317 PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT
*Context
;
319 PCI_TYPE00 PciHeader
;
320 PCI_TYPE01
*PciBridgeHeader
;
324 EFI_PHYSICAL_ADDRESS RomBuffer
;
326 EFI_PCI_EXPANSION_ROM_HEADER EfiRomHeader
;
327 PCI_DATA_STRUCTURE Pcir
;
328 EFI_PCI_OPTION_ROM_DESCRIPTOR
*TempPciOptionRomDescriptors
;
331 Context
= (PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT
*)VoidContext
;
333 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
336 // Save the contents of the PCI Configuration Header
338 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, Address
, sizeof(PciHeader
)/sizeof(UINT32
), &PciHeader
);
340 if (IS_PCI_BRIDGE(&PciHeader
)) {
342 PciBridgeHeader
= (PCI_TYPE01
*)(&PciHeader
);
345 // See if the PCI-PCI Bridge has its secondary interface enabled.
347 if (PciBridgeHeader
->Bridge
.SubordinateBus
>= PciBridgeHeader
->Bridge
.SecondaryBus
) {
350 // Disable the Prefetchable Memory Window
352 Register
= 0x00000000;
353 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
+ 0x26, 1, &Register
);
354 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, Address
+ 0x2c, 1, &Register
);
355 Register
= 0xffffffff;
356 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
+ 0x24, 1, &Register
);
357 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
+ 0x28, 1, &Register
);
360 // Program Memory Window to the PCI Root Bridge Memory Window
362 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
+ 0x20, 4, &Context
->PpbMemoryWindow
);
365 // Enable the Memory decode for the PCI-PCI Bridge
367 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, Address
+ 4, 1, &Register
);
369 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
+ 4, 1, &Register
);
372 // Recurse on the Secondary Bus Number
376 PciBridgeHeader
->Bridge
.SecondaryBus
, PciBridgeHeader
->Bridge
.SecondaryBus
,
385 // Check if an Option ROM Register is present and save the Option ROM Window Register
388 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, Address
+ 0x30, 1, &RomBar
);
389 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, Address
+ 0x30, 1, &RomBar
);
391 RomBarSize
= (~(RomBar
& 0xfffff800)) + 1;
394 // Make sure the size of the ROM is between 0 and 16 MB
396 if (RomBarSize
> 0 && RomBarSize
<= 0x01000000) {
399 // Program Option ROM Window Register to the PCI Root Bridge Window and Enable the Option ROM Window
401 RomBar
= (Context
->PpbMemoryWindow
& 0xffff) << 16;
402 RomBar
= ((RomBar
- 1) & (~(RomBarSize
- 1))) + RomBarSize
;
403 if (RomBar
< (Context
->PpbMemoryWindow
& 0xffff0000)) {
404 MaxRomSize
= (Context
->PpbMemoryWindow
& 0xffff0000) - RomBar
;
406 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, Address
+ 0x30, 1, &RomBar
);
407 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, Address
+ 0x30, 1, &RomBar
);
411 // Enable the Memory decode for the PCI Device
413 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, Address
+ 4, 1, &Register
);
415 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
+ 4, 1, &Register
);
418 // Follow the chain of images to determine the size of the Option ROM present
419 // Keep going until the last image is found by looking at the Indicator field
420 // or the size of an image is 0, or the size of all the images is bigger than the
421 // size of the window programmed into the PPB.
428 ZeroMem (&EfiRomHeader
, sizeof(EfiRomHeader
));
433 sizeof(EfiRomHeader
),
437 Pcir
.ImageLength
= 0;
439 if (EfiRomHeader
.Signature
== 0xaa55) {
441 ZeroMem (&Pcir
, sizeof(Pcir
));
445 RomBar
+ RomBarSize
+ EfiRomHeader
.PcirOffset
,
450 if ((Pcir
.Indicator
& 0x80) == 0x00) {
454 RomBarSize
+= Pcir
.ImageLength
* 512;
456 } while (!LastImage
&& RomBarSize
< MaxRomSize
&& Pcir
.ImageLength
!=0);
458 if (RomBarSize
> 0) {
461 // Allocate a memory buffer for the Option ROM contents.
463 Status
= gBS
->AllocatePages(
466 EFI_SIZE_TO_PAGES(RomBarSize
),
470 if (!EFI_ERROR (Status
)) {
473 // Copy the contents of the Option ROM to the memory buffer
475 IoDev
->Mem
.Read (IoDev
, EfiPciWidthUint32
, RomBar
, RomBarSize
/ sizeof(UINT32
), (VOID
*)(UINTN
)RomBuffer
);
477 Status
= gBS
->AllocatePool(
479 ((UINT32
)mPciOptionRomTable
.PciOptionRomCount
+ 1) * sizeof(EFI_PCI_OPTION_ROM_DESCRIPTOR
),
480 (VOID
*)&TempPciOptionRomDescriptors
482 if (mPciOptionRomTable
.PciOptionRomCount
> 0) {
484 TempPciOptionRomDescriptors
,
485 mPciOptionRomTable
.PciOptionRomDescriptors
,
486 (UINT32
)mPciOptionRomTable
.PciOptionRomCount
* sizeof(EFI_PCI_OPTION_ROM_DESCRIPTOR
)
489 gBS
->FreePool(mPciOptionRomTable
.PciOptionRomDescriptors
);
492 mPciOptionRomTable
.PciOptionRomDescriptors
= TempPciOptionRomDescriptors
;
494 TempPciOptionRomDescriptors
= &(mPciOptionRomTable
.PciOptionRomDescriptors
[(UINT32
)mPciOptionRomTable
.PciOptionRomCount
]);
496 TempPciOptionRomDescriptors
->RomAddress
= RomBuffer
;
497 TempPciOptionRomDescriptors
->MemoryType
= EfiBootServicesData
;
498 TempPciOptionRomDescriptors
->RomLength
= RomBarSize
;
499 TempPciOptionRomDescriptors
->Seg
= (UINT32
)IoDev
->SegmentNumber
;
500 TempPciOptionRomDescriptors
->Bus
= (UINT8
)Bus
;
501 TempPciOptionRomDescriptors
->Dev
= (UINT8
)Device
;
502 TempPciOptionRomDescriptors
->Func
= (UINT8
)Func
;
503 TempPciOptionRomDescriptors
->ExecutedLegacyBiosImage
= TRUE
;
504 TempPciOptionRomDescriptors
->DontLoadEfiRom
= FALSE
;
506 mPciOptionRomTable
.PciOptionRomCount
++;
511 // Disable the Memory decode for the PCI-PCI Bridge
513 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, Address
+ 4, 1, &Register
);
515 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
+ 4, 1, &Register
);
521 // Restore the PCI Configuration Header
523 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, Address
, sizeof(PciHeader
)/sizeof(UINT32
), &PciHeader
);
527 SaveCommandRegister (
528 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
542 PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT
*Context
;
547 Context
= (PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT
*)VoidContext
;
549 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 4);
551 Index
= (Bus
- MinBus
) * (PCI_MAX_DEVICE
+1) * (PCI_MAX_FUNC
+1) + Device
* (PCI_MAX_FUNC
+1) + Func
;
553 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, Address
, 1, &Context
->CommandRegisterBuffer
[Index
]);
556 // Clear the memory enable bit
558 Command
= Context
->CommandRegisterBuffer
[Index
] & (~0x02);
560 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
, 1, &Command
);
564 RestoreCommandRegister (
565 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
579 PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT
*Context
;
583 Context
= (PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT
*)VoidContext
;
585 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 4);
587 Index
= (Bus
- MinBus
) * (PCI_MAX_DEVICE
+1) * (PCI_MAX_FUNC
+1) + Device
* (PCI_MAX_FUNC
+1) + Func
;
589 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
, 1, &Context
->CommandRegisterBuffer
[Index
]);
593 ScanPciRootBridgeForRoms(
594 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
599 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
602 UINT64 RootWindowBase
;
603 UINT64 RootWindowLimit
;
604 PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT Context
;
606 if (mPciOptionRomTableInstalled
== FALSE
) {
607 gBS
->InstallConfigurationTable(&gEfiPciOptionRomTableGuid
, &mPciOptionRomTable
);
608 mPciOptionRomTableInstalled
= TRUE
;
611 Status
= IoDev
->Configuration(IoDev
, (VOID
**)&Descriptors
);
612 if (EFI_ERROR (Status
) || Descriptors
== NULL
) {
613 return EFI_NOT_FOUND
;
620 while (Descriptors
->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
624 if (Descriptors
->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
625 MinBus
= (UINT16
)Descriptors
->AddrRangeMin
;
626 MaxBus
= (UINT16
)Descriptors
->AddrRangeMax
;
629 // Find memory descriptors that are not prefetchable
631 if (Descriptors
->ResType
== ACPI_ADDRESS_SPACE_TYPE_MEM
&& Descriptors
->SpecificFlag
== 0) {
633 // Find Memory Descriptors that are less than 4GB, so the PPB Memory Window can be used for downstream devices
635 if (Descriptors
->AddrRangeMax
< 0x100000000ULL
) {
637 // Find the largest Non-Prefetchable Memory Descriptor that is less than 4GB
639 if ((Descriptors
->AddrRangeMax
- Descriptors
->AddrRangeMin
) > (RootWindowLimit
- RootWindowBase
)) {
640 RootWindowBase
= Descriptors
->AddrRangeMin
;
641 RootWindowLimit
= Descriptors
->AddrRangeMax
;
649 // Make sure a bus range was found
651 if (MinBus
== 0xffff || MaxBus
== 0xffff) {
652 return EFI_NOT_FOUND
;
656 // Make sure a non-prefetchable memory region was found
658 if (RootWindowBase
== 0 && RootWindowLimit
== 0) {
659 return EFI_NOT_FOUND
;
663 // Round the Base and Limit values to 1 MB boudaries
665 RootWindowBase
= ((RootWindowBase
- 1) & 0xfff00000) + 0x00100000;
666 RootWindowLimit
= ((RootWindowLimit
+ 1) & 0xfff00000) - 1;
669 // Make sure that the size of the rounded window is greater than zero
671 if (RootWindowLimit
<= RootWindowBase
) {
672 return EFI_NOT_FOUND
;
676 // Allocate buffer to save the Command register from all the PCI devices
678 Context
.CommandRegisterBuffer
= NULL
;
679 Status
= gBS
->AllocatePool(
681 sizeof(UINT16
) * (MaxBus
- MinBus
+ 1) * (PCI_MAX_DEVICE
+1) * (PCI_MAX_FUNC
+1),
682 (VOID
**)&Context
.CommandRegisterBuffer
685 if (EFI_ERROR (Status
)) {
689 Context
.PpbMemoryWindow
= (((UINT32
)RootWindowBase
) >> 16) | ((UINT32
)RootWindowLimit
& 0xffff0000);
692 // Save the Command register from all the PCI devices, and disable the I/O, Mem, and BusMaster bits
699 SaveCommandRegister
, &Context
703 // Recursively scan all the busses for PCI Option ROMs
710 CheckForRom
, &Context
714 // Restore the Command register in all the PCI devices
721 RestoreCommandRegister
, &Context
725 // Free the buffer used to save all the Command register values
727 gBS
->FreePool(Context
.CommandRegisterBuffer
);