3 Copyright (c) 2005 - 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 EFI PC AT PCI Root Bridge Io Protocol
23 #include "PcatPciRootBridge.h"
25 static BOOLEAN mPciOptionRomTableInstalled
= FALSE
;
26 static EFI_PCI_OPTION_ROM_TABLE mPciOptionRomTable
= {0, NULL
};
29 PcatRootBridgeIoIoRead (
30 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
31 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
32 IN UINT64 UserAddress
,
34 IN OUT VOID
*UserBuffer
37 return gCpuIo
->Io
.Read (
39 (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
47 PcatRootBridgeIoIoWrite (
48 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
49 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
50 IN UINT64 UserAddress
,
52 IN OUT VOID
*UserBuffer
55 return gCpuIo
->Io
.Write (
57 (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
66 PcatRootBridgeIoGetIoPortMapping (
67 OUT EFI_PHYSICAL_ADDRESS
*IoPortMapping
,
68 OUT EFI_PHYSICAL_ADDRESS
*MemoryPortMapping
72 Get the IO Port Mapping. For IA-32 it is always 0.
77 *MemoryPortMapping
= 0;
83 PcatRootBridgeIoPciRW (
84 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
86 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
87 IN UINT64 UserAddress
,
89 IN OUT VOID
*UserBuffer
92 PCI_CONFIG_ACCESS_CF8 Pci
;
93 PCI_CONFIG_ACCESS_CF8 PciAligned
;
98 PCAT_PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
;
99 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress
;
100 UINT64 PciExpressRegAddr
;
101 BOOLEAN UsePciExpressAccess
;
103 if (Width
< 0 || Width
>= EfiPciWidthMaximum
) {
104 return EFI_INVALID_PARAMETER
;
107 if ((Width
& 0x03) >= EfiPciWidthUint64
) {
108 return EFI_INVALID_PARAMETER
;
111 PrivateData
= DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This
);
113 InStride
= 1 << (Width
& 0x03);
114 OutStride
= InStride
;
115 if (Width
>= EfiCpuIoWidthFifoUint8
&& Width
<= EfiCpuIoWidthFifoUint64
) {
119 if (Width
>= EfiCpuIoWidthFillUint8
&& Width
<= EfiCpuIoWidthFillUint64
) {
123 UsePciExpressAccess
= FALSE
;
125 CopyMem (&PciAddress
, &UserAddress
, sizeof(UINT64
));
127 if (PciAddress
.ExtendedRegister
> 0xFF) {
129 // Check PciExpressBaseAddress
131 if ((PrivateData
->PciExpressBaseAddress
== 0) ||
132 (PrivateData
->PciExpressBaseAddress
>= EFI_MAX_ADDRESS
)) {
133 return EFI_UNSUPPORTED
;
135 UsePciExpressAccess
= TRUE
;
138 if (PciAddress
.ExtendedRegister
!= 0) {
139 Pci
.Bits
.Reg
= PciAddress
.ExtendedRegister
& 0xFF;
141 Pci
.Bits
.Reg
= PciAddress
.Register
;
144 // Note: We can also use PciExpress access here, if wanted.
148 if (!UsePciExpressAccess
) {
149 Pci
.Bits
.Func
= PciAddress
.Function
;
150 Pci
.Bits
.Dev
= PciAddress
.Device
;
151 Pci
.Bits
.Bus
= PciAddress
.Bus
;
152 Pci
.Bits
.Reserved
= 0;
156 // PCI Config access are all 32-bit alligned, but by accessing the
157 // CONFIG_DATA_REGISTER (0xcfc) with different widths more cycle types
158 // are possible on PCI.
160 // To read a byte of PCI config space you load 0xcf8 and
161 // read 0xcfc, 0xcfd, 0xcfe, 0xcff
163 PciDataStride
= Pci
.Bits
.Reg
& 0x03;
167 PciAligned
.Bits
.Reg
&= 0xfc;
168 PciData
= (UINTN
)PrivateData
->PciData
+ PciDataStride
;
169 EfiAcquireLock(&PrivateData
->PciLock
);
170 This
->Io
.Write (This
, EfiPciWidthUint32
, PrivateData
->PciAddress
, 1, &PciAligned
);
172 This
->Io
.Write (This
, Width
, PciData
, 1, UserBuffer
);
174 This
->Io
.Read (This
, Width
, PciData
, 1, UserBuffer
);
176 EfiReleaseLock(&PrivateData
->PciLock
);
177 UserBuffer
= ((UINT8
*)UserBuffer
) + OutStride
;
178 PciDataStride
= (PciDataStride
+ InStride
) % 4;
179 Pci
.Bits
.Reg
+= InStride
;
184 // Access PCI-Express space by using memory mapped method.
186 PciExpressRegAddr
= (PrivateData
->PciExpressBaseAddress
) |
187 (PciAddress
.Bus
<< 20) |
188 (PciAddress
.Device
<< 15) |
189 (PciAddress
.Function
<< 12);
190 if (PciAddress
.ExtendedRegister
!= 0) {
191 PciExpressRegAddr
+= PciAddress
.ExtendedRegister
;
193 PciExpressRegAddr
+= PciAddress
.Register
;
197 This
->Mem
.Write (This
, Width
, (UINTN
) PciExpressRegAddr
, 1, UserBuffer
);
199 This
->Mem
.Read (This
, Width
, (UINTN
) PciExpressRegAddr
, 1, UserBuffer
);
202 UserBuffer
= ((UINT8
*) UserBuffer
) + OutStride
;
203 PciExpressRegAddr
+= InStride
;
214 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
221 EFI_PCI_BUS_SCAN_CALLBACK Callback
,
230 PCI_TYPE00 PciHeader
;
233 // Loop through all busses
235 for (Bus
= MinBus
; Bus
<= MaxBus
; Bus
++) {
237 // Loop 32 devices per bus
239 for (Device
= MinDevice
; Device
<= MaxDevice
; Device
++) {
241 // Loop through 8 functions per device
243 for (Func
= MinFunc
; Func
<= MaxFunc
; Func
++) {
246 // Compute the EFI Address required to access the PCI Configuration Header of this PCI Device
248 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
251 // Read the VendorID from this PCI Device's Confioguration Header
253 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, Address
, 1, &PciHeader
.Hdr
.VendorId
);
256 // If VendorId = 0xffff, there does not exist a device at this
257 // location. For each device, if there is any function on it,
258 // there must be 1 function at Function 0. So if Func = 0, there
259 // will be no more functions in the same device, so we can break
260 // loop to deal with the next device.
262 if (PciHeader
.Hdr
.VendorId
== 0xffff && Func
== 0) {
266 if (PciHeader
.Hdr
.VendorId
!= 0xffff) {
269 // Read the HeaderType to determine if this is a multi-function device
271 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint8
, Address
+ 0x0e, 1, &PciHeader
.Hdr
.HeaderType
);
274 // Call the callback function for the device that was found
279 MinDevice
, MaxDevice
,
288 // If this is not a multi-function device, we can leave the loop
289 // to deal with the next device.
291 if ((PciHeader
.Hdr
.HeaderType
& HEADER_TYPE_MULTI_FUNCTION
) == 0x00 && Func
== 0) {
303 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
317 PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT
*Context
;
319 PCI_TYPE00 PciHeader
;
320 PCI_TYPE01
*PciBridgeHeader
;
324 EFI_PHYSICAL_ADDRESS RomBuffer
;
326 EFI_PCI_EXPANSION_ROM_HEADER EfiRomHeader
;
327 PCI_DATA_STRUCTURE Pcir
;
328 EFI_PCI_OPTION_ROM_DESCRIPTOR
*TempPciOptionRomDescriptors
;
331 Context
= (PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT
*)VoidContext
;
333 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
336 // Save the contents of the PCI Configuration Header
338 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, Address
, sizeof(PciHeader
)/sizeof(UINT32
), &PciHeader
);
340 if (IS_PCI_BRIDGE(&PciHeader
)) {
342 PciBridgeHeader
= (PCI_TYPE01
*)(&PciHeader
);
345 // See if the PCI-PCI Bridge has its secondary interface enabled.
347 if (PciBridgeHeader
->Bridge
.SubordinateBus
>= PciBridgeHeader
->Bridge
.SecondaryBus
) {
350 // Disable the Prefetchable Memory Window
352 Register
= 0x00000000;
353 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
+ 0x26, 1, &Register
);
354 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, Address
+ 0x2c, 1, &Register
);
355 Register
= 0xffffffff;
356 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
+ 0x24, 1, &Register
);
357 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
+ 0x28, 1, &Register
);
360 // Program Memory Window to the PCI Root Bridge Memory Window
362 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
+ 0x20, 4, &Context
->PpbMemoryWindow
);
365 // Enable the Memory decode for the PCI-PCI Bridge
367 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, Address
+ 4, 1, &Register
);
369 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
+ 4, 1, &Register
);
372 // Recurse on the Secondary Bus Number
376 PciBridgeHeader
->Bridge
.SecondaryBus
, PciBridgeHeader
->Bridge
.SecondaryBus
,
385 // Check if an Option ROM Register is present and save the Option ROM Window Register
388 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, Address
+ 0x30, 1, &RomBar
);
389 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, Address
+ 0x30, 1, &RomBar
);
391 RomBarSize
= (~(RomBar
& 0xfffff800)) + 1;
394 // Make sure the size of the ROM is between 0 and 16 MB
396 if (RomBarSize
> 0 && RomBarSize
<= 0x01000000) {
399 // Program Option ROM Window Register to the PCI Root Bridge Window and Enable the Option ROM Window
401 RomBar
= (Context
->PpbMemoryWindow
& 0xffff) << 16;
402 RomBar
= ((RomBar
- 1) & (~(RomBarSize
- 1))) + RomBarSize
;
403 if (RomBar
< (Context
->PpbMemoryWindow
& 0xffff0000)) {
404 MaxRomSize
= (Context
->PpbMemoryWindow
& 0xffff0000) - RomBar
;
406 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, Address
+ 0x30, 1, &RomBar
);
407 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, Address
+ 0x30, 1, &RomBar
);
411 // Enable the Memory decode for the PCI Device
413 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, Address
+ 4, 1, &Register
);
415 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
+ 4, 1, &Register
);
418 // Follow the chain of images to determine the size of the Option ROM present
419 // Keep going until the last image is found by looking at the Indicator field
420 // or the size of an image is 0, or the size of all the images is bigger than the
421 // size of the window programmed into the PPB.
428 ZeroMem (&EfiRomHeader
, sizeof(EfiRomHeader
));
433 sizeof(EfiRomHeader
),
437 Pcir
.ImageLength
= 0;
439 if (EfiRomHeader
.Signature
== 0xaa55) {
441 ZeroMem (&Pcir
, sizeof(Pcir
));
445 RomBar
+ RomBarSize
+ EfiRomHeader
.PcirOffset
,
450 if ((Pcir
.Indicator
& 0x80) == 0x00) {
454 RomBarSize
+= Pcir
.ImageLength
* 512;
456 } while (!LastImage
&& RomBarSize
< MaxRomSize
&& Pcir
.ImageLength
!=0);
458 if (RomBarSize
> 0) {
461 // Allocate a memory buffer for the Option ROM contents.
463 Status
= gBS
->AllocatePages(
466 EFI_SIZE_TO_PAGES(RomBarSize
),
470 if (!EFI_ERROR (Status
)) {
473 // Copy the contents of the Option ROM to the memory buffer
475 IoDev
->Mem
.Read (IoDev
, EfiPciWidthUint32
, RomBar
, RomBarSize
/ sizeof(UINT32
), (VOID
*)(UINTN
)RomBuffer
);
477 Status
= gBS
->AllocatePool(
479 ((UINT32
)mPciOptionRomTable
.PciOptionRomCount
+ 1) * sizeof(EFI_PCI_OPTION_ROM_DESCRIPTOR
),
480 &TempPciOptionRomDescriptors
482 if (mPciOptionRomTable
.PciOptionRomCount
> 0) {
484 TempPciOptionRomDescriptors
,
485 mPciOptionRomTable
.PciOptionRomDescriptors
,
486 (UINT32
)mPciOptionRomTable
.PciOptionRomCount
* sizeof(EFI_PCI_OPTION_ROM_DESCRIPTOR
)
489 gBS
->FreePool(mPciOptionRomTable
.PciOptionRomDescriptors
);
492 mPciOptionRomTable
.PciOptionRomDescriptors
= TempPciOptionRomDescriptors
;
494 TempPciOptionRomDescriptors
= &(mPciOptionRomTable
.PciOptionRomDescriptors
[(UINT32
)mPciOptionRomTable
.PciOptionRomCount
]);
496 TempPciOptionRomDescriptors
->RomAddress
= RomBuffer
;
497 TempPciOptionRomDescriptors
->MemoryType
= EfiBootServicesData
;
498 TempPciOptionRomDescriptors
->RomLength
= RomBarSize
;
499 TempPciOptionRomDescriptors
->Seg
= (UINT32
)IoDev
->SegmentNumber
;
500 TempPciOptionRomDescriptors
->Bus
= (UINT8
)Bus
;
501 TempPciOptionRomDescriptors
->Dev
= (UINT8
)Device
;
502 TempPciOptionRomDescriptors
->Func
= (UINT8
)Func
;
503 TempPciOptionRomDescriptors
->ExecutedLegacyBiosImage
= TRUE
;
504 TempPciOptionRomDescriptors
->DontLoadEfiRom
= FALSE
;
506 mPciOptionRomTable
.PciOptionRomCount
++;
511 // Disable the Memory decode for the PCI-PCI Bridge
513 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, Address
+ 4, 1, &Register
);
515 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
+ 4, 1, &Register
);
521 // Restore the PCI Configuration Header
523 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, Address
, sizeof(PciHeader
)/sizeof(UINT32
), &PciHeader
);
528 SaveCommandRegister (
529 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
543 PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT
*Context
;
548 Context
= (PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT
*)VoidContext
;
550 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 4);
552 Index
= (Bus
- MinBus
) * (PCI_MAX_DEVICE
+1) * (PCI_MAX_FUNC
+1) + Device
* (PCI_MAX_FUNC
+1) + Func
;
554 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, Address
, 1, &Context
->CommandRegisterBuffer
[Index
]);
557 // Clear the memory enable bit
559 Command
= Context
->CommandRegisterBuffer
[Index
] & (~0x02);
561 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
, 1, &Command
);
566 RestoreCommandRegister (
567 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
581 PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT
*Context
;
585 Context
= (PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT
*)VoidContext
;
587 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 4);
589 Index
= (Bus
- MinBus
) * (PCI_MAX_DEVICE
+1) * (PCI_MAX_FUNC
+1) + Device
* (PCI_MAX_FUNC
+1) + Func
;
591 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, Address
, 1, &Context
->CommandRegisterBuffer
[Index
]);
595 ScanPciRootBridgeForRoms(
596 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
601 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
604 UINT64 RootWindowBase
;
605 UINT64 RootWindowLimit
;
606 PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT Context
;
608 if (mPciOptionRomTableInstalled
== FALSE
) {
609 gBS
->InstallConfigurationTable(&gEfiPciOptionRomTableGuid
, &mPciOptionRomTable
);
610 mPciOptionRomTableInstalled
= TRUE
;
613 Status
= IoDev
->Configuration(IoDev
, &Descriptors
);
614 if (EFI_ERROR (Status
) || Descriptors
== NULL
) {
615 return EFI_NOT_FOUND
;
622 while (Descriptors
->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
626 if (Descriptors
->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
627 MinBus
= (UINT16
)Descriptors
->AddrRangeMin
;
628 MaxBus
= (UINT16
)Descriptors
->AddrRangeMax
;
631 // Find memory descriptors that are not prefetchable
633 if (Descriptors
->ResType
== ACPI_ADDRESS_SPACE_TYPE_MEM
&& Descriptors
->SpecificFlag
== 0) {
635 // Find Memory Descriptors that are less than 4GB, so the PPB Memory Window can be used for downstream devices
637 if (Descriptors
->AddrRangeMax
< 0x100000000) {
639 // Find the largest Non-Prefetchable Memory Descriptor that is less than 4GB
641 if ((Descriptors
->AddrRangeMax
- Descriptors
->AddrRangeMin
) > (RootWindowLimit
- RootWindowBase
)) {
642 RootWindowBase
= Descriptors
->AddrRangeMin
;
643 RootWindowLimit
= Descriptors
->AddrRangeMax
;
651 // Make sure a bus range was found
653 if (MinBus
== 0xffff || MaxBus
== 0xffff) {
654 return EFI_NOT_FOUND
;
658 // Make sure a non-prefetchable memory region was found
660 if (RootWindowBase
== 0 && RootWindowLimit
== 0) {
661 return EFI_NOT_FOUND
;
665 // Round the Base and Limit values to 1 MB boudaries
667 RootWindowBase
= ((RootWindowBase
- 1) & 0xfff00000) + 0x00100000;
668 RootWindowLimit
= ((RootWindowLimit
+ 1) & 0xfff00000) - 1;
671 // Make sure that the size of the rounded window is greater than zero
673 if (RootWindowLimit
<= RootWindowBase
) {
674 return EFI_NOT_FOUND
;
678 // Allocate buffer to save the Command register from all the PCI devices
680 Context
.CommandRegisterBuffer
= NULL
;
681 Status
= gBS
->AllocatePool(
683 sizeof(UINT16
) * (MaxBus
- MinBus
+ 1) * (PCI_MAX_DEVICE
+1) * (PCI_MAX_FUNC
+1),
684 &Context
.CommandRegisterBuffer
687 if (EFI_ERROR (Status
)) {
691 Context
.PpbMemoryWindow
= (((UINT32
)RootWindowBase
) >> 16) | ((UINT32
)RootWindowLimit
& 0xffff0000);
694 // Save the Command register from all the PCI devices, and disable the I/O, Mem, and BusMaster bits
701 SaveCommandRegister
, &Context
705 // Recursively scan all the busses for PCI Option ROMs
712 CheckForRom
, &Context
716 // Restore the Command register in all the PCI devices
723 RestoreCommandRegister
, &Context
727 // Free the buffer used to save all the Command register values
729 gBS
->FreePool(Context
.CommandRegisterBuffer
);