DynamicTablesPkg/Include/ArmNameSpaceObjects.h

   1 /** @file
   2
   3   Copyright (c) 2017 - 2022, Arm Limited. All rights reserved.<BR>
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7   @par Glossary:
   8     - Cm or CM   - Configuration Manager
   9     - Obj or OBJ - Object
  10     - Std or STD - Standard
  11 **/
  12
  13 #ifndef ARM_NAMESPACE_OBJECTS_H_
  14 #define ARM_NAMESPACE_OBJECTS_H_
  15
  16 #include <StandardNameSpaceObjects.h>
  17
  18 #pragma pack(1)
  19
  20 /** The EARM_OBJECT_ID enum describes the Object IDs
  21     in the ARM Namespace
  22 */
  23 typedef enum ArmObjectID {
  24   EArmObjReserved,                     ///<  0 - Reserved
  25   EArmObjBootArchInfo,                 ///<  1 - Boot Architecture Info
  26   EArmObjCpuInfo,                      ///<  2 - CPU Info
  27   EArmObjPowerManagementProfileInfo,   ///<  3 - Power Management Profile Info
  28   EArmObjGicCInfo,                     ///<  4 - GIC CPU Interface Info
  29   EArmObjGicDInfo,                     ///<  5 - GIC Distributor Info
  30   EArmObjGicMsiFrameInfo,              ///<  6 - GIC MSI Frame Info
  31   EArmObjGicRedistributorInfo,         ///<  7 - GIC Redistributor Info
  32   EArmObjGicItsInfo,                   ///<  8 - GIC ITS Info
  33   EArmObjSerialConsolePortInfo,        ///<  9 - Serial Console Port Info
  34   EArmObjSerialDebugPortInfo,          ///< 10 - Serial Debug Port Info
  35   EArmObjGenericTimerInfo,             ///< 11 - Generic Timer Info
  36   EArmObjPlatformGTBlockInfo,          ///< 12 - Platform GT Block Info
  37   EArmObjGTBlockTimerFrameInfo,        ///< 13 - Generic Timer Block Frame Info
  38   EArmObjPlatformGenericWatchdogInfo,  ///< 14 - Platform Generic Watchdog
  39   EArmObjPciConfigSpaceInfo,           ///< 15 - PCI Configuration Space Info
  40   EArmObjHypervisorVendorIdentity,     ///< 16 - Hypervisor Vendor Id
  41   EArmObjFixedFeatureFlags,            ///< 17 - Fixed feature flags for FADT
  42   EArmObjItsGroup,                     ///< 18 - ITS Group
  43   EArmObjNamedComponent,               ///< 19 - Named Component
  44   EArmObjRootComplex,                  ///< 20 - Root Complex
  45   EArmObjSmmuV1SmmuV2,                 ///< 21 - SMMUv1 or SMMUv2
  46   EArmObjSmmuV3,                       ///< 22 - SMMUv3
  47   EArmObjPmcg,                         ///< 23 - PMCG
  48   EArmObjGicItsIdentifierArray,        ///< 24 - GIC ITS Identifier Array
  49   EArmObjIdMappingArray,               ///< 25 - ID Mapping Array
  50   EArmObjSmmuInterruptArray,           ///< 26 - SMMU Interrupt Array
  51   EArmObjProcHierarchyInfo,            ///< 27 - Processor Hierarchy Info
  52   EArmObjCacheInfo,                    ///< 28 - Cache Info
  53   EArmObjReserved29,                   ///< 29 - Reserved
  54   EArmObjCmRef,                        ///< 30 - CM Object Reference
  55   EArmObjMemoryAffinityInfo,           ///< 31 - Memory Affinity Info
  56   EArmObjDeviceHandleAcpi,             ///< 32 - Device Handle Acpi
  57   EArmObjDeviceHandlePci,              ///< 33 - Device Handle Pci
  58   EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity
  59   EArmObjSerialPortInfo,               ///< 35 - Generic Serial Port Info
  60   EArmObjCmn600Info,                   ///< 36 - CMN-600 Info
  61   EArmObjLpiInfo,                      ///< 37 - Lpi Info
  62   EArmObjPciAddressMapInfo,            ///< 38 - Pci Address Map Info
  63   EArmObjPciInterruptMapInfo,          ///< 39 - Pci Interrupt Map Info
  64   EArmObjRmr,                          ///< 40 - Reserved Memory Range Node
  65   EArmObjMemoryRangeDescriptor,        ///< 41 - Memory Range Descriptor
  66   EArmObjMax
  67 } EARM_OBJECT_ID;
  68
  69 /** A structure that describes the
  70     ARM Boot Architecture flags.
  71
  72     ID: EArmObjBootArchInfo
  73 */
  74 typedef struct CmArmBootArchInfo {
  75   /** This is the ARM_BOOT_ARCH flags field of the FADT Table
  76       described in the ACPI Table Specification.
  77   */
  78   UINT16    BootArchFlags;
  79 } CM_ARM_BOOT_ARCH_INFO;
  80
  81 /** A structure that describes the
  82     Power Management Profile Information for the Platform.
  83
  84     ID: EArmObjPowerManagementProfileInfo
  85 */
  86 typedef struct CmArmPowerManagementProfileInfo {
  87   /** This is the Preferred_PM_Profile field of the FADT Table
  88       described in the ACPI Specification
  89   */
  90   UINT8    PowerManagementProfile;
  91 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;
  92
  93 /** A structure that describes the
  94     GIC CPU Interface for the Platform.
  95
  96     ID: EArmObjGicCInfo
  97 */
  98 typedef struct CmArmGicCInfo {
  99   /// The GIC CPU Interface number.
 100   UINT32    CPUInterfaceNumber;
 101
 102   /** The ACPI Processor UID. This must match the
 103       _UID of the CPU Device object information described
 104       in the DSDT/SSDT for the CPU.
 105   */
 106   UINT32    AcpiProcessorUid;
 107
 108   /** The flags field as described by the GICC structure
 109       in the ACPI Specification.
 110   */
 111   UINT32    Flags;
 112
 113   /** The parking protocol version field as described by
 114     the GICC structure in the ACPI Specification.
 115   */
 116   UINT32    ParkingProtocolVersion;
 117
 118   /** The Performance Interrupt field as described by
 119       the GICC structure in the ACPI Specification.
 120   */
 121   UINT32    PerformanceInterruptGsiv;
 122
 123   /** The CPU Parked address field as described by
 124       the GICC structure in the ACPI Specification.
 125   */
 126   UINT64    ParkedAddress;
 127
 128   /** The base address for the GIC CPU Interface
 129       as described by the GICC structure in the
 130       ACPI Specification.
 131   */
 132   UINT64    PhysicalBaseAddress;
 133
 134   /** The base address for GICV interface
 135       as described by the GICC structure in the
 136       ACPI Specification.
 137   */
 138   UINT64    GICV;
 139
 140   /** The base address for GICH interface
 141       as described by the GICC structure in the
 142       ACPI Specification.
 143   */
 144   UINT64    GICH;
 145
 146   /** The GICV maintenance interrupt
 147       as described by the GICC structure in the
 148       ACPI Specification.
 149   */
 150   UINT32    VGICMaintenanceInterrupt;
 151
 152   /** The base address for GICR interface
 153       as described by the GICC structure in the
 154       ACPI Specification.
 155   */
 156   UINT64    GICRBaseAddress;
 157
 158   /** The MPIDR for the CPU
 159       as described by the GICC structure in the
 160       ACPI Specification.
 161   */
 162   UINT64    MPIDR;
 163
 164   /** The Processor Power Efficiency class
 165       as described by the GICC structure in the
 166       ACPI Specification.
 167   */
 168   UINT8     ProcessorPowerEfficiencyClass;
 169
 170   /** Statistical Profiling Extension buffer overflow GSIV. Zero if
 171       unsupported by this processor. This field was introduced in
 172       ACPI 6.3 (MADT revision 5) and is therefore ignored when
 173       generating MADT revision 4 or lower.
 174   */
 175   UINT16    SpeOverflowInterrupt;
 176
 177   /** The proximity domain to which the logical processor belongs.
 178       This field is used to populate the GICC affinity structure
 179       in the SRAT table.
 180   */
 181   UINT32    ProximityDomain;
 182
 183   /** The clock domain to which the logical processor belongs.
 184       This field is used to populate the GICC affinity structure
 185       in the SRAT table.
 186   */
 187   UINT32    ClockDomain;
 188
 189   /** The GICC Affinity flags field as described by the GICC Affinity structure
 190       in the SRAT table.
 191   */
 192   UINT32    AffinityFlags;
 193 } CM_ARM_GICC_INFO;
 194
 195 /** A structure that describes the
 196     GIC Distributor information for the Platform.
 197
 198     ID: EArmObjGicDInfo
 199 */
 200 typedef struct CmArmGicDInfo {
 201   /// The Physical Base address for the GIC Distributor.
 202   UINT64    PhysicalBaseAddress;
 203
 204   /** The global system interrupt
 205       number where this GIC Distributor's
 206       interrupt inputs start.
 207   */
 208   UINT32    SystemVectorBase;
 209
 210   /** The GIC version as described
 211       by the GICD structure in the
 212       ACPI Specification.
 213   */
 214   UINT8     GicVersion;
 215 } CM_ARM_GICD_INFO;
 216
 217 /** A structure that describes the
 218     GIC MSI Frame information for the Platform.
 219
 220     ID: EArmObjGicMsiFrameInfo
 221 */
 222 typedef struct CmArmGicMsiFrameInfo {
 223   /// The GIC MSI Frame ID
 224   UINT32    GicMsiFrameId;
 225
 226   /// The Physical base address for the MSI Frame
 227   UINT64    PhysicalBaseAddress;
 228
 229   /** The GIC MSI Frame flags
 230       as described by the GIC MSI frame
 231       structure in the ACPI Specification.
 232   */
 233   UINT32    Flags;
 234
 235   /// SPI Count used by this frame
 236   UINT16    SPICount;
 237
 238   /// SPI Base used by this frame
 239   UINT16    SPIBase;
 240 } CM_ARM_GIC_MSI_FRAME_INFO;
 241
 242 /** A structure that describes the
 243     GIC Redistributor information for the Platform.
 244
 245     ID: EArmObjGicRedistributorInfo
 246 */
 247 typedef struct CmArmGicRedistInfo {
 248   /** The physical address of a page range
 249       containing all GIC Redistributors.
 250   */
 251   UINT64    DiscoveryRangeBaseAddress;
 252
 253   /// Length of the GIC Redistributor Discovery page range
 254   UINT32    DiscoveryRangeLength;
 255 } CM_ARM_GIC_REDIST_INFO;
 256
 257 /** A structure that describes the
 258     GIC Interrupt Translation Service information for the Platform.
 259
 260     ID: EArmObjGicItsInfo
 261 */
 262 typedef struct CmArmGicItsInfo {
 263   /// The GIC ITS ID
 264   UINT32    GicItsId;
 265
 266   /// The physical address for the Interrupt Translation Service
 267   UINT64    PhysicalBaseAddress;
 268
 269   /** The proximity domain to which the logical processor belongs.
 270       This field is used to populate the GIC ITS affinity structure
 271       in the SRAT table.
 272   */
 273   UINT32    ProximityDomain;
 274 } CM_ARM_GIC_ITS_INFO;
 275
 276 /** A structure that describes the
 277     Serial Port information for the Platform.
 278
 279     ID: EArmObjSerialConsolePortInfo or
 280         EArmObjSerialDebugPortInfo or
 281         EArmObjSerialPortInfo
 282 */
 283 typedef struct CmArmSerialPortInfo {
 284   /// The physical base address for the serial port
 285   UINT64    BaseAddress;
 286
 287   /// The serial port interrupt
 288   UINT32    Interrupt;
 289
 290   /// The serial port baud rate
 291   UINT64    BaudRate;
 292
 293   /// The serial port clock
 294   UINT32    Clock;
 295
 296   /// Serial Port subtype
 297   UINT16    PortSubtype;
 298
 299   /// The Base address length
 300   UINT64    BaseAddressLength;
 301
 302   /// The access size
 303   UINT8     AccessSize;
 304 } CM_ARM_SERIAL_PORT_INFO;
 305
 306 /** A structure that describes the
 307     Generic Timer information for the Platform.
 308
 309     ID: EArmObjGenericTimerInfo
 310 */
 311 typedef struct CmArmGenericTimerInfo {
 312   /// The physical base address for the counter control frame
 313   UINT64    CounterControlBaseAddress;
 314
 315   /// The physical base address for the counter read frame
 316   UINT64    CounterReadBaseAddress;
 317
 318   /// The secure PL1 timer interrupt
 319   UINT32    SecurePL1TimerGSIV;
 320
 321   /// The secure PL1 timer flags
 322   UINT32    SecurePL1TimerFlags;
 323
 324   /// The non-secure PL1 timer interrupt
 325   UINT32    NonSecurePL1TimerGSIV;
 326
 327   /// The non-secure PL1 timer flags
 328   UINT32    NonSecurePL1TimerFlags;
 329
 330   /// The virtual timer interrupt
 331   UINT32    VirtualTimerGSIV;
 332
 333   /// The virtual timer flags
 334   UINT32    VirtualTimerFlags;
 335
 336   /// The non-secure PL2 timer interrupt
 337   UINT32    NonSecurePL2TimerGSIV;
 338
 339   /// The non-secure PL2 timer flags
 340   UINT32    NonSecurePL2TimerFlags;
 341
 342   /// GSIV for the virtual EL2 timer
 343   UINT32    VirtualPL2TimerGSIV;
 344
 345   /// Flags for the virtual EL2 timer
 346   UINT32    VirtualPL2TimerFlags;
 347 } CM_ARM_GENERIC_TIMER_INFO;
 348
 349 /** A structure that describes the
 350     Platform Generic Block Timer Frame information for the Platform.
 351
 352     ID: EArmObjGTBlockTimerFrameInfo
 353 */
 354 typedef struct CmArmGTBlockTimerFrameInfo {
 355   /// The Generic Timer frame number
 356   UINT8     FrameNumber;
 357
 358   /// The physical base address for the CntBase block
 359   UINT64    PhysicalAddressCntBase;
 360
 361   /// The physical base address for the CntEL0Base block
 362   UINT64    PhysicalAddressCntEL0Base;
 363
 364   /// The physical timer interrupt
 365   UINT32    PhysicalTimerGSIV;
 366
 367   /** The physical timer flags as described by the GT Block
 368       Timer frame Structure in the ACPI Specification.
 369   */
 370   UINT32    PhysicalTimerFlags;
 371
 372   /// The virtual timer interrupt
 373   UINT32    VirtualTimerGSIV;
 374
 375   /** The virtual timer flags as described by the GT Block
 376       Timer frame Structure in the ACPI Specification.
 377   */
 378   UINT32    VirtualTimerFlags;
 379
 380   /** The common timer flags as described by the GT Block
 381       Timer frame Structure in the ACPI Specification.
 382   */
 383   UINT32    CommonFlags;
 384 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;
 385
 386 /** A structure that describes the
 387     Platform Generic Block Timer information for the Platform.
 388
 389     ID: EArmObjPlatformGTBlockInfo
 390 */
 391 typedef struct CmArmGTBlockInfo {
 392   /// The physical base address for the GT Block Timer structure
 393   UINT64             GTBlockPhysicalAddress;
 394
 395   /// The number of timer frames implemented in the GT Block
 396   UINT32             GTBlockTimerFrameCount;
 397
 398   /// Reference token for the GT Block timer frame list
 399   CM_OBJECT_TOKEN    GTBlockTimerFrameToken;
 400 } CM_ARM_GTBLOCK_INFO;
 401
 402 /** A structure that describes the
 403     Arm Generic Watchdog information for the Platform.
 404
 405     ID: EArmObjPlatformGenericWatchdogInfo
 406 */
 407 typedef struct CmArmGenericWatchdogInfo {
 408   /// The physical base address of the Arm Watchdog control frame
 409   UINT64    ControlFrameAddress;
 410
 411   /// The physical base address of the Arm Watchdog refresh frame
 412   UINT64    RefreshFrameAddress;
 413
 414   /// The watchdog interrupt
 415   UINT32    TimerGSIV;
 416
 417   /** The flags for the watchdog as described by the Arm watchdog
 418       structure in the ACPI specification.
 419   */
 420   UINT32    Flags;
 421 } CM_ARM_GENERIC_WATCHDOG_INFO;
 422
 423 /** A structure that describes the
 424     PCI Configuration Space information for the Platform.
 425
 426     ID: EArmObjPciConfigSpaceInfo
 427 */
 428 typedef struct CmArmPciConfigSpaceInfo {
 429   /// The physical base address for the PCI segment
 430   UINT64             BaseAddress;
 431
 432   /// The PCI segment group number
 433   UINT16             PciSegmentGroupNumber;
 434
 435   /// The start bus number
 436   UINT8              StartBusNumber;
 437
 438   /// The end bus number
 439   UINT8              EndBusNumber;
 440
 441   /// Optional field: Reference Token for address mapping.
 442   /// Token identifying a CM_ARM_OBJ_REF structure.
 443   CM_OBJECT_TOKEN    AddressMapToken;
 444
 445   /// Optional field: Reference Token for interrupt mapping.
 446   /// Token identifying a CM_ARM_OBJ_REF structure.
 447   CM_OBJECT_TOKEN    InterruptMapToken;
 448 } CM_ARM_PCI_CONFIG_SPACE_INFO;
 449
 450 /** A structure that describes the
 451     Hypervisor Vendor ID information for the Platform.
 452
 453     ID: EArmObjHypervisorVendorIdentity
 454 */
 455 typedef struct CmArmHypervisorVendorId {
 456   /// The hypervisor Vendor ID
 457   UINT64    HypervisorVendorId;
 458 } CM_ARM_HYPERVISOR_VENDOR_ID;
 459
 460 /** A structure that describes the
 461     Fixed feature flags for the Platform.
 462
 463     ID: EArmObjFixedFeatureFlags
 464 */
 465 typedef struct CmArmFixedFeatureFlags {
 466   /// The Fixed feature flags
 467   UINT32    Flags;
 468 } CM_ARM_FIXED_FEATURE_FLAGS;
 469
 470 /** A structure that describes the
 471     ITS Group node for the Platform.
 472
 473     ID: EArmObjItsGroup
 474 */
 475 typedef struct CmArmItsGroupNode {
 476   /// An unique token used to identify this object
 477   CM_OBJECT_TOKEN    Token;
 478   /// The number of ITS identifiers in the ITS node
 479   UINT32             ItsIdCount;
 480   /// Reference token for the ITS identifier array
 481   CM_OBJECT_TOKEN    ItsIdToken;
 482
 483   /// Unique identifier for this node.
 484   UINT32             Identifier;
 485 } CM_ARM_ITS_GROUP_NODE;
 486
 487 /** A structure that describes the
 488     Named component node for the Platform.
 489
 490     ID: EArmObjNamedComponent
 491 */
 492 typedef struct CmArmNamedComponentNode {
 493   /// An unique token used to identify this object
 494   CM_OBJECT_TOKEN    Token;
 495   /// Number of ID mappings
 496   UINT32             IdMappingCount;
 497   /// Reference token for the ID mapping array
 498   CM_OBJECT_TOKEN    IdMappingToken;
 499
 500   /// Flags for the named component
 501   UINT32             Flags;
 502
 503   /// Memory access properties : Cache coherent attributes
 504   UINT32             CacheCoherent;
 505   /// Memory access properties : Allocation hints
 506   UINT8              AllocationHints;
 507   /// Memory access properties : Memory access flags
 508   UINT8              MemoryAccessFlags;
 509
 510   /// Memory access properties : Address size limit
 511   UINT8              AddressSizeLimit;
 512
 513   /** ASCII Null terminated string with the full path to
 514       the entry in the namespace for this object.
 515   */
 516   CHAR8              *ObjectName;
 517
 518   /// Unique identifier for this node.
 519   UINT32             Identifier;
 520 } CM_ARM_NAMED_COMPONENT_NODE;
 521
 522 /** A structure that describes the
 523     Root complex node for the Platform.
 524
 525     ID: EArmObjRootComplex
 526 */
 527 typedef struct CmArmRootComplexNode {
 528   /// An unique token used to identify this object
 529   CM_OBJECT_TOKEN    Token;
 530   /// Number of ID mappings
 531   UINT32             IdMappingCount;
 532   /// Reference token for the ID mapping array
 533   CM_OBJECT_TOKEN    IdMappingToken;
 534
 535   /// Memory access properties : Cache coherent attributes
 536   UINT32             CacheCoherent;
 537   /// Memory access properties : Allocation hints
 538   UINT8              AllocationHints;
 539   /// Memory access properties : Memory access flags
 540   UINT8              MemoryAccessFlags;
 541
 542   /// ATS attributes
 543   UINT32             AtsAttribute;
 544   /// PCI segment number
 545   UINT32             PciSegmentNumber;
 546   /// Memory address size limit
 547   UINT8              MemoryAddressSize;
 548   /// PASID capabilities
 549   UINT16             PasidCapabilities;
 550   /// Flags
 551   UINT32             Flags;
 552
 553   /// Unique identifier for this node.
 554   UINT32             Identifier;
 555 } CM_ARM_ROOT_COMPLEX_NODE;
 556
 557 /** A structure that describes the
 558     SMMUv1 or SMMUv2 node for the Platform.
 559
 560     ID: EArmObjSmmuV1SmmuV2
 561 */
 562 typedef struct CmArmSmmuV1SmmuV2Node {
 563   /// An unique token used to identify this object
 564   CM_OBJECT_TOKEN    Token;
 565   /// Number of ID mappings
 566   UINT32             IdMappingCount;
 567   /// Reference token for the ID mapping array
 568   CM_OBJECT_TOKEN    IdMappingToken;
 569
 570   /// SMMU Base Address
 571   UINT64             BaseAddress;
 572   /// Length of the memory range covered by the SMMU
 573   UINT64             Span;
 574   /// SMMU Model
 575   UINT32             Model;
 576   /// SMMU flags
 577   UINT32             Flags;
 578
 579   /// Number of context interrupts
 580   UINT32             ContextInterruptCount;
 581   /// Reference token for the context interrupt array
 582   CM_OBJECT_TOKEN    ContextInterruptToken;
 583
 584   /// Number of PMU interrupts
 585   UINT32             PmuInterruptCount;
 586   /// Reference token for the PMU interrupt array
 587   CM_OBJECT_TOKEN    PmuInterruptToken;
 588
 589   /// GSIV of the SMMU_NSgIrpt interrupt
 590   UINT32             SMMU_NSgIrpt;
 591   /// SMMU_NSgIrpt interrupt flags
 592   UINT32             SMMU_NSgIrptFlags;
 593   /// GSIV of the SMMU_NSgCfgIrpt interrupt
 594   UINT32             SMMU_NSgCfgIrpt;
 595   /// SMMU_NSgCfgIrpt interrupt flags
 596   UINT32             SMMU_NSgCfgIrptFlags;
 597
 598   /// Unique identifier for this node.
 599   UINT32             Identifier;
 600 } CM_ARM_SMMUV1_SMMUV2_NODE;
 601
 602 /** A structure that describes the
 603     SMMUv3 node for the Platform.
 604
 605     ID: EArmObjSmmuV3
 606 */
 607 typedef struct CmArmSmmuV3Node {
 608   /// An unique token used to identify this object
 609   CM_OBJECT_TOKEN    Token;
 610   /// Number of ID mappings
 611   UINT32             IdMappingCount;
 612   /// Reference token for the ID mapping array
 613   CM_OBJECT_TOKEN    IdMappingToken;
 614
 615   /// SMMU Base Address
 616   UINT64             BaseAddress;
 617   /// SMMU flags
 618   UINT32             Flags;
 619   /// VATOS address
 620   UINT64             VatosAddress;
 621   /// Model
 622   UINT32             Model;
 623   /// GSIV of the Event interrupt if SPI based
 624   UINT32             EventInterrupt;
 625   /// PRI Interrupt if SPI based
 626   UINT32             PriInterrupt;
 627   /// GERR interrupt if GSIV based
 628   UINT32             GerrInterrupt;
 629   /// Sync interrupt if GSIV based
 630   UINT32             SyncInterrupt;
 631
 632   /// Proximity domain flag
 633   UINT32             ProximityDomain;
 634   /// Index into the array of ID mapping
 635   UINT32             DeviceIdMappingIndex;
 636
 637   /// Unique identifier for this node.
 638   UINT32             Identifier;
 639 } CM_ARM_SMMUV3_NODE;
 640
 641 /** A structure that describes the
 642     PMCG node for the Platform.
 643
 644     ID: EArmObjPmcg
 645 */
 646 typedef struct CmArmPmcgNode {
 647   /// An unique token used to identify this object
 648   CM_OBJECT_TOKEN    Token;
 649   /// Number of ID mappings
 650   UINT32             IdMappingCount;
 651   /// Reference token for the ID mapping array
 652   CM_OBJECT_TOKEN    IdMappingToken;
 653
 654   /// Base Address for performance monitor counter group
 655   UINT64             BaseAddress;
 656   /// GSIV for the Overflow interrupt
 657   UINT32             OverflowInterrupt;
 658   /// Page 1 Base address
 659   UINT64             Page1BaseAddress;
 660
 661   /// Reference token for the IORT node associated with this node
 662   CM_OBJECT_TOKEN    ReferenceToken;
 663
 664   /// Unique identifier for this node.
 665   UINT32             Identifier;
 666 } CM_ARM_PMCG_NODE;
 667
 668 /** A structure that describes the
 669     GIC ITS Identifiers for an ITS Group node.
 670
 671     ID: EArmObjGicItsIdentifierArray
 672 */
 673 typedef struct CmArmGicItsIdentifier {
 674   /// The ITS Identifier
 675   UINT32    ItsId;
 676 } CM_ARM_ITS_IDENTIFIER;
 677
 678 /** A structure that describes the
 679     ID Mappings for the Platform.
 680
 681     ID: EArmObjIdMappingArray
 682 */
 683 typedef struct CmArmIdMapping {
 684   /// Input base
 685   UINT32             InputBase;
 686   /// Number of input IDs
 687   UINT32             NumIds;
 688   /// Output Base
 689   UINT32             OutputBase;
 690   /// Reference token for the output node
 691   CM_OBJECT_TOKEN    OutputReferenceToken;
 692   /// Flags
 693   UINT32             Flags;
 694 } CM_ARM_ID_MAPPING;
 695
 696 /** A structure that describes the Arm
 697     Generic Interrupts.
 698 */
 699 typedef struct CmArmGenericInterrupt {
 700   /// Interrupt number
 701   UINT32    Interrupt;
 702
 703   /// Flags
 704   /// BIT0: 0: Interrupt is Level triggered
 705   ///       1: Interrupt is Edge triggered
 706   /// BIT1: 0: Interrupt is Active high
 707   ///       1: Interrupt is Active low
 708   UINT32    Flags;
 709 } CM_ARM_GENERIC_INTERRUPT;
 710
 711 /** A structure that describes the SMMU interrupts for the Platform.
 712
 713     Interrupt   Interrupt number.
 714     Flags       Interrupt flags as defined for SMMU node.
 715
 716     ID: EArmObjSmmuInterruptArray
 717 */
 718 typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_SMMU_INTERRUPT;
 719
 720 /** A structure that describes the AML Extended Interrupts.
 721
 722     Interrupt   Interrupt number.
 723     Flags       Interrupt flags as defined by the Interrupt
 724                 Vector Flags (Byte 3) of the Extended Interrupt
 725                 resource descriptor.
 726                 See EFI_ACPI_EXTENDED_INTERRUPT_FLAG_xxx in Acpi10.h
 727 */
 728 typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_EXTENDED_INTERRUPT;
 729
 730 /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT
 731
 732     ID: EArmObjProcHierarchyInfo
 733 */
 734 typedef struct CmArmProcHierarchyInfo {
 735   /// A unique token used to identify this object
 736   CM_OBJECT_TOKEN    Token;
 737   /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)
 738   UINT32             Flags;
 739   /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor
 740   /// topology. A value of CM_NULL_TOKEN means this node has no parent.
 741   CM_OBJECT_TOKEN    ParentToken;
 742   /// Token of the associated CM_ARM_GICC_INFO object which has the
 743   /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this
 744   /// node represents a group of associated processors and it does not have an
 745   /// associated GIC CPU interface.
 746   CM_OBJECT_TOKEN    GicCToken;
 747   /// Number of resources private to this Node
 748   UINT32             NoOfPrivateResources;
 749   /// Token of the array which contains references to the resources private to
 750   /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if
 751   /// the NoOfPrivateResources is 0, in which case it is recommended to set
 752   /// this field to CM_NULL_TOKEN.
 753   CM_OBJECT_TOKEN    PrivateResourcesArrayToken;
 754   /// Optional field: Reference Token for the Lpi state of this processor.
 755   /// Token identifying a CM_ARM_OBJ_REF structure, itself referencing
 756   /// CM_ARM_LPI_INFO objects.
 757   CM_OBJECT_TOKEN    LpiToken;
 758 } CM_ARM_PROC_HIERARCHY_INFO;
 759
 760 /** A structure that describes the Cache Type Structure (Type 1) in PPTT
 761
 762     ID: EArmObjCacheInfo
 763 */
 764 typedef struct CmArmCacheInfo {
 765   /// A unique token used to identify this object
 766   CM_OBJECT_TOKEN    Token;
 767   /// Reference token for the next level of cache that is private to the same
 768   /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this
 769   /// entry represents the last cache level appropriate to the processor
 770   /// hierarchy node structures using this entry.
 771   CM_OBJECT_TOKEN    NextLevelOfCacheToken;
 772   /// Size of the cache in bytes
 773   UINT32             Size;
 774   /// Number of sets in the cache
 775   UINT32             NumberOfSets;
 776   /// Integer number of ways. The maximum associativity supported by
 777   /// ACPI Cache type structure is limited to MAX_UINT8. However,
 778   /// the maximum number of ways supported by the architecture is
 779   /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field
 780   /// is 32-bit wide.
 781   UINT32             Associativity;
 782   /// Cache attributes (ACPI 6.4 - January 2021, PPTT, Table 5.140)
 783   UINT8              Attributes;
 784   /// Line size in bytes
 785   UINT16             LineSize;
 786   /// Unique ID for the cache
 787   UINT32             CacheId;
 788 } CM_ARM_CACHE_INFO;
 789
 790 /** A structure that describes a reference to another Configuration Manager
 791     object.
 792
 793     This is useful for creating an array of reference tokens. The framework
 794     can then query the configuration manager for these arrays using the
 795     object ID EArmObjCmRef.
 796
 797     This can be used is to represent one-to-many relationships between objects.
 798
 799     ID: EArmObjCmRef
 800 */
 801 typedef struct CmArmObjRef {
 802   /// Token of the CM object being referenced
 803   CM_OBJECT_TOKEN    ReferenceToken;
 804 } CM_ARM_OBJ_REF;
 805
 806 /** A structure that describes the Memory Affinity Structure (Type 1) in SRAT
 807
 808     ID: EArmObjMemoryAffinityInfo
 809 */
 810 typedef struct CmArmMemoryAffinityInfo {
 811   /// The proximity domain to which the "range of memory" belongs.
 812   UINT32    ProximityDomain;
 813
 814   /// Base Address
 815   UINT64    BaseAddress;
 816
 817   /// Length
 818   UINT64    Length;
 819
 820   /// Flags
 821   UINT32    Flags;
 822 } CM_ARM_MEMORY_AFFINITY_INFO;
 823
 824 /** A structure that describes the ACPI Device Handle (Type 0) in the
 825     Generic Initiator Affinity structure in SRAT
 826
 827     ID: EArmObjDeviceHandleAcpi
 828 */
 829 typedef struct CmArmDeviceHandleAcpi {
 830   /// Hardware ID
 831   UINT64    Hid;
 832
 833   /// Unique Id
 834   UINT32    Uid;
 835 } CM_ARM_DEVICE_HANDLE_ACPI;
 836
 837 /** A structure that describes the PCI Device Handle (Type 1) in the
 838     Generic Initiator Affinity structure in SRAT
 839
 840     ID: EArmObjDeviceHandlePci
 841 */
 842 typedef struct CmArmDeviceHandlePci {
 843   /// PCI Segment Number
 844   UINT16    SegmentNumber;
 845
 846   /// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)
 847   UINT8     BusNumber;
 848
 849   /// PCI Device Number - Max 32 devices (Bits 7:3 of BDF)
 850   UINT8     DeviceNumber;
 851
 852   /// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)
 853   UINT8     FunctionNumber;
 854 } CM_ARM_DEVICE_HANDLE_PCI;
 855
 856 /** A structure that describes the Generic Initiator Affinity structure in SRAT
 857
 858     ID: EArmObjGenericInitiatorAffinityInfo
 859 */
 860 typedef struct CmArmGenericInitiatorAffinityInfo {
 861   /// The proximity domain to which the generic initiator belongs.
 862   UINT32             ProximityDomain;
 863
 864   /// Flags
 865   UINT32             Flags;
 866
 867   /// Device Handle Type
 868   UINT8              DeviceHandleType;
 869
 870   /// Reference Token for the Device Handle
 871   CM_OBJECT_TOKEN    DeviceHandleToken;
 872 } CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO;
 873
 874 /** A structure that describes the CMN-600 hardware.
 875
 876     ID: EArmObjCmn600Info
 877 */
 878 typedef struct CmArmCmn600Info {
 879   /// The PERIPHBASE address.
 880   /// Corresponds to the Configuration Node Region (CFGR) base address.
 881   UINT64    PeriphBaseAddress;
 882
 883   /// The PERIPHBASE address length.
 884   /// Corresponds to the CFGR base address length.
 885   UINT64    PeriphBaseAddressLength;
 886
 887   /// The ROOTNODEBASE address.
 888   /// Corresponds to the Root node (ROOT) base address.
 889   UINT64    RootNodeBaseAddress;
 890
 891   /// The Debug and Trace Logic Controller (DTC) count.
 892   /// CMN-600 can have maximum 4 DTCs.
 893   UINT8     DtcCount;
 894
 895   /// DTC Interrupt list.
 896   /// The first interrupt resource descriptor pertains to
 897   /// DTC[0], the second to DTC[1] and so on.
 898   /// DtcCount determines the number of DTC Interrupts that
 899   /// are populated. If DTC count is 2 then DtcInterrupt[2]
 900   /// and DtcInterrupt[3] are ignored.
 901   /// Note: The size of CM_ARM_CMN_600_INFO structure remains
 902   /// constant and does not vary with the DTC count.
 903   CM_ARM_EXTENDED_INTERRUPT    DtcInterrupt[4];
 904 } CM_ARM_CMN_600_INFO;
 905
 906 /** A structure that describes the Lpi information.
 907
 908   The Low Power Idle states are described in DSDT/SSDT and associated
 909   to cpus/clusters in the cpu topology.
 910
 911   ID: EArmObjLpiInfo
 912 */
 913 typedef struct CmArmLpiInfo {
 914   /** Minimum Residency. Time in microseconds after which a
 915       state becomes more energy efficient than any shallower state.
 916   */
 917   UINT32                                    MinResidency;
 918
 919   /** Worst case time in microseconds from a wake interrupt
 920       being asserted to the return to a running state
 921   */
 922   UINT32                                    WorstCaseWakeLatency;
 923
 924   /** Flags.
 925   */
 926   UINT32                                    Flags;
 927
 928   /** Architecture specific context loss flags.
 929   */
 930   UINT32                                    ArchFlags;
 931
 932   /** Residency counter frequency in cycles-per-second (Hz).
 933   */
 934   UINT32                                    ResCntFreq;
 935
 936   /** Every shallower power state in the parent is also enabled.
 937   */
 938   UINT32                                    EnableParentState;
 939
 940   /** The EntryMethod _LPI field can be described as an integer
 941       or in a Register resource data descriptor.
 942
 943   If IsInteger is TRUE, the IntegerEntryMethod field is used.
 944   If IsInteger is FALSE, the RegisterEntryMethod field is used.
 945   */
 946   BOOLEAN                                   IsInteger;
 947
 948   /** EntryMethod described as an Integer.
 949   */
 950   UINT64                                    IntegerEntryMethod;
 951
 952   /** EntryMethod described as a EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR.
 953   */
 954   EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE    RegisterEntryMethod;
 955
 956   /** Residency counter register.
 957   */
 958   EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE    ResidencyCounterRegister;
 959
 960   /** Usage counter register.
 961   */
 962   EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE    UsageCounterRegister;
 963
 964   /** String representing the Lpi state
 965   */
 966   CHAR8                                     StateName[16];
 967 } CM_ARM_LPI_INFO;
 968
 969 /** A structure that describes a PCI Address Map.
 970
 971   The memory-ranges used by the PCI bus are described by this object.
 972
 973   ID: EArmObjPciAddressMapInfo
 974 */
 975 typedef struct CmArmPciAddressMapInfo {
 976   /** Pci address space code
 977
 978   Available values are:
 979    - 0: Configuration Space
 980    - 1: I/O Space
 981    - 2: 32-bit-address Memory Space
 982    - 3: 64-bit-address Memory Space
 983   */
 984   UINT8     SpaceCode;
 985
 986   /// PCI address
 987   UINT64    PciAddress;
 988
 989   /// Cpu address
 990   UINT64    CpuAddress;
 991
 992   /// Address size
 993   UINT64    AddressSize;
 994 } CM_ARM_PCI_ADDRESS_MAP_INFO;
 995
 996 /** A structure that describes a PCI Interrupt Map.
 997
 998   The legacy PCI interrupts used by PCI devices are described by this object.
 999
1000   Cf Devicetree Specification - Release v0.3
1001   s2.4.3 "Interrupt Nexus Properties"
1002
1003   ID: EArmObjPciInterruptMapInfo
1004 */
1005 typedef struct CmArmPciInterruptMapInfo {
1006   /// Pci Bus.
1007   /// Value on 8 bits (max 255).
1008   UINT8    PciBus;
1009
1010   /// Pci Bus.
1011   /// Value on 5 bits (max 31).
1012   UINT8    PciDevice;
1013
1014   /** PCI interrupt
1015
1016   ACPI bindings are used:
1017   Cf. ACPI 6.4, s6.2.13 _PRT (PCI Routing Table):
1018       "0-INTA, 1-INTB, 2-INTC, 3-INTD"
1019
1020   Device-tree bindings are shifted by 1:
1021       "INTA=1, INTB=2, INTC=3, INTD=4"
1022   */
1023   UINT8                       PciInterrupt;
1024
1025   /** Interrupt controller interrupt.
1026
1027   Cf Devicetree Specification - Release v0.3
1028   s2.4.3 "Interrupt Nexus Properties": "parent interrupt specifier"
1029   */
1030   CM_ARM_GENERIC_INTERRUPT    IntcInterrupt;
1031 } CM_ARM_PCI_INTERRUPT_MAP_INFO;
1032
1033 /** A structure that describes the
1034     RMR node for the Platform.
1035
1036     ID: EArmObjRmr
1037 */
1038 typedef struct CmArmRmrNode {
1039   /// An unique token used to identify this object
1040   CM_OBJECT_TOKEN    Token;
1041   /// Number of ID mappings
1042   UINT32             IdMappingCount;
1043   /// Reference token for the ID mapping array
1044   CM_OBJECT_TOKEN    IdMappingToken;
1045
1046   /// Unique identifier for this node.
1047   UINT32             Identifier;
1048
1049   /// Reserved Memory Range flags.
1050   UINT32             Flags;
1051
1052   /// Memory range descriptor count.
1053   UINT32             MemRangeDescCount;
1054   /// Reference token for the Memory Range descriptor array
1055   CM_OBJECT_TOKEN    MemRangeDescToken;
1056 } CM_ARM_RMR_NODE;
1057
1058 /** A structure that describes the
1059     Memory Range descriptor.
1060
1061     ID: EArmObjMemoryRangeDescriptor
1062 */
1063 typedef struct CmArmRmrDescriptor {
1064   /// Base address of Reserved Memory Range,
1065   /// aligned to a page size of 64K.
1066   UINT64    BaseAddress;
1067
1068   /// Length of the Reserved Memory range.
1069   /// Must be a multiple of the page size of 64K.
1070   UINT64    Length;
1071 } CM_ARM_MEMORY_RANGE_DESCRIPTOR;
1072
1073 #pragma pack()
1074
1075 #endif // ARM_NAMESPACE_OBJECTS_H_