3 Copyright (c) 2017 - 2022, Arm Limited. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
8 - Cm or CM - Configuration Manager
10 - Std or STD - Standard
13 #ifndef ARM_NAMESPACE_OBJECTS_H_
14 #define ARM_NAMESPACE_OBJECTS_H_
16 #include <StandardNameSpaceObjects.h>
20 /** The EARM_OBJECT_ID enum describes the Object IDs
23 typedef enum ArmObjectID
{
24 EArmObjReserved
, ///< 0 - Reserved
25 EArmObjBootArchInfo
, ///< 1 - Boot Architecture Info
26 EArmObjCpuInfo
, ///< 2 - CPU Info
27 EArmObjPowerManagementProfileInfo
, ///< 3 - Power Management Profile Info
28 EArmObjGicCInfo
, ///< 4 - GIC CPU Interface Info
29 EArmObjGicDInfo
, ///< 5 - GIC Distributor Info
30 EArmObjGicMsiFrameInfo
, ///< 6 - GIC MSI Frame Info
31 EArmObjGicRedistributorInfo
, ///< 7 - GIC Redistributor Info
32 EArmObjGicItsInfo
, ///< 8 - GIC ITS Info
33 EArmObjSerialConsolePortInfo
, ///< 9 - Serial Console Port Info
34 EArmObjSerialDebugPortInfo
, ///< 10 - Serial Debug Port Info
35 EArmObjGenericTimerInfo
, ///< 11 - Generic Timer Info
36 EArmObjPlatformGTBlockInfo
, ///< 12 - Platform GT Block Info
37 EArmObjGTBlockTimerFrameInfo
, ///< 13 - Generic Timer Block Frame Info
38 EArmObjPlatformGenericWatchdogInfo
, ///< 14 - Platform Generic Watchdog
39 EArmObjPciConfigSpaceInfo
, ///< 15 - PCI Configuration Space Info
40 EArmObjHypervisorVendorIdentity
, ///< 16 - Hypervisor Vendor Id
41 EArmObjFixedFeatureFlags
, ///< 17 - Fixed feature flags for FADT
42 EArmObjItsGroup
, ///< 18 - ITS Group
43 EArmObjNamedComponent
, ///< 19 - Named Component
44 EArmObjRootComplex
, ///< 20 - Root Complex
45 EArmObjSmmuV1SmmuV2
, ///< 21 - SMMUv1 or SMMUv2
46 EArmObjSmmuV3
, ///< 22 - SMMUv3
47 EArmObjPmcg
, ///< 23 - PMCG
48 EArmObjGicItsIdentifierArray
, ///< 24 - GIC ITS Identifier Array
49 EArmObjIdMappingArray
, ///< 25 - ID Mapping Array
50 EArmObjSmmuInterruptArray
, ///< 26 - SMMU Interrupt Array
51 EArmObjProcHierarchyInfo
, ///< 27 - Processor Hierarchy Info
52 EArmObjCacheInfo
, ///< 28 - Cache Info
53 EArmObjReserved29
, ///< 29 - Reserved
54 EArmObjCmRef
, ///< 30 - CM Object Reference
55 EArmObjMemoryAffinityInfo
, ///< 31 - Memory Affinity Info
56 EArmObjDeviceHandleAcpi
, ///< 32 - Device Handle Acpi
57 EArmObjDeviceHandlePci
, ///< 33 - Device Handle Pci
58 EArmObjGenericInitiatorAffinityInfo
, ///< 34 - Generic Initiator Affinity
59 EArmObjSerialPortInfo
, ///< 35 - Generic Serial Port Info
60 EArmObjCmn600Info
, ///< 36 - CMN-600 Info
61 EArmObjLpiInfo
, ///< 37 - Lpi Info
62 EArmObjPciAddressMapInfo
, ///< 38 - Pci Address Map Info
63 EArmObjPciInterruptMapInfo
, ///< 39 - Pci Interrupt Map Info
64 EArmObjRmr
, ///< 40 - Reserved Memory Range Node
65 EArmObjMemoryRangeDescriptor
, ///< 41 - Memory Range Descriptor
69 /** A structure that describes the
70 ARM Boot Architecture flags.
72 ID: EArmObjBootArchInfo
74 typedef struct CmArmBootArchInfo
{
75 /** This is the ARM_BOOT_ARCH flags field of the FADT Table
76 described in the ACPI Table Specification.
79 } CM_ARM_BOOT_ARCH_INFO
;
81 /** A structure that describes the
82 Power Management Profile Information for the Platform.
84 ID: EArmObjPowerManagementProfileInfo
86 typedef struct CmArmPowerManagementProfileInfo
{
87 /** This is the Preferred_PM_Profile field of the FADT Table
88 described in the ACPI Specification
90 UINT8 PowerManagementProfile
;
91 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO
;
93 /** A structure that describes the
94 GIC CPU Interface for the Platform.
98 typedef struct CmArmGicCInfo
{
99 /// The GIC CPU Interface number.
100 UINT32 CPUInterfaceNumber
;
102 /** The ACPI Processor UID. This must match the
103 _UID of the CPU Device object information described
104 in the DSDT/SSDT for the CPU.
106 UINT32 AcpiProcessorUid
;
108 /** The flags field as described by the GICC structure
109 in the ACPI Specification.
113 /** The parking protocol version field as described by
114 the GICC structure in the ACPI Specification.
116 UINT32 ParkingProtocolVersion
;
118 /** The Performance Interrupt field as described by
119 the GICC structure in the ACPI Specification.
121 UINT32 PerformanceInterruptGsiv
;
123 /** The CPU Parked address field as described by
124 the GICC structure in the ACPI Specification.
126 UINT64 ParkedAddress
;
128 /** The base address for the GIC CPU Interface
129 as described by the GICC structure in the
132 UINT64 PhysicalBaseAddress
;
134 /** The base address for GICV interface
135 as described by the GICC structure in the
140 /** The base address for GICH interface
141 as described by the GICC structure in the
146 /** The GICV maintenance interrupt
147 as described by the GICC structure in the
150 UINT32 VGICMaintenanceInterrupt
;
152 /** The base address for GICR interface
153 as described by the GICC structure in the
156 UINT64 GICRBaseAddress
;
158 /** The MPIDR for the CPU
159 as described by the GICC structure in the
164 /** The Processor Power Efficiency class
165 as described by the GICC structure in the
168 UINT8 ProcessorPowerEfficiencyClass
;
170 /** Statistical Profiling Extension buffer overflow GSIV. Zero if
171 unsupported by this processor. This field was introduced in
172 ACPI 6.3 (MADT revision 5) and is therefore ignored when
173 generating MADT revision 4 or lower.
175 UINT16 SpeOverflowInterrupt
;
177 /** The proximity domain to which the logical processor belongs.
178 This field is used to populate the GICC affinity structure
181 UINT32 ProximityDomain
;
183 /** The clock domain to which the logical processor belongs.
184 This field is used to populate the GICC affinity structure
189 /** The GICC Affinity flags field as described by the GICC Affinity structure
192 UINT32 AffinityFlags
;
195 /** A structure that describes the
196 GIC Distributor information for the Platform.
200 typedef struct CmArmGicDInfo
{
201 /// The Physical Base address for the GIC Distributor.
202 UINT64 PhysicalBaseAddress
;
204 /** The global system interrupt
205 number where this GIC Distributor's
206 interrupt inputs start.
208 UINT32 SystemVectorBase
;
210 /** The GIC version as described
211 by the GICD structure in the
217 /** A structure that describes the
218 GIC MSI Frame information for the Platform.
220 ID: EArmObjGicMsiFrameInfo
222 typedef struct CmArmGicMsiFrameInfo
{
223 /// The GIC MSI Frame ID
224 UINT32 GicMsiFrameId
;
226 /// The Physical base address for the MSI Frame
227 UINT64 PhysicalBaseAddress
;
229 /** The GIC MSI Frame flags
230 as described by the GIC MSI frame
231 structure in the ACPI Specification.
235 /// SPI Count used by this frame
238 /// SPI Base used by this frame
240 } CM_ARM_GIC_MSI_FRAME_INFO
;
242 /** A structure that describes the
243 GIC Redistributor information for the Platform.
245 ID: EArmObjGicRedistributorInfo
247 typedef struct CmArmGicRedistInfo
{
248 /** The physical address of a page range
249 containing all GIC Redistributors.
251 UINT64 DiscoveryRangeBaseAddress
;
253 /// Length of the GIC Redistributor Discovery page range
254 UINT32 DiscoveryRangeLength
;
255 } CM_ARM_GIC_REDIST_INFO
;
257 /** A structure that describes the
258 GIC Interrupt Translation Service information for the Platform.
260 ID: EArmObjGicItsInfo
262 typedef struct CmArmGicItsInfo
{
266 /// The physical address for the Interrupt Translation Service
267 UINT64 PhysicalBaseAddress
;
269 /** The proximity domain to which the logical processor belongs.
270 This field is used to populate the GIC ITS affinity structure
273 UINT32 ProximityDomain
;
274 } CM_ARM_GIC_ITS_INFO
;
276 /** A structure that describes the
277 Serial Port information for the Platform.
279 ID: EArmObjSerialConsolePortInfo or
280 EArmObjSerialDebugPortInfo or
281 EArmObjSerialPortInfo
283 typedef struct CmArmSerialPortInfo
{
284 /// The physical base address for the serial port
287 /// The serial port interrupt
290 /// The serial port baud rate
293 /// The serial port clock
296 /// Serial Port subtype
299 /// The Base address length
300 UINT64 BaseAddressLength
;
304 } CM_ARM_SERIAL_PORT_INFO
;
306 /** A structure that describes the
307 Generic Timer information for the Platform.
309 ID: EArmObjGenericTimerInfo
311 typedef struct CmArmGenericTimerInfo
{
312 /// The physical base address for the counter control frame
313 UINT64 CounterControlBaseAddress
;
315 /// The physical base address for the counter read frame
316 UINT64 CounterReadBaseAddress
;
318 /// The secure PL1 timer interrupt
319 UINT32 SecurePL1TimerGSIV
;
321 /// The secure PL1 timer flags
322 UINT32 SecurePL1TimerFlags
;
324 /// The non-secure PL1 timer interrupt
325 UINT32 NonSecurePL1TimerGSIV
;
327 /// The non-secure PL1 timer flags
328 UINT32 NonSecurePL1TimerFlags
;
330 /// The virtual timer interrupt
331 UINT32 VirtualTimerGSIV
;
333 /// The virtual timer flags
334 UINT32 VirtualTimerFlags
;
336 /// The non-secure PL2 timer interrupt
337 UINT32 NonSecurePL2TimerGSIV
;
339 /// The non-secure PL2 timer flags
340 UINT32 NonSecurePL2TimerFlags
;
342 /// GSIV for the virtual EL2 timer
343 UINT32 VirtualPL2TimerGSIV
;
345 /// Flags for the virtual EL2 timer
346 UINT32 VirtualPL2TimerFlags
;
347 } CM_ARM_GENERIC_TIMER_INFO
;
349 /** A structure that describes the
350 Platform Generic Block Timer Frame information for the Platform.
352 ID: EArmObjGTBlockTimerFrameInfo
354 typedef struct CmArmGTBlockTimerFrameInfo
{
355 /// The Generic Timer frame number
358 /// The physical base address for the CntBase block
359 UINT64 PhysicalAddressCntBase
;
361 /// The physical base address for the CntEL0Base block
362 UINT64 PhysicalAddressCntEL0Base
;
364 /// The physical timer interrupt
365 UINT32 PhysicalTimerGSIV
;
367 /** The physical timer flags as described by the GT Block
368 Timer frame Structure in the ACPI Specification.
370 UINT32 PhysicalTimerFlags
;
372 /// The virtual timer interrupt
373 UINT32 VirtualTimerGSIV
;
375 /** The virtual timer flags as described by the GT Block
376 Timer frame Structure in the ACPI Specification.
378 UINT32 VirtualTimerFlags
;
380 /** The common timer flags as described by the GT Block
381 Timer frame Structure in the ACPI Specification.
384 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO
;
386 /** A structure that describes the
387 Platform Generic Block Timer information for the Platform.
389 ID: EArmObjPlatformGTBlockInfo
391 typedef struct CmArmGTBlockInfo
{
392 /// The physical base address for the GT Block Timer structure
393 UINT64 GTBlockPhysicalAddress
;
395 /// The number of timer frames implemented in the GT Block
396 UINT32 GTBlockTimerFrameCount
;
398 /// Reference token for the GT Block timer frame list
399 CM_OBJECT_TOKEN GTBlockTimerFrameToken
;
400 } CM_ARM_GTBLOCK_INFO
;
402 /** A structure that describes the
403 Arm Generic Watchdog information for the Platform.
405 ID: EArmObjPlatformGenericWatchdogInfo
407 typedef struct CmArmGenericWatchdogInfo
{
408 /// The physical base address of the Arm Watchdog control frame
409 UINT64 ControlFrameAddress
;
411 /// The physical base address of the Arm Watchdog refresh frame
412 UINT64 RefreshFrameAddress
;
414 /// The watchdog interrupt
417 /** The flags for the watchdog as described by the Arm watchdog
418 structure in the ACPI specification.
421 } CM_ARM_GENERIC_WATCHDOG_INFO
;
423 /** A structure that describes the
424 PCI Configuration Space information for the Platform.
426 ID: EArmObjPciConfigSpaceInfo
428 typedef struct CmArmPciConfigSpaceInfo
{
429 /// The physical base address for the PCI segment
432 /// The PCI segment group number
433 UINT16 PciSegmentGroupNumber
;
435 /// The start bus number
436 UINT8 StartBusNumber
;
438 /// The end bus number
441 /// Optional field: Reference Token for address mapping.
442 /// Token identifying a CM_ARM_OBJ_REF structure.
443 CM_OBJECT_TOKEN AddressMapToken
;
445 /// Optional field: Reference Token for interrupt mapping.
446 /// Token identifying a CM_ARM_OBJ_REF structure.
447 CM_OBJECT_TOKEN InterruptMapToken
;
448 } CM_ARM_PCI_CONFIG_SPACE_INFO
;
450 /** A structure that describes the
451 Hypervisor Vendor ID information for the Platform.
453 ID: EArmObjHypervisorVendorIdentity
455 typedef struct CmArmHypervisorVendorId
{
456 /// The hypervisor Vendor ID
457 UINT64 HypervisorVendorId
;
458 } CM_ARM_HYPERVISOR_VENDOR_ID
;
460 /** A structure that describes the
461 Fixed feature flags for the Platform.
463 ID: EArmObjFixedFeatureFlags
465 typedef struct CmArmFixedFeatureFlags
{
466 /// The Fixed feature flags
468 } CM_ARM_FIXED_FEATURE_FLAGS
;
470 /** A structure that describes the
471 ITS Group node for the Platform.
475 typedef struct CmArmItsGroupNode
{
476 /// An unique token used to identify this object
477 CM_OBJECT_TOKEN Token
;
478 /// The number of ITS identifiers in the ITS node
480 /// Reference token for the ITS identifier array
481 CM_OBJECT_TOKEN ItsIdToken
;
483 /// Unique identifier for this node.
485 } CM_ARM_ITS_GROUP_NODE
;
487 /** A structure that describes the
488 Named component node for the Platform.
490 ID: EArmObjNamedComponent
492 typedef struct CmArmNamedComponentNode
{
493 /// An unique token used to identify this object
494 CM_OBJECT_TOKEN Token
;
495 /// Number of ID mappings
496 UINT32 IdMappingCount
;
497 /// Reference token for the ID mapping array
498 CM_OBJECT_TOKEN IdMappingToken
;
500 /// Flags for the named component
503 /// Memory access properties : Cache coherent attributes
504 UINT32 CacheCoherent
;
505 /// Memory access properties : Allocation hints
506 UINT8 AllocationHints
;
507 /// Memory access properties : Memory access flags
508 UINT8 MemoryAccessFlags
;
510 /// Memory access properties : Address size limit
511 UINT8 AddressSizeLimit
;
513 /** ASCII Null terminated string with the full path to
514 the entry in the namespace for this object.
518 /// Unique identifier for this node.
520 } CM_ARM_NAMED_COMPONENT_NODE
;
522 /** A structure that describes the
523 Root complex node for the Platform.
525 ID: EArmObjRootComplex
527 typedef struct CmArmRootComplexNode
{
528 /// An unique token used to identify this object
529 CM_OBJECT_TOKEN Token
;
530 /// Number of ID mappings
531 UINT32 IdMappingCount
;
532 /// Reference token for the ID mapping array
533 CM_OBJECT_TOKEN IdMappingToken
;
535 /// Memory access properties : Cache coherent attributes
536 UINT32 CacheCoherent
;
537 /// Memory access properties : Allocation hints
538 UINT8 AllocationHints
;
539 /// Memory access properties : Memory access flags
540 UINT8 MemoryAccessFlags
;
544 /// PCI segment number
545 UINT32 PciSegmentNumber
;
546 /// Memory address size limit
547 UINT8 MemoryAddressSize
;
548 /// PASID capabilities
549 UINT16 PasidCapabilities
;
553 /// Unique identifier for this node.
555 } CM_ARM_ROOT_COMPLEX_NODE
;
557 /** A structure that describes the
558 SMMUv1 or SMMUv2 node for the Platform.
560 ID: EArmObjSmmuV1SmmuV2
562 typedef struct CmArmSmmuV1SmmuV2Node
{
563 /// An unique token used to identify this object
564 CM_OBJECT_TOKEN Token
;
565 /// Number of ID mappings
566 UINT32 IdMappingCount
;
567 /// Reference token for the ID mapping array
568 CM_OBJECT_TOKEN IdMappingToken
;
570 /// SMMU Base Address
572 /// Length of the memory range covered by the SMMU
579 /// Number of context interrupts
580 UINT32 ContextInterruptCount
;
581 /// Reference token for the context interrupt array
582 CM_OBJECT_TOKEN ContextInterruptToken
;
584 /// Number of PMU interrupts
585 UINT32 PmuInterruptCount
;
586 /// Reference token for the PMU interrupt array
587 CM_OBJECT_TOKEN PmuInterruptToken
;
589 /// GSIV of the SMMU_NSgIrpt interrupt
591 /// SMMU_NSgIrpt interrupt flags
592 UINT32 SMMU_NSgIrptFlags
;
593 /// GSIV of the SMMU_NSgCfgIrpt interrupt
594 UINT32 SMMU_NSgCfgIrpt
;
595 /// SMMU_NSgCfgIrpt interrupt flags
596 UINT32 SMMU_NSgCfgIrptFlags
;
598 /// Unique identifier for this node.
600 } CM_ARM_SMMUV1_SMMUV2_NODE
;
602 /** A structure that describes the
603 SMMUv3 node for the Platform.
607 typedef struct CmArmSmmuV3Node
{
608 /// An unique token used to identify this object
609 CM_OBJECT_TOKEN Token
;
610 /// Number of ID mappings
611 UINT32 IdMappingCount
;
612 /// Reference token for the ID mapping array
613 CM_OBJECT_TOKEN IdMappingToken
;
615 /// SMMU Base Address
623 /// GSIV of the Event interrupt if SPI based
624 UINT32 EventInterrupt
;
625 /// PRI Interrupt if SPI based
627 /// GERR interrupt if GSIV based
628 UINT32 GerrInterrupt
;
629 /// Sync interrupt if GSIV based
630 UINT32 SyncInterrupt
;
632 /// Proximity domain flag
633 UINT32 ProximityDomain
;
634 /// Index into the array of ID mapping
635 UINT32 DeviceIdMappingIndex
;
637 /// Unique identifier for this node.
639 } CM_ARM_SMMUV3_NODE
;
641 /** A structure that describes the
642 PMCG node for the Platform.
646 typedef struct CmArmPmcgNode
{
647 /// An unique token used to identify this object
648 CM_OBJECT_TOKEN Token
;
649 /// Number of ID mappings
650 UINT32 IdMappingCount
;
651 /// Reference token for the ID mapping array
652 CM_OBJECT_TOKEN IdMappingToken
;
654 /// Base Address for performance monitor counter group
656 /// GSIV for the Overflow interrupt
657 UINT32 OverflowInterrupt
;
658 /// Page 1 Base address
659 UINT64 Page1BaseAddress
;
661 /// Reference token for the IORT node associated with this node
662 CM_OBJECT_TOKEN ReferenceToken
;
664 /// Unique identifier for this node.
668 /** A structure that describes the
669 GIC ITS Identifiers for an ITS Group node.
671 ID: EArmObjGicItsIdentifierArray
673 typedef struct CmArmGicItsIdentifier
{
674 /// The ITS Identifier
676 } CM_ARM_ITS_IDENTIFIER
;
678 /** A structure that describes the
679 ID Mappings for the Platform.
681 ID: EArmObjIdMappingArray
683 typedef struct CmArmIdMapping
{
686 /// Number of input IDs
690 /// Reference token for the output node
691 CM_OBJECT_TOKEN OutputReferenceToken
;
696 /** A structure that describes the Arm
699 typedef struct CmArmGenericInterrupt
{
704 /// BIT0: 0: Interrupt is Level triggered
705 /// 1: Interrupt is Edge triggered
706 /// BIT1: 0: Interrupt is Active high
707 /// 1: Interrupt is Active low
709 } CM_ARM_GENERIC_INTERRUPT
;
711 /** A structure that describes the SMMU interrupts for the Platform.
713 Interrupt Interrupt number.
714 Flags Interrupt flags as defined for SMMU node.
716 ID: EArmObjSmmuInterruptArray
718 typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_SMMU_INTERRUPT
;
720 /** A structure that describes the AML Extended Interrupts.
722 Interrupt Interrupt number.
723 Flags Interrupt flags as defined by the Interrupt
724 Vector Flags (Byte 3) of the Extended Interrupt
726 See EFI_ACPI_EXTENDED_INTERRUPT_FLAG_xxx in Acpi10.h
728 typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_EXTENDED_INTERRUPT
;
730 /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT
732 ID: EArmObjProcHierarchyInfo
734 typedef struct CmArmProcHierarchyInfo
{
735 /// A unique token used to identify this object
736 CM_OBJECT_TOKEN Token
;
737 /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)
739 /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor
740 /// topology. A value of CM_NULL_TOKEN means this node has no parent.
741 CM_OBJECT_TOKEN ParentToken
;
742 /// Token of the associated CM_ARM_GICC_INFO object which has the
743 /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this
744 /// node represents a group of associated processors and it does not have an
745 /// associated GIC CPU interface.
746 CM_OBJECT_TOKEN GicCToken
;
747 /// Number of resources private to this Node
748 UINT32 NoOfPrivateResources
;
749 /// Token of the array which contains references to the resources private to
750 /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if
751 /// the NoOfPrivateResources is 0, in which case it is recommended to set
752 /// this field to CM_NULL_TOKEN.
753 CM_OBJECT_TOKEN PrivateResourcesArrayToken
;
754 /// Optional field: Reference Token for the Lpi state of this processor.
755 /// Token identifying a CM_ARM_OBJ_REF structure, itself referencing
756 /// CM_ARM_LPI_INFO objects.
757 CM_OBJECT_TOKEN LpiToken
;
758 } CM_ARM_PROC_HIERARCHY_INFO
;
760 /** A structure that describes the Cache Type Structure (Type 1) in PPTT
764 typedef struct CmArmCacheInfo
{
765 /// A unique token used to identify this object
766 CM_OBJECT_TOKEN Token
;
767 /// Reference token for the next level of cache that is private to the same
768 /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this
769 /// entry represents the last cache level appropriate to the processor
770 /// hierarchy node structures using this entry.
771 CM_OBJECT_TOKEN NextLevelOfCacheToken
;
772 /// Size of the cache in bytes
774 /// Number of sets in the cache
776 /// Integer number of ways. The maximum associativity supported by
777 /// ACPI Cache type structure is limited to MAX_UINT8. However,
778 /// the maximum number of ways supported by the architecture is
779 /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field
781 UINT32 Associativity
;
782 /// Cache attributes (ACPI 6.4 - January 2021, PPTT, Table 5.140)
784 /// Line size in bytes
786 /// Unique ID for the cache
790 /** A structure that describes a reference to another Configuration Manager
793 This is useful for creating an array of reference tokens. The framework
794 can then query the configuration manager for these arrays using the
795 object ID EArmObjCmRef.
797 This can be used is to represent one-to-many relationships between objects.
801 typedef struct CmArmObjRef
{
802 /// Token of the CM object being referenced
803 CM_OBJECT_TOKEN ReferenceToken
;
806 /** A structure that describes the Memory Affinity Structure (Type 1) in SRAT
808 ID: EArmObjMemoryAffinityInfo
810 typedef struct CmArmMemoryAffinityInfo
{
811 /// The proximity domain to which the "range of memory" belongs.
812 UINT32 ProximityDomain
;
822 } CM_ARM_MEMORY_AFFINITY_INFO
;
824 /** A structure that describes the ACPI Device Handle (Type 0) in the
825 Generic Initiator Affinity structure in SRAT
827 ID: EArmObjDeviceHandleAcpi
829 typedef struct CmArmDeviceHandleAcpi
{
835 } CM_ARM_DEVICE_HANDLE_ACPI
;
837 /** A structure that describes the PCI Device Handle (Type 1) in the
838 Generic Initiator Affinity structure in SRAT
840 ID: EArmObjDeviceHandlePci
842 typedef struct CmArmDeviceHandlePci
{
843 /// PCI Segment Number
844 UINT16 SegmentNumber
;
846 /// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)
849 /// PCI Device Number - Max 32 devices (Bits 7:3 of BDF)
852 /// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)
853 UINT8 FunctionNumber
;
854 } CM_ARM_DEVICE_HANDLE_PCI
;
856 /** A structure that describes the Generic Initiator Affinity structure in SRAT
858 ID: EArmObjGenericInitiatorAffinityInfo
860 typedef struct CmArmGenericInitiatorAffinityInfo
{
861 /// The proximity domain to which the generic initiator belongs.
862 UINT32 ProximityDomain
;
867 /// Device Handle Type
868 UINT8 DeviceHandleType
;
870 /// Reference Token for the Device Handle
871 CM_OBJECT_TOKEN DeviceHandleToken
;
872 } CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO
;
874 /** A structure that describes the CMN-600 hardware.
876 ID: EArmObjCmn600Info
878 typedef struct CmArmCmn600Info
{
879 /// The PERIPHBASE address.
880 /// Corresponds to the Configuration Node Region (CFGR) base address.
881 UINT64 PeriphBaseAddress
;
883 /// The PERIPHBASE address length.
884 /// Corresponds to the CFGR base address length.
885 UINT64 PeriphBaseAddressLength
;
887 /// The ROOTNODEBASE address.
888 /// Corresponds to the Root node (ROOT) base address.
889 UINT64 RootNodeBaseAddress
;
891 /// The Debug and Trace Logic Controller (DTC) count.
892 /// CMN-600 can have maximum 4 DTCs.
895 /// DTC Interrupt list.
896 /// The first interrupt resource descriptor pertains to
897 /// DTC[0], the second to DTC[1] and so on.
898 /// DtcCount determines the number of DTC Interrupts that
899 /// are populated. If DTC count is 2 then DtcInterrupt[2]
900 /// and DtcInterrupt[3] are ignored.
901 /// Note: The size of CM_ARM_CMN_600_INFO structure remains
902 /// constant and does not vary with the DTC count.
903 CM_ARM_EXTENDED_INTERRUPT DtcInterrupt
[4];
904 } CM_ARM_CMN_600_INFO
;
906 /** A structure that describes the Lpi information.
908 The Low Power Idle states are described in DSDT/SSDT and associated
909 to cpus/clusters in the cpu topology.
913 typedef struct CmArmLpiInfo
{
914 /** Minimum Residency. Time in microseconds after which a
915 state becomes more energy efficient than any shallower state.
919 /** Worst case time in microseconds from a wake interrupt
920 being asserted to the return to a running state
922 UINT32 WorstCaseWakeLatency
;
928 /** Architecture specific context loss flags.
932 /** Residency counter frequency in cycles-per-second (Hz).
936 /** Every shallower power state in the parent is also enabled.
938 UINT32 EnableParentState
;
940 /** The EntryMethod _LPI field can be described as an integer
941 or in a Register resource data descriptor.
943 If IsInteger is TRUE, the IntegerEntryMethod field is used.
944 If IsInteger is FALSE, the RegisterEntryMethod field is used.
948 /** EntryMethod described as an Integer.
950 UINT64 IntegerEntryMethod
;
952 /** EntryMethod described as a EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR.
954 EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterEntryMethod
;
956 /** Residency counter register.
958 EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResidencyCounterRegister
;
960 /** Usage counter register.
962 EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE UsageCounterRegister
;
964 /** String representing the Lpi state
969 /** A structure that describes a PCI Address Map.
971 The memory-ranges used by the PCI bus are described by this object.
973 ID: EArmObjPciAddressMapInfo
975 typedef struct CmArmPciAddressMapInfo
{
976 /** Pci address space code
978 Available values are:
979 - 0: Configuration Space
981 - 2: 32-bit-address Memory Space
982 - 3: 64-bit-address Memory Space
994 } CM_ARM_PCI_ADDRESS_MAP_INFO
;
996 /** A structure that describes a PCI Interrupt Map.
998 The legacy PCI interrupts used by PCI devices are described by this object.
1000 Cf Devicetree Specification - Release v0.3
1001 s2.4.3 "Interrupt Nexus Properties"
1003 ID: EArmObjPciInterruptMapInfo
1005 typedef struct CmArmPciInterruptMapInfo
{
1007 /// Value on 8 bits (max 255).
1011 /// Value on 5 bits (max 31).
1016 ACPI bindings are used:
1017 Cf. ACPI 6.4, s6.2.13 _PRT (PCI Routing Table):
1018 "0-INTA, 1-INTB, 2-INTC, 3-INTD"
1020 Device-tree bindings are shifted by 1:
1021 "INTA=1, INTB=2, INTC=3, INTD=4"
1025 /** Interrupt controller interrupt.
1027 Cf Devicetree Specification - Release v0.3
1028 s2.4.3 "Interrupt Nexus Properties": "parent interrupt specifier"
1030 CM_ARM_GENERIC_INTERRUPT IntcInterrupt
;
1031 } CM_ARM_PCI_INTERRUPT_MAP_INFO
;
1033 /** A structure that describes the
1034 RMR node for the Platform.
1038 typedef struct CmArmRmrNode
{
1039 /// An unique token used to identify this object
1040 CM_OBJECT_TOKEN Token
;
1041 /// Number of ID mappings
1042 UINT32 IdMappingCount
;
1043 /// Reference token for the ID mapping array
1044 CM_OBJECT_TOKEN IdMappingToken
;
1046 /// Unique identifier for this node.
1049 /// Reserved Memory Range flags.
1052 /// Memory range descriptor count.
1053 UINT32 MemRangeDescCount
;
1054 /// Reference token for the Memory Range descriptor array
1055 CM_OBJECT_TOKEN MemRangeDescToken
;
1058 /** A structure that describes the
1059 Memory Range descriptor.
1061 ID: EArmObjMemoryRangeDescriptor
1063 typedef struct CmArmRmrDescriptor
{
1064 /// Base address of Reserved Memory Range,
1065 /// aligned to a page size of 64K.
1068 /// Length of the Reserved Memory range.
1069 /// Must be a multiple of the page size of 64K.
1071 } CM_ARM_MEMORY_RANGE_DESCRIPTOR
;
1075 #endif // ARM_NAMESPACE_OBJECTS_H_