DynamicTablesPkg/Include/ArmNameSpaceObjects.h

   1 /** @file
   2
   3   Copyright (c) 2017 - 2022, Arm Limited. All rights reserved.<BR>
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7   @par Glossary:
   8     - Cm or CM   - Configuration Manager
   9     - Obj or OBJ - Object
  10     - Std or STD - Standard
  11 **/
  12
  13 #ifndef ARM_NAMESPACE_OBJECTS_H_
  14 #define ARM_NAMESPACE_OBJECTS_H_
  15
  16 #include <AmlCpcInfo.h>
  17 #include <StandardNameSpaceObjects.h>
  18
  19 #pragma pack(1)
  20
  21 /** The EARM_OBJECT_ID enum describes the Object IDs
  22     in the ARM Namespace
  23 */
  24 typedef enum ArmObjectID {
  25   EArmObjReserved,                                             ///<  0 - Reserved
  26   EArmObjBootArchInfo,                                         ///<  1 - Boot Architecture Info
  27   EArmObjCpuInfo,                                              ///<  2 - CPU Info
  28   EArmObjPowerManagementProfileInfo,                           ///<  3 - Power Management Profile Info
  29   EArmObjGicCInfo,                                             ///<  4 - GIC CPU Interface Info
  30   EArmObjGicDInfo,                                             ///<  5 - GIC Distributor Info
  31   EArmObjGicMsiFrameInfo,                                      ///<  6 - GIC MSI Frame Info
  32   EArmObjGicRedistributorInfo,                                 ///<  7 - GIC Redistributor Info
  33   EArmObjGicItsInfo,                                           ///<  8 - GIC ITS Info
  34   EArmObjSerialConsolePortInfo,                                ///<  9 - Serial Console Port Info
  35   EArmObjSerialDebugPortInfo,                                  ///< 10 - Serial Debug Port Info
  36   EArmObjGenericTimerInfo,                                     ///< 11 - Generic Timer Info
  37   EArmObjPlatformGTBlockInfo,                                  ///< 12 - Platform GT Block Info
  38   EArmObjGTBlockTimerFrameInfo,                                ///< 13 - Generic Timer Block Frame Info
  39   EArmObjPlatformGenericWatchdogInfo,                          ///< 14 - Platform Generic Watchdog
  40   EArmObjPciConfigSpaceInfo,                                   ///< 15 - PCI Configuration Space Info
  41   EArmObjHypervisorVendorIdentity,                             ///< 16 - Hypervisor Vendor Id
  42   EArmObjFixedFeatureFlags,                                    ///< 17 - Fixed feature flags for FADT
  43   EArmObjItsGroup,                                             ///< 18 - ITS Group
  44   EArmObjNamedComponent,                                       ///< 19 - Named Component
  45   EArmObjRootComplex,                                          ///< 20 - Root Complex
  46   EArmObjSmmuV1SmmuV2,                                         ///< 21 - SMMUv1 or SMMUv2
  47   EArmObjSmmuV3,                                               ///< 22 - SMMUv3
  48   EArmObjPmcg,                                                 ///< 23 - PMCG
  49   EArmObjGicItsIdentifierArray,                                ///< 24 - GIC ITS Identifier Array
  50   EArmObjIdMappingArray,                                       ///< 25 - ID Mapping Array
  51   EArmObjSmmuInterruptArray,                                   ///< 26 - SMMU Interrupt Array
  52   EArmObjProcHierarchyInfo,                                    ///< 27 - Processor Hierarchy Info
  53   EArmObjCacheInfo,                                            ///< 28 - Cache Info
  54   EArmObjReserved29,                                           ///< 29 - Reserved
  55   EArmObjCmRef,                                                ///< 30 - CM Object Reference
  56   EArmObjMemoryAffinityInfo,                                   ///< 31 - Memory Affinity Info
  57   EArmObjDeviceHandleAcpi,                                     ///< 32 - Device Handle Acpi
  58   EArmObjDeviceHandlePci,                                      ///< 33 - Device Handle Pci
  59   EArmObjGenericInitiatorAffinityInfo,                         ///< 34 - Generic Initiator Affinity
  60   EArmObjSerialPortInfo,                                       ///< 35 - Generic Serial Port Info
  61   EArmObjCmn600Info,                                           ///< 36 - CMN-600 Info
  62   EArmObjLpiInfo,                                              ///< 37 - Lpi Info
  63   EArmObjPciAddressMapInfo,                                    ///< 38 - Pci Address Map Info
  64   EArmObjPciInterruptMapInfo,                                  ///< 39 - Pci Interrupt Map Info
  65   EArmObjRmr,                                                  ///< 40 - Reserved Memory Range Node
  66   EArmObjMemoryRangeDescriptor,                                ///< 41 - Memory Range Descriptor
  67   EArmObjCpcInfo,                                              ///< 42 - Continuous Performance Control Info
  68   EArmObjPccSubspaceType0Info,                                 ///< 43 - Pcc Subspace Type 0 Info
  69   EArmObjPccSubspaceType1Info,                                 ///< 44 - Pcc Subspace Type 2 Info
  70   EArmObjPccSubspaceType2Info,                                 ///< 45 - Pcc Subspace Type 2 Info
  71   EArmObjPccSubspaceType3Info,                                 ///< 46 - Pcc Subspace Type 3 Info
  72   EArmObjPccSubspaceType4Info,                                 ///< 47 - Pcc Subspace Type 4 Info
  73   EArmObjPccSubspaceType5Info,                                 ///< 48 - Pcc Subspace Type 5 Info
  74   EArmObjMax
  75 } EARM_OBJECT_ID;
  76
  77 /** A structure that describes the
  78     ARM Boot Architecture flags.
  79
  80     ID: EArmObjBootArchInfo
  81 */
  82 typedef struct CmArmBootArchInfo {
  83   /** This is the ARM_BOOT_ARCH flags field of the FADT Table
  84       described in the ACPI Table Specification.
  85   */
  86   UINT16    BootArchFlags;
  87 } CM_ARM_BOOT_ARCH_INFO;
  88
  89 /** A structure that describes the
  90     Power Management Profile Information for the Platform.
  91
  92     ID: EArmObjPowerManagementProfileInfo
  93 */
  94 typedef struct CmArmPowerManagementProfileInfo {
  95   /** This is the Preferred_PM_Profile field of the FADT Table
  96       described in the ACPI Specification
  97   */
  98   UINT8    PowerManagementProfile;
  99 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;
 100
 101 /** A structure that describes the
 102     GIC CPU Interface for the Platform.
 103
 104     ID: EArmObjGicCInfo
 105 */
 106 typedef struct CmArmGicCInfo {
 107   /// The GIC CPU Interface number.
 108   UINT32             CPUInterfaceNumber;
 109
 110   /** The ACPI Processor UID. This must match the
 111       _UID of the CPU Device object information described
 112       in the DSDT/SSDT for the CPU.
 113   */
 114   UINT32             AcpiProcessorUid;
 115
 116   /** The flags field as described by the GICC structure
 117       in the ACPI Specification.
 118   */
 119   UINT32             Flags;
 120
 121   /** The parking protocol version field as described by
 122     the GICC structure in the ACPI Specification.
 123   */
 124   UINT32             ParkingProtocolVersion;
 125
 126   /** The Performance Interrupt field as described by
 127       the GICC structure in the ACPI Specification.
 128   */
 129   UINT32             PerformanceInterruptGsiv;
 130
 131   /** The CPU Parked address field as described by
 132       the GICC structure in the ACPI Specification.
 133   */
 134   UINT64             ParkedAddress;
 135
 136   /** The base address for the GIC CPU Interface
 137       as described by the GICC structure in the
 138       ACPI Specification.
 139   */
 140   UINT64             PhysicalBaseAddress;
 141
 142   /** The base address for GICV interface
 143       as described by the GICC structure in the
 144       ACPI Specification.
 145   */
 146   UINT64             GICV;
 147
 148   /** The base address for GICH interface
 149       as described by the GICC structure in the
 150       ACPI Specification.
 151   */
 152   UINT64             GICH;
 153
 154   /** The GICV maintenance interrupt
 155       as described by the GICC structure in the
 156       ACPI Specification.
 157   */
 158   UINT32             VGICMaintenanceInterrupt;
 159
 160   /** The base address for GICR interface
 161       as described by the GICC structure in the
 162       ACPI Specification.
 163   */
 164   UINT64             GICRBaseAddress;
 165
 166   /** The MPIDR for the CPU
 167       as described by the GICC structure in the
 168       ACPI Specification.
 169   */
 170   UINT64             MPIDR;
 171
 172   /** The Processor Power Efficiency class
 173       as described by the GICC structure in the
 174       ACPI Specification.
 175   */
 176   UINT8              ProcessorPowerEfficiencyClass;
 177
 178   /** Statistical Profiling Extension buffer overflow GSIV. Zero if
 179       unsupported by this processor. This field was introduced in
 180       ACPI 6.3 (MADT revision 5) and is therefore ignored when
 181       generating MADT revision 4 or lower.
 182   */
 183   UINT16             SpeOverflowInterrupt;
 184
 185   /** The proximity domain to which the logical processor belongs.
 186       This field is used to populate the GICC affinity structure
 187       in the SRAT table.
 188   */
 189   UINT32             ProximityDomain;
 190
 191   /** The clock domain to which the logical processor belongs.
 192       This field is used to populate the GICC affinity structure
 193       in the SRAT table.
 194   */
 195   UINT32             ClockDomain;
 196
 197   /** The GICC Affinity flags field as described by the GICC Affinity structure
 198       in the SRAT table.
 199   */
 200   UINT32             AffinityFlags;
 201
 202   /** Optional field: Reference Token for the Cpc info of this processor.
 203       i.e. a token referencing a CM_ARM_CPC_INFO object.
 204   */
 205   CM_OBJECT_TOKEN    CpcToken;
 206 } CM_ARM_GICC_INFO;
 207
 208 /** A structure that describes the
 209     GIC Distributor information for the Platform.
 210
 211     ID: EArmObjGicDInfo
 212 */
 213 typedef struct CmArmGicDInfo {
 214   /// The Physical Base address for the GIC Distributor.
 215   UINT64    PhysicalBaseAddress;
 216
 217   /** The global system interrupt
 218       number where this GIC Distributor's
 219       interrupt inputs start.
 220   */
 221   UINT32    SystemVectorBase;
 222
 223   /** The GIC version as described
 224       by the GICD structure in the
 225       ACPI Specification.
 226   */
 227   UINT8     GicVersion;
 228 } CM_ARM_GICD_INFO;
 229
 230 /** A structure that describes the
 231     GIC MSI Frame information for the Platform.
 232
 233     ID: EArmObjGicMsiFrameInfo
 234 */
 235 typedef struct CmArmGicMsiFrameInfo {
 236   /// The GIC MSI Frame ID
 237   UINT32    GicMsiFrameId;
 238
 239   /// The Physical base address for the MSI Frame
 240   UINT64    PhysicalBaseAddress;
 241
 242   /** The GIC MSI Frame flags
 243       as described by the GIC MSI frame
 244       structure in the ACPI Specification.
 245   */
 246   UINT32    Flags;
 247
 248   /// SPI Count used by this frame
 249   UINT16    SPICount;
 250
 251   /// SPI Base used by this frame
 252   UINT16    SPIBase;
 253 } CM_ARM_GIC_MSI_FRAME_INFO;
 254
 255 /** A structure that describes the
 256     GIC Redistributor information for the Platform.
 257
 258     ID: EArmObjGicRedistributorInfo
 259 */
 260 typedef struct CmArmGicRedistInfo {
 261   /** The physical address of a page range
 262       containing all GIC Redistributors.
 263   */
 264   UINT64    DiscoveryRangeBaseAddress;
 265
 266   /// Length of the GIC Redistributor Discovery page range
 267   UINT32    DiscoveryRangeLength;
 268 } CM_ARM_GIC_REDIST_INFO;
 269
 270 /** A structure that describes the
 271     GIC Interrupt Translation Service information for the Platform.
 272
 273     ID: EArmObjGicItsInfo
 274 */
 275 typedef struct CmArmGicItsInfo {
 276   /// The GIC ITS ID
 277   UINT32    GicItsId;
 278
 279   /// The physical address for the Interrupt Translation Service
 280   UINT64    PhysicalBaseAddress;
 281
 282   /** The proximity domain to which the logical processor belongs.
 283       This field is used to populate the GIC ITS affinity structure
 284       in the SRAT table.
 285   */
 286   UINT32    ProximityDomain;
 287 } CM_ARM_GIC_ITS_INFO;
 288
 289 /** A structure that describes the
 290     Serial Port information for the Platform.
 291
 292     ID: EArmObjSerialConsolePortInfo or
 293         EArmObjSerialDebugPortInfo or
 294         EArmObjSerialPortInfo
 295 */
 296 typedef struct CmArmSerialPortInfo {
 297   /// The physical base address for the serial port
 298   UINT64    BaseAddress;
 299
 300   /// The serial port interrupt
 301   UINT32    Interrupt;
 302
 303   /// The serial port baud rate
 304   UINT64    BaudRate;
 305
 306   /// The serial port clock
 307   UINT32    Clock;
 308
 309   /// Serial Port subtype
 310   UINT16    PortSubtype;
 311
 312   /// The Base address length
 313   UINT64    BaseAddressLength;
 314
 315   /// The access size
 316   UINT8     AccessSize;
 317 } CM_ARM_SERIAL_PORT_INFO;
 318
 319 /** A structure that describes the
 320     Generic Timer information for the Platform.
 321
 322     ID: EArmObjGenericTimerInfo
 323 */
 324 typedef struct CmArmGenericTimerInfo {
 325   /// The physical base address for the counter control frame
 326   UINT64    CounterControlBaseAddress;
 327
 328   /// The physical base address for the counter read frame
 329   UINT64    CounterReadBaseAddress;
 330
 331   /// The secure PL1 timer interrupt
 332   UINT32    SecurePL1TimerGSIV;
 333
 334   /// The secure PL1 timer flags
 335   UINT32    SecurePL1TimerFlags;
 336
 337   /// The non-secure PL1 timer interrupt
 338   UINT32    NonSecurePL1TimerGSIV;
 339
 340   /// The non-secure PL1 timer flags
 341   UINT32    NonSecurePL1TimerFlags;
 342
 343   /// The virtual timer interrupt
 344   UINT32    VirtualTimerGSIV;
 345
 346   /// The virtual timer flags
 347   UINT32    VirtualTimerFlags;
 348
 349   /// The non-secure PL2 timer interrupt
 350   UINT32    NonSecurePL2TimerGSIV;
 351
 352   /// The non-secure PL2 timer flags
 353   UINT32    NonSecurePL2TimerFlags;
 354
 355   /// GSIV for the virtual EL2 timer
 356   UINT32    VirtualPL2TimerGSIV;
 357
 358   /// Flags for the virtual EL2 timer
 359   UINT32    VirtualPL2TimerFlags;
 360 } CM_ARM_GENERIC_TIMER_INFO;
 361
 362 /** A structure that describes the
 363     Platform Generic Block Timer information for the Platform.
 364
 365     ID: EArmObjPlatformGTBlockInfo
 366 */
 367 typedef struct CmArmGTBlockInfo {
 368   /// The physical base address for the GT Block Timer structure
 369   UINT64             GTBlockPhysicalAddress;
 370
 371   /// The number of timer frames implemented in the GT Block
 372   UINT32             GTBlockTimerFrameCount;
 373
 374   /// Reference token for the GT Block timer frame list
 375   CM_OBJECT_TOKEN    GTBlockTimerFrameToken;
 376 } CM_ARM_GTBLOCK_INFO;
 377
 378 /** A structure that describes the
 379     Platform Generic Block Timer Frame information for the Platform.
 380
 381     ID: EArmObjGTBlockTimerFrameInfo
 382 */
 383 typedef struct CmArmGTBlockTimerFrameInfo {
 384   /// The Generic Timer frame number
 385   UINT8     FrameNumber;
 386
 387   /// The physical base address for the CntBase block
 388   UINT64    PhysicalAddressCntBase;
 389
 390   /// The physical base address for the CntEL0Base block
 391   UINT64    PhysicalAddressCntEL0Base;
 392
 393   /// The physical timer interrupt
 394   UINT32    PhysicalTimerGSIV;
 395
 396   /** The physical timer flags as described by the GT Block
 397       Timer frame Structure in the ACPI Specification.
 398   */
 399   UINT32    PhysicalTimerFlags;
 400
 401   /// The virtual timer interrupt
 402   UINT32    VirtualTimerGSIV;
 403
 404   /** The virtual timer flags as described by the GT Block
 405       Timer frame Structure in the ACPI Specification.
 406   */
 407   UINT32    VirtualTimerFlags;
 408
 409   /** The common timer flags as described by the GT Block
 410       Timer frame Structure in the ACPI Specification.
 411   */
 412   UINT32    CommonFlags;
 413 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;
 414
 415 /** A structure that describes the
 416     Arm Generic Watchdog information for the Platform.
 417
 418     ID: EArmObjPlatformGenericWatchdogInfo
 419 */
 420 typedef struct CmArmGenericWatchdogInfo {
 421   /// The physical base address of the Arm Watchdog control frame
 422   UINT64    ControlFrameAddress;
 423
 424   /// The physical base address of the Arm Watchdog refresh frame
 425   UINT64    RefreshFrameAddress;
 426
 427   /// The watchdog interrupt
 428   UINT32    TimerGSIV;
 429
 430   /** The flags for the watchdog as described by the Arm watchdog
 431       structure in the ACPI specification.
 432   */
 433   UINT32    Flags;
 434 } CM_ARM_GENERIC_WATCHDOG_INFO;
 435
 436 /** A structure that describes the
 437     PCI Configuration Space information for the Platform.
 438
 439     ID: EArmObjPciConfigSpaceInfo
 440 */
 441 typedef struct CmArmPciConfigSpaceInfo {
 442   /// The physical base address for the PCI segment
 443   UINT64             BaseAddress;
 444
 445   /// The PCI segment group number
 446   UINT16             PciSegmentGroupNumber;
 447
 448   /// The start bus number
 449   UINT8              StartBusNumber;
 450
 451   /// The end bus number
 452   UINT8              EndBusNumber;
 453
 454   /// Optional field: Reference Token for address mapping.
 455   /// Token identifying a CM_ARM_OBJ_REF structure.
 456   CM_OBJECT_TOKEN    AddressMapToken;
 457
 458   /// Optional field: Reference Token for interrupt mapping.
 459   /// Token identifying a CM_ARM_OBJ_REF structure.
 460   CM_OBJECT_TOKEN    InterruptMapToken;
 461 } CM_ARM_PCI_CONFIG_SPACE_INFO;
 462
 463 /** A structure that describes the
 464     Hypervisor Vendor ID information for the Platform.
 465
 466     ID: EArmObjHypervisorVendorIdentity
 467 */
 468 typedef struct CmArmHypervisorVendorId {
 469   /// The hypervisor Vendor ID
 470   UINT64    HypervisorVendorId;
 471 } CM_ARM_HYPERVISOR_VENDOR_ID;
 472
 473 /** A structure that describes the
 474     Fixed feature flags for the Platform.
 475
 476     ID: EArmObjFixedFeatureFlags
 477 */
 478 typedef struct CmArmFixedFeatureFlags {
 479   /// The Fixed feature flags
 480   UINT32    Flags;
 481 } CM_ARM_FIXED_FEATURE_FLAGS;
 482
 483 /** A structure that describes the
 484     ITS Group node for the Platform.
 485
 486     ID: EArmObjItsGroup
 487 */
 488 typedef struct CmArmItsGroupNode {
 489   /// An unique token used to identify this object
 490   CM_OBJECT_TOKEN    Token;
 491   /// The number of ITS identifiers in the ITS node
 492   UINT32             ItsIdCount;
 493   /// Reference token for the ITS identifier array
 494   CM_OBJECT_TOKEN    ItsIdToken;
 495
 496   /// Unique identifier for this node.
 497   UINT32             Identifier;
 498 } CM_ARM_ITS_GROUP_NODE;
 499
 500 /** A structure that describes the
 501     Named component node for the Platform.
 502
 503     ID: EArmObjNamedComponent
 504 */
 505 typedef struct CmArmNamedComponentNode {
 506   /// An unique token used to identify this object
 507   CM_OBJECT_TOKEN    Token;
 508   /// Number of ID mappings
 509   UINT32             IdMappingCount;
 510   /// Reference token for the ID mapping array
 511   CM_OBJECT_TOKEN    IdMappingToken;
 512
 513   /// Flags for the named component
 514   UINT32             Flags;
 515
 516   /// Memory access properties : Cache coherent attributes
 517   UINT32             CacheCoherent;
 518   /// Memory access properties : Allocation hints
 519   UINT8              AllocationHints;
 520   /// Memory access properties : Memory access flags
 521   UINT8              MemoryAccessFlags;
 522
 523   /// Memory access properties : Address size limit
 524   UINT8              AddressSizeLimit;
 525
 526   /** ASCII Null terminated string with the full path to
 527       the entry in the namespace for this object.
 528   */
 529   CHAR8              *ObjectName;
 530
 531   /// Unique identifier for this node.
 532   UINT32             Identifier;
 533 } CM_ARM_NAMED_COMPONENT_NODE;
 534
 535 /** A structure that describes the
 536     Root complex node for the Platform.
 537
 538     ID: EArmObjRootComplex
 539 */
 540 typedef struct CmArmRootComplexNode {
 541   /// An unique token used to identify this object
 542   CM_OBJECT_TOKEN    Token;
 543   /// Number of ID mappings
 544   UINT32             IdMappingCount;
 545   /// Reference token for the ID mapping array
 546   CM_OBJECT_TOKEN    IdMappingToken;
 547
 548   /// Memory access properties : Cache coherent attributes
 549   UINT32             CacheCoherent;
 550   /// Memory access properties : Allocation hints
 551   UINT8              AllocationHints;
 552   /// Memory access properties : Memory access flags
 553   UINT8              MemoryAccessFlags;
 554
 555   /// ATS attributes
 556   UINT32             AtsAttribute;
 557   /// PCI segment number
 558   UINT32             PciSegmentNumber;
 559   /// Memory address size limit
 560   UINT8              MemoryAddressSize;
 561   /// PASID capabilities
 562   UINT16             PasidCapabilities;
 563   /// Flags
 564   UINT32             Flags;
 565
 566   /// Unique identifier for this node.
 567   UINT32             Identifier;
 568 } CM_ARM_ROOT_COMPLEX_NODE;
 569
 570 /** A structure that describes the
 571     SMMUv1 or SMMUv2 node for the Platform.
 572
 573     ID: EArmObjSmmuV1SmmuV2
 574 */
 575 typedef struct CmArmSmmuV1SmmuV2Node {
 576   /// An unique token used to identify this object
 577   CM_OBJECT_TOKEN    Token;
 578   /// Number of ID mappings
 579   UINT32             IdMappingCount;
 580   /// Reference token for the ID mapping array
 581   CM_OBJECT_TOKEN    IdMappingToken;
 582
 583   /// SMMU Base Address
 584   UINT64             BaseAddress;
 585   /// Length of the memory range covered by the SMMU
 586   UINT64             Span;
 587   /// SMMU Model
 588   UINT32             Model;
 589   /// SMMU flags
 590   UINT32             Flags;
 591
 592   /// Number of context interrupts
 593   UINT32             ContextInterruptCount;
 594   /// Reference token for the context interrupt array
 595   CM_OBJECT_TOKEN    ContextInterruptToken;
 596
 597   /// Number of PMU interrupts
 598   UINT32             PmuInterruptCount;
 599   /// Reference token for the PMU interrupt array
 600   CM_OBJECT_TOKEN    PmuInterruptToken;
 601
 602   /// GSIV of the SMMU_NSgIrpt interrupt
 603   UINT32             SMMU_NSgIrpt;
 604   /// SMMU_NSgIrpt interrupt flags
 605   UINT32             SMMU_NSgIrptFlags;
 606   /// GSIV of the SMMU_NSgCfgIrpt interrupt
 607   UINT32             SMMU_NSgCfgIrpt;
 608   /// SMMU_NSgCfgIrpt interrupt flags
 609   UINT32             SMMU_NSgCfgIrptFlags;
 610
 611   /// Unique identifier for this node.
 612   UINT32             Identifier;
 613 } CM_ARM_SMMUV1_SMMUV2_NODE;
 614
 615 /** A structure that describes the
 616     SMMUv3 node for the Platform.
 617
 618     ID: EArmObjSmmuV3
 619 */
 620 typedef struct CmArmSmmuV3Node {
 621   /// An unique token used to identify this object
 622   CM_OBJECT_TOKEN    Token;
 623   /// Number of ID mappings
 624   UINT32             IdMappingCount;
 625   /// Reference token for the ID mapping array
 626   CM_OBJECT_TOKEN    IdMappingToken;
 627
 628   /// SMMU Base Address
 629   UINT64             BaseAddress;
 630   /// SMMU flags
 631   UINT32             Flags;
 632   /// VATOS address
 633   UINT64             VatosAddress;
 634   /// Model
 635   UINT32             Model;
 636   /// GSIV of the Event interrupt if SPI based
 637   UINT32             EventInterrupt;
 638   /// PRI Interrupt if SPI based
 639   UINT32             PriInterrupt;
 640   /// GERR interrupt if GSIV based
 641   UINT32             GerrInterrupt;
 642   /// Sync interrupt if GSIV based
 643   UINT32             SyncInterrupt;
 644
 645   /// Proximity domain flag
 646   UINT32             ProximityDomain;
 647   /// Index into the array of ID mapping
 648   UINT32             DeviceIdMappingIndex;
 649
 650   /// Unique identifier for this node.
 651   UINT32             Identifier;
 652 } CM_ARM_SMMUV3_NODE;
 653
 654 /** A structure that describes the
 655     PMCG node for the Platform.
 656
 657     ID: EArmObjPmcg
 658 */
 659 typedef struct CmArmPmcgNode {
 660   /// An unique token used to identify this object
 661   CM_OBJECT_TOKEN    Token;
 662   /// Number of ID mappings
 663   UINT32             IdMappingCount;
 664   /// Reference token for the ID mapping array
 665   CM_OBJECT_TOKEN    IdMappingToken;
 666
 667   /// Base Address for performance monitor counter group
 668   UINT64             BaseAddress;
 669   /// GSIV for the Overflow interrupt
 670   UINT32             OverflowInterrupt;
 671   /// Page 1 Base address
 672   UINT64             Page1BaseAddress;
 673
 674   /// Reference token for the IORT node associated with this node
 675   CM_OBJECT_TOKEN    ReferenceToken;
 676
 677   /// Unique identifier for this node.
 678   UINT32             Identifier;
 679 } CM_ARM_PMCG_NODE;
 680
 681 /** A structure that describes the
 682     GIC ITS Identifiers for an ITS Group node.
 683
 684     ID: EArmObjGicItsIdentifierArray
 685 */
 686 typedef struct CmArmGicItsIdentifier {
 687   /// The ITS Identifier
 688   UINT32    ItsId;
 689 } CM_ARM_ITS_IDENTIFIER;
 690
 691 /** A structure that describes the
 692     ID Mappings for the Platform.
 693
 694     ID: EArmObjIdMappingArray
 695 */
 696 typedef struct CmArmIdMapping {
 697   /// Input base
 698   UINT32             InputBase;
 699   /// Number of input IDs
 700   UINT32             NumIds;
 701   /// Output Base
 702   UINT32             OutputBase;
 703   /// Reference token for the output node
 704   CM_OBJECT_TOKEN    OutputReferenceToken;
 705   /// Flags
 706   UINT32             Flags;
 707 } CM_ARM_ID_MAPPING;
 708
 709 /** A structure that describes the Arm
 710     Generic Interrupts.
 711 */
 712 typedef struct CmArmGenericInterrupt {
 713   /// Interrupt number
 714   UINT32    Interrupt;
 715
 716   /// Flags
 717   /// BIT0: 0: Interrupt is Level triggered
 718   ///       1: Interrupt is Edge triggered
 719   /// BIT1: 0: Interrupt is Active high
 720   ///       1: Interrupt is Active low
 721   UINT32    Flags;
 722 } CM_ARM_GENERIC_INTERRUPT;
 723
 724 /** A structure that describes the SMMU interrupts for the Platform.
 725
 726     Interrupt   Interrupt number.
 727     Flags       Interrupt flags as defined for SMMU node.
 728
 729     ID: EArmObjSmmuInterruptArray
 730 */
 731 typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_SMMU_INTERRUPT;
 732
 733 /** A structure that describes the AML Extended Interrupts.
 734
 735     Interrupt   Interrupt number.
 736     Flags       Interrupt flags as defined by the Interrupt
 737                 Vector Flags (Byte 3) of the Extended Interrupt
 738                 resource descriptor.
 739                 See EFI_ACPI_EXTENDED_INTERRUPT_FLAG_xxx in Acpi10.h
 740 */
 741 typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_EXTENDED_INTERRUPT;
 742
 743 /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT
 744
 745     ID: EArmObjProcHierarchyInfo
 746 */
 747 typedef struct CmArmProcHierarchyInfo {
 748   /// A unique token used to identify this object
 749   CM_OBJECT_TOKEN    Token;
 750   /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)
 751   UINT32             Flags;
 752   /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor
 753   /// topology. A value of CM_NULL_TOKEN means this node has no parent.
 754   CM_OBJECT_TOKEN    ParentToken;
 755   /// Token of the associated CM_ARM_GICC_INFO object which has the
 756   /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this
 757   /// node represents a group of associated processors and it does not have an
 758   /// associated GIC CPU interface.
 759   CM_OBJECT_TOKEN    GicCToken;
 760   /// Number of resources private to this Node
 761   UINT32             NoOfPrivateResources;
 762   /// Token of the array which contains references to the resources private to
 763   /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if
 764   /// the NoOfPrivateResources is 0, in which case it is recommended to set
 765   /// this field to CM_NULL_TOKEN.
 766   CM_OBJECT_TOKEN    PrivateResourcesArrayToken;
 767   /// Optional field: Reference Token for the Lpi state of this processor.
 768   /// Token identifying a CM_ARM_OBJ_REF structure, itself referencing
 769   /// CM_ARM_LPI_INFO objects.
 770   CM_OBJECT_TOKEN    LpiToken;
 771   /// Set to TRUE if UID should override index for name and _UID
 772   /// for processor container nodes and name of processors.
 773   /// This should be consistently set for containers or processors to avoid
 774   /// duplicate values
 775   BOOLEAN            OverrideNameUidEnabled;
 776   /// If OverrideNameUidEnabled is TRUE then this value will be used for name of
 777   /// processors and processor containers.
 778   UINT16             OverrideName;
 779   /// If OverrideNameUidEnabled is TRUE then this value will be used for
 780   /// the UID of processor containers.
 781   UINT32             OverrideUid;
 782 } CM_ARM_PROC_HIERARCHY_INFO;
 783
 784 /** A structure that describes the Cache Type Structure (Type 1) in PPTT
 785
 786     ID: EArmObjCacheInfo
 787 */
 788 typedef struct CmArmCacheInfo {
 789   /// A unique token used to identify this object
 790   CM_OBJECT_TOKEN    Token;
 791   /// Reference token for the next level of cache that is private to the same
 792   /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this
 793   /// entry represents the last cache level appropriate to the processor
 794   /// hierarchy node structures using this entry.
 795   CM_OBJECT_TOKEN    NextLevelOfCacheToken;
 796   /// Size of the cache in bytes
 797   UINT32             Size;
 798   /// Number of sets in the cache
 799   UINT32             NumberOfSets;
 800   /// Integer number of ways. The maximum associativity supported by
 801   /// ACPI Cache type structure is limited to MAX_UINT8. However,
 802   /// the maximum number of ways supported by the architecture is
 803   /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field
 804   /// is 32-bit wide.
 805   UINT32             Associativity;
 806   /// Cache attributes (ACPI 6.4 - January 2021, PPTT, Table 5.140)
 807   UINT8              Attributes;
 808   /// Line size in bytes
 809   UINT16             LineSize;
 810   /// Unique ID for the cache
 811   UINT32             CacheId;
 812 } CM_ARM_CACHE_INFO;
 813
 814 /** A structure that describes a reference to another Configuration Manager
 815     object.
 816
 817     This is useful for creating an array of reference tokens. The framework
 818     can then query the configuration manager for these arrays using the
 819     object ID EArmObjCmRef.
 820
 821     This can be used is to represent one-to-many relationships between objects.
 822
 823     ID: EArmObjCmRef
 824 */
 825 typedef struct CmArmObjRef {
 826   /// Token of the CM object being referenced
 827   CM_OBJECT_TOKEN    ReferenceToken;
 828 } CM_ARM_OBJ_REF;
 829
 830 /** A structure that describes the Memory Affinity Structure (Type 1) in SRAT
 831
 832     ID: EArmObjMemoryAffinityInfo
 833 */
 834 typedef struct CmArmMemoryAffinityInfo {
 835   /// The proximity domain to which the "range of memory" belongs.
 836   UINT32    ProximityDomain;
 837
 838   /// Base Address
 839   UINT64    BaseAddress;
 840
 841   /// Length
 842   UINT64    Length;
 843
 844   /// Flags
 845   UINT32    Flags;
 846 } CM_ARM_MEMORY_AFFINITY_INFO;
 847
 848 /** A structure that describes the ACPI Device Handle (Type 0) in the
 849     Generic Initiator Affinity structure in SRAT
 850
 851     ID: EArmObjDeviceHandleAcpi
 852 */
 853 typedef struct CmArmDeviceHandleAcpi {
 854   /// Hardware ID
 855   UINT64    Hid;
 856
 857   /// Unique Id
 858   UINT32    Uid;
 859 } CM_ARM_DEVICE_HANDLE_ACPI;
 860
 861 /** A structure that describes the PCI Device Handle (Type 1) in the
 862     Generic Initiator Affinity structure in SRAT
 863
 864     ID: EArmObjDeviceHandlePci
 865 */
 866 typedef struct CmArmDeviceHandlePci {
 867   /// PCI Segment Number
 868   UINT16    SegmentNumber;
 869
 870   /// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)
 871   UINT8     BusNumber;
 872
 873   /// PCI Device Number - Max 32 devices (Bits 7:3 of BDF)
 874   UINT8     DeviceNumber;
 875
 876   /// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)
 877   UINT8     FunctionNumber;
 878 } CM_ARM_DEVICE_HANDLE_PCI;
 879
 880 /** A structure that describes the Generic Initiator Affinity structure in SRAT
 881
 882     ID: EArmObjGenericInitiatorAffinityInfo
 883 */
 884 typedef struct CmArmGenericInitiatorAffinityInfo {
 885   /// The proximity domain to which the generic initiator belongs.
 886   UINT32             ProximityDomain;
 887
 888   /// Flags
 889   UINT32             Flags;
 890
 891   /// Device Handle Type
 892   UINT8              DeviceHandleType;
 893
 894   /// Reference Token for the Device Handle
 895   CM_OBJECT_TOKEN    DeviceHandleToken;
 896 } CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO;
 897
 898 /** A structure that describes the CMN-600 hardware.
 899
 900     ID: EArmObjCmn600Info
 901 */
 902 typedef struct CmArmCmn600Info {
 903   /// The PERIPHBASE address.
 904   /// Corresponds to the Configuration Node Region (CFGR) base address.
 905   UINT64    PeriphBaseAddress;
 906
 907   /// The PERIPHBASE address length.
 908   /// Corresponds to the CFGR base address length.
 909   UINT64    PeriphBaseAddressLength;
 910
 911   /// The ROOTNODEBASE address.
 912   /// Corresponds to the Root node (ROOT) base address.
 913   UINT64    RootNodeBaseAddress;
 914
 915   /// The Debug and Trace Logic Controller (DTC) count.
 916   /// CMN-600 can have maximum 4 DTCs.
 917   UINT8     DtcCount;
 918
 919   /// DTC Interrupt list.
 920   /// The first interrupt resource descriptor pertains to
 921   /// DTC[0], the second to DTC[1] and so on.
 922   /// DtcCount determines the number of DTC Interrupts that
 923   /// are populated. If DTC count is 2 then DtcInterrupt[2]
 924   /// and DtcInterrupt[3] are ignored.
 925   /// Note: The size of CM_ARM_CMN_600_INFO structure remains
 926   /// constant and does not vary with the DTC count.
 927   CM_ARM_EXTENDED_INTERRUPT    DtcInterrupt[4];
 928 } CM_ARM_CMN_600_INFO;
 929
 930 /** A structure that describes the Lpi information.
 931
 932   The Low Power Idle states are described in DSDT/SSDT and associated
 933   to cpus/clusters in the cpu topology.
 934
 935   ID: EArmObjLpiInfo
 936 */
 937 typedef struct CmArmLpiInfo {
 938   /** Minimum Residency. Time in microseconds after which a
 939       state becomes more energy efficient than any shallower state.
 940   */
 941   UINT32                                    MinResidency;
 942
 943   /** Worst case time in microseconds from a wake interrupt
 944       being asserted to the return to a running state
 945   */
 946   UINT32                                    WorstCaseWakeLatency;
 947
 948   /** Flags.
 949   */
 950   UINT32                                    Flags;
 951
 952   /** Architecture specific context loss flags.
 953   */
 954   UINT32                                    ArchFlags;
 955
 956   /** Residency counter frequency in cycles-per-second (Hz).
 957   */
 958   UINT32                                    ResCntFreq;
 959
 960   /** Every shallower power state in the parent is also enabled.
 961   */
 962   UINT32                                    EnableParentState;
 963
 964   /** The EntryMethod _LPI field can be described as an integer
 965       or in a Register resource data descriptor.
 966
 967   If IsInteger is TRUE, the IntegerEntryMethod field is used.
 968   If IsInteger is FALSE, the RegisterEntryMethod field is used.
 969   */
 970   BOOLEAN                                   IsInteger;
 971
 972   /** EntryMethod described as an Integer.
 973   */
 974   UINT64                                    IntegerEntryMethod;
 975
 976   /** EntryMethod described as a EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR.
 977   */
 978   EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE    RegisterEntryMethod;
 979
 980   /** Residency counter register.
 981   */
 982   EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE    ResidencyCounterRegister;
 983
 984   /** Usage counter register.
 985   */
 986   EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE    UsageCounterRegister;
 987
 988   /** String representing the Lpi state
 989   */
 990   CHAR8                                     StateName[16];
 991 } CM_ARM_LPI_INFO;
 992
 993 /** A structure that describes a PCI Address Map.
 994
 995   The memory-ranges used by the PCI bus are described by this object.
 996
 997   ID: EArmObjPciAddressMapInfo
 998 */
 999 typedef struct CmArmPciAddressMapInfo {
1000   /** Pci address space code
1001
1002   Available values are:
1003    - 0: Configuration Space
1004    - 1: I/O Space
1005    - 2: 32-bit-address Memory Space
1006    - 3: 64-bit-address Memory Space
1007   */
1008   UINT8     SpaceCode;
1009
1010   /// PCI address
1011   UINT64    PciAddress;
1012
1013   /// Cpu address
1014   UINT64    CpuAddress;
1015
1016   /// Address size
1017   UINT64    AddressSize;
1018 } CM_ARM_PCI_ADDRESS_MAP_INFO;
1019
1020 /** A structure that describes a PCI Interrupt Map.
1021
1022   The legacy PCI interrupts used by PCI devices are described by this object.
1023
1024   Cf Devicetree Specification - Release v0.3
1025   s2.4.3 "Interrupt Nexus Properties"
1026
1027   ID: EArmObjPciInterruptMapInfo
1028 */
1029 typedef struct CmArmPciInterruptMapInfo {
1030   /// Pci Bus.
1031   /// Value on 8 bits (max 255).
1032   UINT8    PciBus;
1033
1034   /// Pci Device.
1035   /// Value on 5 bits (max 31).
1036   UINT8    PciDevice;
1037
1038   /** PCI interrupt
1039
1040   ACPI bindings are used:
1041   Cf. ACPI 6.4, s6.2.13 _PRT (PCI Routing Table):
1042       "0-INTA, 1-INTB, 2-INTC, 3-INTD"
1043
1044   Device-tree bindings are shifted by 1:
1045       "INTA=1, INTB=2, INTC=3, INTD=4"
1046   */
1047   UINT8                       PciInterrupt;
1048
1049   /** Interrupt controller interrupt.
1050
1051   Cf Devicetree Specification - Release v0.3
1052   s2.4.3 "Interrupt Nexus Properties": "parent interrupt specifier"
1053   */
1054   CM_ARM_GENERIC_INTERRUPT    IntcInterrupt;
1055 } CM_ARM_PCI_INTERRUPT_MAP_INFO;
1056
1057 /** A structure that describes the
1058     RMR node for the Platform.
1059
1060     ID: EArmObjRmr
1061 */
1062 typedef struct CmArmRmrNode {
1063   /// An unique token used to identify this object
1064   CM_OBJECT_TOKEN    Token;
1065   /// Number of ID mappings
1066   UINT32             IdMappingCount;
1067   /// Reference token for the ID mapping array
1068   CM_OBJECT_TOKEN    IdMappingToken;
1069
1070   /// Unique identifier for this node.
1071   UINT32             Identifier;
1072
1073   /// Reserved Memory Range flags.
1074   UINT32             Flags;
1075
1076   /// Memory range descriptor count.
1077   UINT32             MemRangeDescCount;
1078   /// Reference token for the Memory Range descriptor array
1079   CM_OBJECT_TOKEN    MemRangeDescToken;
1080 } CM_ARM_RMR_NODE;
1081
1082 /** A structure that describes the
1083     Memory Range descriptor.
1084
1085     ID: EArmObjMemoryRangeDescriptor
1086 */
1087 typedef struct CmArmRmrDescriptor {
1088   /// Base address of Reserved Memory Range,
1089   /// aligned to a page size of 64K.
1090   UINT64    BaseAddress;
1091
1092   /// Length of the Reserved Memory range.
1093   /// Must be a multiple of the page size of 64K.
1094   UINT64    Length;
1095 } CM_ARM_MEMORY_RANGE_DESCRIPTOR;
1096
1097 /** A structure that describes the Cpc information.
1098
1099   Continuous Performance Control is described in DSDT/SSDT and associated
1100   to cpus/clusters in the cpu topology.
1101
1102   Unsupported Optional registers should be encoded with NULL resource
1103   Register {(SystemMemory, 0, 0, 0, 0)}
1104
1105   For values that support Integer or Buffer, integer will be used
1106   if buffer is NULL resource.
1107   If resource is not NULL then Integer must be 0
1108
1109   Cf. ACPI 6.4, s8.4.7.1 _CPC (Continuous Performance Control)
1110
1111   ID: EArmObjCpcInfo
1112 */
1113 typedef AML_CPC_INFO CM_ARM_CPC_INFO;
1114
1115 /** A structure that describes a
1116     PCC Mailbox Register.
1117 */
1118 typedef struct PccMailboxRegisterInfo {
1119   /// GAS describing the Register.
1120   EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE    Register;
1121
1122   /** Mask of bits to preserve when writing.
1123
1124     This mask is also used for registers. The Register is only read
1125     and there is no write mask required. E.g.:
1126     - Error Status mask (Cf. PCC Subspace types 3/4/5).
1127     - Command Complete Check mask (Cf. PCC Subspace types 3/4/5).
1128   */
1129   UINT64    PreserveMask;
1130
1131   /// Mask of bits to set when writing.
1132   UINT64    WriteMask;
1133 } PCC_MAILBOX_REGISTER_INFO;
1134
1135 /** A structure that describes the
1136     PCC Subspace CHannel Timings.
1137 */
1138 typedef struct PccSubspaceChannelTimingInfo {
1139   /// Expected latency to process a command, in microseconds.
1140   UINT32    NominalLatency;
1141
1142   /** Maximum number of periodic requests that the subspace channel can
1143       support, reported in commands per minute. 0 indicates no limitation.
1144
1145     This field is ignored for the PCC Subspace type 5 (HW Registers based).
1146   */
1147   UINT32    MaxPeriodicAccessRate;
1148
1149   /** Minimum amount of time that OSPM must wait after the completion
1150       of a command before issuing the next command, in microseconds.
1151   */
1152   UINT16    MinRequestTurnaroundTime;
1153 } PCC_SUBSPACE_CHANNEL_TIMING_INFO;
1154
1155 /** A structure that describes a
1156     Generic PCC Subspace (Type 0).
1157 */
1158 typedef struct CmArmPccSubspaceGenericInfo {
1159   /** Subspace Id.
1160
1161   Cf. ACPI 6.4, s14.7 Referencing the PCC address space
1162   Cf. s14.1.2 Platform Communications Channel Subspace Structures
1163       The subspace ID of a PCC subspace is its index in the array of
1164       subspace structures, starting with subspace 0.
1165
1166   At most 256 subspaces are supported.
1167   */
1168   UINT8                               SubspaceId;
1169
1170   /// Table type (or subspace).
1171   UINT8                               Type;
1172
1173   /// Base address of the shared memory range.
1174   /// This field is ignored for the PCC Subspace type 5 (HW Registers based).
1175   UINT64                              BaseAddress;
1176
1177   /// Address length.
1178   UINT64                              AddressLength;
1179
1180   /// Doorbell Register.
1181   PCC_MAILBOX_REGISTER_INFO           DoorbellReg;
1182
1183   /// Mailbox Timings.
1184   PCC_SUBSPACE_CHANNEL_TIMING_INFO    ChannelTiming;
1185 } PCC_SUBSPACE_GENERIC_INFO;
1186
1187 /** A structure that describes a
1188     PCC Subspace of type 0 (Generic).
1189
1190     ID: EArmObjPccSubspaceType0Info
1191 */
1192 typedef PCC_SUBSPACE_GENERIC_INFO CM_ARM_PCC_SUBSPACE_TYPE0_INFO;
1193
1194 /** A structure that describes a
1195     PCC Subspace of type 1 (HW-Reduced).
1196
1197     ID: EArmObjPccSubspaceType1Info
1198 */
1199 typedef struct CmArmPccSubspaceType1Info {
1200   /** Generic Pcc information.
1201
1202     The Subspace of Type0 contains information that can be re-used
1203     in other Subspace types.
1204   */
1205   PCC_SUBSPACE_GENERIC_INFO    GenericPccInfo;
1206
1207   /// Platform Interrupt.
1208   CM_ARM_GENERIC_INTERRUPT     PlatIrq;
1209 } CM_ARM_PCC_SUBSPACE_TYPE1_INFO;
1210
1211 /** A structure that describes a
1212     PCC Subspace of type 2 (HW-Reduced).
1213
1214     ID: EArmObjPccSubspaceType2Info
1215 */
1216 typedef struct CmArmPccSubspaceType2Info {
1217   /** Generic Pcc information.
1218
1219     The Subspace of Type0 contains information that can be re-used
1220     in other Subspace types.
1221   */
1222   PCC_SUBSPACE_GENERIC_INFO    GenericPccInfo;
1223
1224   /// Platform Interrupt.
1225   CM_ARM_GENERIC_INTERRUPT     PlatIrq;
1226
1227   /// Platform Interrupt Register.
1228   PCC_MAILBOX_REGISTER_INFO    PlatIrqAckReg;
1229 } CM_ARM_PCC_SUBSPACE_TYPE2_INFO;
1230
1231 /** A structure that describes a
1232     PCC Subspace of type 3 (Extended)
1233
1234     ID: EArmObjPccSubspaceType3Info
1235 */
1236 typedef struct CmArmPccSubspaceType3Info {
1237   /** Generic Pcc information.
1238
1239     The Subspace of Type0 contains information that can be re-used
1240     in other Subspace types.
1241   */
1242   PCC_SUBSPACE_GENERIC_INFO    GenericPccInfo;
1243
1244   /// Platform Interrupt.
1245   CM_ARM_GENERIC_INTERRUPT     PlatIrq;
1246
1247   /// Platform Interrupt Register.
1248   PCC_MAILBOX_REGISTER_INFO    PlatIrqAckReg;
1249
1250   /// Command Complete Check Register.
1251   /// The WriteMask field is not used.
1252   PCC_MAILBOX_REGISTER_INFO    CmdCompleteCheckReg;
1253
1254   /// Command Complete Update Register.
1255   PCC_MAILBOX_REGISTER_INFO    CmdCompleteUpdateReg;
1256
1257   /// Error Status Register.
1258   /// The WriteMask field is not used.
1259   PCC_MAILBOX_REGISTER_INFO    ErrorStatusReg;
1260 } CM_ARM_PCC_SUBSPACE_TYPE3_INFO;
1261
1262 /** A structure that describes a
1263     PCC Subspace of type 4 (Extended)
1264
1265     ID: EArmObjPccSubspaceType4Info
1266 */
1267 typedef CM_ARM_PCC_SUBSPACE_TYPE3_INFO CM_ARM_PCC_SUBSPACE_TYPE4_INFO;
1268
1269 /** A structure that describes a
1270     PCC Subspace of type 5 (HW-Registers).
1271
1272     ID: EArmObjPccSubspaceType5Info
1273 */
1274 typedef struct CmArmPccSubspaceType5Info {
1275   /** Generic Pcc information.
1276
1277     The Subspace of Type0 contains information that can be re-used
1278     in other Subspace types.
1279
1280     MaximumPeriodicAccessRate doesn't need to be populated for
1281     this structure.
1282   */
1283   PCC_SUBSPACE_GENERIC_INFO    GenericPccInfo;
1284
1285   /// Version.
1286   UINT16                       Version;
1287
1288   /// Platform Interrupt.
1289   CM_ARM_GENERIC_INTERRUPT     PlatIrq;
1290
1291   /// Command Complete Check Register.
1292   /// The WriteMask field is not used.
1293   PCC_MAILBOX_REGISTER_INFO    CmdCompleteCheckReg;
1294
1295   /// Error Status Register.
1296   /// The WriteMask field is not used.
1297   PCC_MAILBOX_REGISTER_INFO    ErrorStatusReg;
1298 } CM_ARM_PCC_SUBSPACE_TYPE5_INFO;
1299
1300 #pragma pack()
1301
1302 #endif // ARM_NAMESPACE_OBJECTS_H_