DynamicTablesPkg/Include/ArmNameSpaceObjects.h

   1 /** @file
   2
   3   Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.<BR>
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7   @par Glossary:
   8     - Cm or CM   - Configuration Manager
   9     - Obj or OBJ - Object
  10     - Std or STD - Standard
  11 **/
  12
  13 #ifndef ARM_NAMESPACE_OBJECTS_H_
  14 #define ARM_NAMESPACE_OBJECTS_H_
  15
  16 #include <StandardNameSpaceObjects.h>
  17
  18 #pragma pack(1)
  19
  20 /** The EARM_OBJECT_ID enum describes the Object IDs
  21     in the ARM Namespace
  22 */
  23 typedef enum ArmObjectID {
  24   EArmObjReserved,                     ///<  0 - Reserved
  25   EArmObjBootArchInfo,                 ///<  1 - Boot Architecture Info
  26   EArmObjCpuInfo,                      ///<  2 - CPU Info
  27   EArmObjPowerManagementProfileInfo,   ///<  3 - Power Management Profile Info
  28   EArmObjGicCInfo,                     ///<  4 - GIC CPU Interface Info
  29   EArmObjGicDInfo,                     ///<  5 - GIC Distributor Info
  30   EArmObjGicMsiFrameInfo,              ///<  6 - GIC MSI Frame Info
  31   EArmObjGicRedistributorInfo,         ///<  7 - GIC Redistributor Info
  32   EArmObjGicItsInfo,                   ///<  8 - GIC ITS Info
  33   EArmObjSerialConsolePortInfo,        ///<  9 - Serial Console Port Info
  34   EArmObjSerialDebugPortInfo,          ///< 10 - Serial Debug Port Info
  35   EArmObjGenericTimerInfo,             ///< 11 - Generic Timer Info
  36   EArmObjPlatformGTBlockInfo,          ///< 12 - Platform GT Block Info
  37   EArmObjGTBlockTimerFrameInfo,        ///< 13 - Generic Timer Block Frame Info
  38   EArmObjPlatformGenericWatchdogInfo,  ///< 14 - Platform Generic Watchdog
  39   EArmObjPciConfigSpaceInfo,           ///< 15 - PCI Configuration Space Info
  40   EArmObjHypervisorVendorIdentity,     ///< 16 - Hypervisor Vendor Id
  41   EArmObjFixedFeatureFlags,            ///< 17 - Fixed feature flags for FADT
  42   EArmObjItsGroup,                     ///< 18 - ITS Group
  43   EArmObjNamedComponent,               ///< 19 - Named Component
  44   EArmObjRootComplex,                  ///< 20 - Root Complex
  45   EArmObjSmmuV1SmmuV2,                 ///< 21 - SMMUv1 or SMMUv2
  46   EArmObjSmmuV3,                       ///< 22 - SMMUv3
  47   EArmObjPmcg,                         ///< 23 - PMCG
  48   EArmObjGicItsIdentifierArray,        ///< 24 - GIC ITS Identifier Array
  49   EArmObjIdMappingArray,               ///< 25 - ID Mapping Array
  50   EArmObjSmmuInterruptArray,           ///< 26 - SMMU Interrupt Array
  51   EArmObjProcHierarchyInfo,            ///< 27 - Processor Hierarchy Info
  52   EArmObjCacheInfo,                    ///< 28 - Cache Info
  53   EArmObjReserved29,                   ///< 29 - Reserved
  54   EArmObjCmRef,                        ///< 30 - CM Object Reference
  55   EArmObjMemoryAffinityInfo,           ///< 31 - Memory Affinity Info
  56   EArmObjDeviceHandleAcpi,             ///< 32 - Device Handle Acpi
  57   EArmObjDeviceHandlePci,              ///< 33 - Device Handle Pci
  58   EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity
  59   EArmObjSerialPortInfo,               ///< 35 - Generic Serial Port Info
  60   EArmObjCmn600Info,                   ///< 36 - CMN-600 Info
  61   EArmObjLpiInfo,                      ///< 37 - Lpi Info
  62   EArmObjPciAddressMapInfo,            ///< 38 - Pci Address Map Info
  63   EArmObjPciInterruptMapInfo,          ///< 39 - Pci Interrupt Map Info
  64   EArmObjMax
  65 } EARM_OBJECT_ID;
  66
  67 /** A structure that describes the
  68     ARM Boot Architecture flags.
  69
  70     ID: EArmObjBootArchInfo
  71 */
  72 typedef struct CmArmBootArchInfo {
  73   /** This is the ARM_BOOT_ARCH flags field of the FADT Table
  74       described in the ACPI Table Specification.
  75   */
  76   UINT16    BootArchFlags;
  77 } CM_ARM_BOOT_ARCH_INFO;
  78
  79 /** A structure that describes the
  80     Power Management Profile Information for the Platform.
  81
  82     ID: EArmObjPowerManagementProfileInfo
  83 */
  84 typedef struct CmArmPowerManagementProfileInfo {
  85   /** This is the Preferred_PM_Profile field of the FADT Table
  86       described in the ACPI Specification
  87   */
  88   UINT8    PowerManagementProfile;
  89 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;
  90
  91 /** A structure that describes the
  92     GIC CPU Interface for the Platform.
  93
  94     ID: EArmObjGicCInfo
  95 */
  96 typedef struct CmArmGicCInfo {
  97   /// The GIC CPU Interface number.
  98   UINT32    CPUInterfaceNumber;
  99
 100   /** The ACPI Processor UID. This must match the
 101       _UID of the CPU Device object information described
 102       in the DSDT/SSDT for the CPU.
 103   */
 104   UINT32    AcpiProcessorUid;
 105
 106   /** The flags field as described by the GICC structure
 107       in the ACPI Specification.
 108   */
 109   UINT32    Flags;
 110
 111   /** The parking protocol version field as described by
 112     the GICC structure in the ACPI Specification.
 113   */
 114   UINT32    ParkingProtocolVersion;
 115
 116   /** The Performance Interrupt field as described by
 117       the GICC structure in the ACPI Specification.
 118   */
 119   UINT32    PerformanceInterruptGsiv;
 120
 121   /** The CPU Parked address field as described by
 122       the GICC structure in the ACPI Specification.
 123   */
 124   UINT64    ParkedAddress;
 125
 126   /** The base address for the GIC CPU Interface
 127       as described by the GICC structure in the
 128       ACPI Specification.
 129   */
 130   UINT64    PhysicalBaseAddress;
 131
 132   /** The base address for GICV interface
 133       as described by the GICC structure in the
 134       ACPI Specification.
 135   */
 136   UINT64    GICV;
 137
 138   /** The base address for GICH interface
 139       as described by the GICC structure in the
 140       ACPI Specification.
 141   */
 142   UINT64    GICH;
 143
 144   /** The GICV maintenance interrupt
 145       as described by the GICC structure in the
 146       ACPI Specification.
 147   */
 148   UINT32    VGICMaintenanceInterrupt;
 149
 150   /** The base address for GICR interface
 151       as described by the GICC structure in the
 152       ACPI Specification.
 153   */
 154   UINT64    GICRBaseAddress;
 155
 156   /** The MPIDR for the CPU
 157       as described by the GICC structure in the
 158       ACPI Specification.
 159   */
 160   UINT64    MPIDR;
 161
 162   /** The Processor Power Efficiency class
 163       as described by the GICC structure in the
 164       ACPI Specification.
 165   */
 166   UINT8     ProcessorPowerEfficiencyClass;
 167
 168   /** Statistical Profiling Extension buffer overflow GSIV. Zero if
 169       unsupported by this processor. This field was introduced in
 170       ACPI 6.3 (MADT revision 5) and is therefore ignored when
 171       generating MADT revision 4 or lower.
 172   */
 173   UINT16    SpeOverflowInterrupt;
 174
 175   /** The proximity domain to which the logical processor belongs.
 176       This field is used to populate the GICC affinity structure
 177       in the SRAT table.
 178   */
 179   UINT32    ProximityDomain;
 180
 181   /** The clock domain to which the logical processor belongs.
 182       This field is used to populate the GICC affinity structure
 183       in the SRAT table.
 184   */
 185   UINT32    ClockDomain;
 186
 187   /** The GICC Affinity flags field as described by the GICC Affinity structure
 188       in the SRAT table.
 189   */
 190   UINT32    AffinityFlags;
 191 } CM_ARM_GICC_INFO;
 192
 193 /** A structure that describes the
 194     GIC Distributor information for the Platform.
 195
 196     ID: EArmObjGicDInfo
 197 */
 198 typedef struct CmArmGicDInfo {
 199   /// The Physical Base address for the GIC Distributor.
 200   UINT64    PhysicalBaseAddress;
 201
 202   /** The global system interrupt
 203       number where this GIC Distributor's
 204       interrupt inputs start.
 205   */
 206   UINT32    SystemVectorBase;
 207
 208   /** The GIC version as described
 209       by the GICD structure in the
 210       ACPI Specification.
 211   */
 212   UINT8     GicVersion;
 213 } CM_ARM_GICD_INFO;
 214
 215 /** A structure that describes the
 216     GIC MSI Frame information for the Platform.
 217
 218     ID: EArmObjGicMsiFrameInfo
 219 */
 220 typedef struct CmArmGicMsiFrameInfo {
 221   /// The GIC MSI Frame ID
 222   UINT32    GicMsiFrameId;
 223
 224   /// The Physical base address for the MSI Frame
 225   UINT64    PhysicalBaseAddress;
 226
 227   /** The GIC MSI Frame flags
 228       as described by the GIC MSI frame
 229       structure in the ACPI Specification.
 230   */
 231   UINT32    Flags;
 232
 233   /// SPI Count used by this frame
 234   UINT16    SPICount;
 235
 236   /// SPI Base used by this frame
 237   UINT16    SPIBase;
 238 } CM_ARM_GIC_MSI_FRAME_INFO;
 239
 240 /** A structure that describes the
 241     GIC Redistributor information for the Platform.
 242
 243     ID: EArmObjGicRedistributorInfo
 244 */
 245 typedef struct CmArmGicRedistInfo {
 246   /** The physical address of a page range
 247       containing all GIC Redistributors.
 248   */
 249   UINT64    DiscoveryRangeBaseAddress;
 250
 251   /// Length of the GIC Redistributor Discovery page range
 252   UINT32    DiscoveryRangeLength;
 253 } CM_ARM_GIC_REDIST_INFO;
 254
 255 /** A structure that describes the
 256     GIC Interrupt Translation Service information for the Platform.
 257
 258     ID: EArmObjGicItsInfo
 259 */
 260 typedef struct CmArmGicItsInfo {
 261   /// The GIC ITS ID
 262   UINT32    GicItsId;
 263
 264   /// The physical address for the Interrupt Translation Service
 265   UINT64    PhysicalBaseAddress;
 266
 267   /** The proximity domain to which the logical processor belongs.
 268       This field is used to populate the GIC ITS affinity structure
 269       in the SRAT table.
 270   */
 271   UINT32    ProximityDomain;
 272 } CM_ARM_GIC_ITS_INFO;
 273
 274 /** A structure that describes the
 275     Serial Port information for the Platform.
 276
 277     ID: EArmObjSerialConsolePortInfo or
 278         EArmObjSerialDebugPortInfo or
 279         EArmObjSerialPortInfo
 280 */
 281 typedef struct CmArmSerialPortInfo {
 282   /// The physical base address for the serial port
 283   UINT64    BaseAddress;
 284
 285   /// The serial port interrupt
 286   UINT32    Interrupt;
 287
 288   /// The serial port baud rate
 289   UINT64    BaudRate;
 290
 291   /// The serial port clock
 292   UINT32    Clock;
 293
 294   /// Serial Port subtype
 295   UINT16    PortSubtype;
 296
 297   /// The Base address length
 298   UINT64    BaseAddressLength;
 299
 300   /// The access size
 301   UINT8     AccessSize;
 302 } CM_ARM_SERIAL_PORT_INFO;
 303
 304 /** A structure that describes the
 305     Generic Timer information for the Platform.
 306
 307     ID: EArmObjGenericTimerInfo
 308 */
 309 typedef struct CmArmGenericTimerInfo {
 310   /// The physical base address for the counter control frame
 311   UINT64    CounterControlBaseAddress;
 312
 313   /// The physical base address for the counter read frame
 314   UINT64    CounterReadBaseAddress;
 315
 316   /// The secure PL1 timer interrupt
 317   UINT32    SecurePL1TimerGSIV;
 318
 319   /// The secure PL1 timer flags
 320   UINT32    SecurePL1TimerFlags;
 321
 322   /// The non-secure PL1 timer interrupt
 323   UINT32    NonSecurePL1TimerGSIV;
 324
 325   /// The non-secure PL1 timer flags
 326   UINT32    NonSecurePL1TimerFlags;
 327
 328   /// The virtual timer interrupt
 329   UINT32    VirtualTimerGSIV;
 330
 331   /// The virtual timer flags
 332   UINT32    VirtualTimerFlags;
 333
 334   /// The non-secure PL2 timer interrupt
 335   UINT32    NonSecurePL2TimerGSIV;
 336
 337   /// The non-secure PL2 timer flags
 338   UINT32    NonSecurePL2TimerFlags;
 339
 340   /// GSIV for the virtual EL2 timer
 341   UINT32    VirtualPL2TimerGSIV;
 342
 343   /// Flags for the virtual EL2 timer
 344   UINT32    VirtualPL2TimerFlags;
 345 } CM_ARM_GENERIC_TIMER_INFO;
 346
 347 /** A structure that describes the
 348     Platform Generic Block Timer Frame information for the Platform.
 349
 350     ID: EArmObjGTBlockTimerFrameInfo
 351 */
 352 typedef struct CmArmGTBlockTimerFrameInfo {
 353   /// The Generic Timer frame number
 354   UINT8     FrameNumber;
 355
 356   /// The physical base address for the CntBase block
 357   UINT64    PhysicalAddressCntBase;
 358
 359   /// The physical base address for the CntEL0Base block
 360   UINT64    PhysicalAddressCntEL0Base;
 361
 362   /// The physical timer interrupt
 363   UINT32    PhysicalTimerGSIV;
 364
 365   /** The physical timer flags as described by the GT Block
 366       Timer frame Structure in the ACPI Specification.
 367   */
 368   UINT32    PhysicalTimerFlags;
 369
 370   /// The virtual timer interrupt
 371   UINT32    VirtualTimerGSIV;
 372
 373   /** The virtual timer flags as described by the GT Block
 374       Timer frame Structure in the ACPI Specification.
 375   */
 376   UINT32    VirtualTimerFlags;
 377
 378   /** The common timer flags as described by the GT Block
 379       Timer frame Structure in the ACPI Specification.
 380   */
 381   UINT32    CommonFlags;
 382 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;
 383
 384 /** A structure that describes the
 385     Platform Generic Block Timer information for the Platform.
 386
 387     ID: EArmObjPlatformGTBlockInfo
 388 */
 389 typedef struct CmArmGTBlockInfo {
 390   /// The physical base address for the GT Block Timer structure
 391   UINT64             GTBlockPhysicalAddress;
 392
 393   /// The number of timer frames implemented in the GT Block
 394   UINT32             GTBlockTimerFrameCount;
 395
 396   /// Reference token for the GT Block timer frame list
 397   CM_OBJECT_TOKEN    GTBlockTimerFrameToken;
 398 } CM_ARM_GTBLOCK_INFO;
 399
 400 /** A structure that describes the
 401     Arm Generic Watchdog information for the Platform.
 402
 403     ID: EArmObjPlatformGenericWatchdogInfo
 404 */
 405 typedef struct CmArmGenericWatchdogInfo {
 406   /// The physical base address of the Arm Watchdog control frame
 407   UINT64    ControlFrameAddress;
 408
 409   /// The physical base address of the Arm Watchdog refresh frame
 410   UINT64    RefreshFrameAddress;
 411
 412   /// The watchdog interrupt
 413   UINT32    TimerGSIV;
 414
 415   /** The flags for the watchdog as described by the Arm watchdog
 416       structure in the ACPI specification.
 417   */
 418   UINT32    Flags;
 419 } CM_ARM_GENERIC_WATCHDOG_INFO;
 420
 421 /** A structure that describes the
 422     PCI Configuration Space information for the Platform.
 423
 424     ID: EArmObjPciConfigSpaceInfo
 425 */
 426 typedef struct CmArmPciConfigSpaceInfo {
 427   /// The physical base address for the PCI segment
 428   UINT64             BaseAddress;
 429
 430   /// The PCI segment group number
 431   UINT16             PciSegmentGroupNumber;
 432
 433   /// The start bus number
 434   UINT8              StartBusNumber;
 435
 436   /// The end bus number
 437   UINT8              EndBusNumber;
 438
 439   /// Optional field: Reference Token for address mapping.
 440   /// Token identifying a CM_ARM_OBJ_REF structure.
 441   CM_OBJECT_TOKEN    AddressMapToken;
 442
 443   /// Optional field: Reference Token for interrupt mapping.
 444   /// Token identifying a CM_ARM_OBJ_REF structure.
 445   CM_OBJECT_TOKEN    InterruptMapToken;
 446 } CM_ARM_PCI_CONFIG_SPACE_INFO;
 447
 448 /** A structure that describes the
 449     Hypervisor Vendor ID information for the Platform.
 450
 451     ID: EArmObjHypervisorVendorIdentity
 452 */
 453 typedef struct CmArmHypervisorVendorId {
 454   /// The hypervisor Vendor ID
 455   UINT64    HypervisorVendorId;
 456 } CM_ARM_HYPERVISOR_VENDOR_ID;
 457
 458 /** A structure that describes the
 459     Fixed feature flags for the Platform.
 460
 461     ID: EArmObjFixedFeatureFlags
 462 */
 463 typedef struct CmArmFixedFeatureFlags {
 464   /// The Fixed feature flags
 465   UINT32    Flags;
 466 } CM_ARM_FIXED_FEATURE_FLAGS;
 467
 468 /** A structure that describes the
 469     ITS Group node for the Platform.
 470
 471     ID: EArmObjItsGroup
 472 */
 473 typedef struct CmArmItsGroupNode {
 474   /// An unique token used to identify this object
 475   CM_OBJECT_TOKEN    Token;
 476   /// The number of ITS identifiers in the ITS node
 477   UINT32             ItsIdCount;
 478   /// Reference token for the ITS identifier array
 479   CM_OBJECT_TOKEN    ItsIdToken;
 480 } CM_ARM_ITS_GROUP_NODE;
 481
 482 /** A structure that describes the
 483     Named component node for the Platform.
 484
 485     ID: EArmObjNamedComponent
 486 */
 487 typedef struct CmArmNamedComponentNode {
 488   /// An unique token used to identify this object
 489   CM_OBJECT_TOKEN    Token;
 490   /// Number of ID mappings
 491   UINT32             IdMappingCount;
 492   /// Reference token for the ID mapping array
 493   CM_OBJECT_TOKEN    IdMappingToken;
 494
 495   /// Flags for the named component
 496   UINT32             Flags;
 497
 498   /// Memory access properties : Cache coherent attributes
 499   UINT32             CacheCoherent;
 500   /// Memory access properties : Allocation hints
 501   UINT8              AllocationHints;
 502   /// Memory access properties : Memory access flags
 503   UINT8              MemoryAccessFlags;
 504
 505   /// Memory access properties : Address size limit
 506   UINT8              AddressSizeLimit;
 507
 508   /** ASCII Null terminated string with the full path to
 509       the entry in the namespace for this object.
 510   */
 511   CHAR8              *ObjectName;
 512 } CM_ARM_NAMED_COMPONENT_NODE;
 513
 514 /** A structure that describes the
 515     Root complex node for the Platform.
 516
 517     ID: EArmObjRootComplex
 518 */
 519 typedef struct CmArmRootComplexNode {
 520   /// An unique token used to identify this object
 521   CM_OBJECT_TOKEN    Token;
 522   /// Number of ID mappings
 523   UINT32             IdMappingCount;
 524   /// Reference token for the ID mapping array
 525   CM_OBJECT_TOKEN    IdMappingToken;
 526
 527   /// Memory access properties : Cache coherent attributes
 528   UINT32             CacheCoherent;
 529   /// Memory access properties : Allocation hints
 530   UINT8              AllocationHints;
 531   /// Memory access properties : Memory access flags
 532   UINT8              MemoryAccessFlags;
 533
 534   /// ATS attributes
 535   UINT32             AtsAttribute;
 536   /// PCI segment number
 537   UINT32             PciSegmentNumber;
 538   /// Memory address size limit
 539   UINT8              MemoryAddressSize;
 540 } CM_ARM_ROOT_COMPLEX_NODE;
 541
 542 /** A structure that describes the
 543     SMMUv1 or SMMUv2 node for the Platform.
 544
 545     ID: EArmObjSmmuV1SmmuV2
 546 */
 547 typedef struct CmArmSmmuV1SmmuV2Node {
 548   /// An unique token used to identify this object
 549   CM_OBJECT_TOKEN    Token;
 550   /// Number of ID mappings
 551   UINT32             IdMappingCount;
 552   /// Reference token for the ID mapping array
 553   CM_OBJECT_TOKEN    IdMappingToken;
 554
 555   /// SMMU Base Address
 556   UINT64             BaseAddress;
 557   /// Length of the memory range covered by the SMMU
 558   UINT64             Span;
 559   /// SMMU Model
 560   UINT32             Model;
 561   /// SMMU flags
 562   UINT32             Flags;
 563
 564   /// Number of context interrupts
 565   UINT32             ContextInterruptCount;
 566   /// Reference token for the context interrupt array
 567   CM_OBJECT_TOKEN    ContextInterruptToken;
 568
 569   /// Number of PMU interrupts
 570   UINT32             PmuInterruptCount;
 571   /// Reference token for the PMU interrupt array
 572   CM_OBJECT_TOKEN    PmuInterruptToken;
 573
 574   /// GSIV of the SMMU_NSgIrpt interrupt
 575   UINT32             SMMU_NSgIrpt;
 576   /// SMMU_NSgIrpt interrupt flags
 577   UINT32             SMMU_NSgIrptFlags;
 578   /// GSIV of the SMMU_NSgCfgIrpt interrupt
 579   UINT32             SMMU_NSgCfgIrpt;
 580   /// SMMU_NSgCfgIrpt interrupt flags
 581   UINT32             SMMU_NSgCfgIrptFlags;
 582 } CM_ARM_SMMUV1_SMMUV2_NODE;
 583
 584 /** A structure that describes the
 585     SMMUv3 node for the Platform.
 586
 587     ID: EArmObjSmmuV3
 588 */
 589 typedef struct CmArmSmmuV3Node {
 590   /// An unique token used to identify this object
 591   CM_OBJECT_TOKEN    Token;
 592   /// Number of ID mappings
 593   UINT32             IdMappingCount;
 594   /// Reference token for the ID mapping array
 595   CM_OBJECT_TOKEN    IdMappingToken;
 596
 597   /// SMMU Base Address
 598   UINT64             BaseAddress;
 599   /// SMMU flags
 600   UINT32             Flags;
 601   /// VATOS address
 602   UINT64             VatosAddress;
 603   /// Model
 604   UINT32             Model;
 605   /// GSIV of the Event interrupt if SPI based
 606   UINT32             EventInterrupt;
 607   /// PRI Interrupt if SPI based
 608   UINT32             PriInterrupt;
 609   /// GERR interrupt if GSIV based
 610   UINT32             GerrInterrupt;
 611   /// Sync interrupt if GSIV based
 612   UINT32             SyncInterrupt;
 613
 614   /// Proximity domain flag
 615   UINT32             ProximityDomain;
 616   /// Index into the array of ID mapping
 617   UINT32             DeviceIdMappingIndex;
 618 } CM_ARM_SMMUV3_NODE;
 619
 620 /** A structure that describes the
 621     PMCG node for the Platform.
 622
 623     ID: EArmObjPmcg
 624 */
 625 typedef struct CmArmPmcgNode {
 626   /// An unique token used to identify this object
 627   CM_OBJECT_TOKEN    Token;
 628   /// Number of ID mappings
 629   UINT32             IdMappingCount;
 630   /// Reference token for the ID mapping array
 631   CM_OBJECT_TOKEN    IdMappingToken;
 632
 633   /// Base Address for performance monitor counter group
 634   UINT64             BaseAddress;
 635   /// GSIV for the Overflow interrupt
 636   UINT32             OverflowInterrupt;
 637   /// Page 1 Base address
 638   UINT64             Page1BaseAddress;
 639
 640   /// Reference token for the IORT node associated with this node
 641   CM_OBJECT_TOKEN    ReferenceToken;
 642 } CM_ARM_PMCG_NODE;
 643
 644 /** A structure that describes the
 645     GIC ITS Identifiers for an ITS Group node.
 646
 647     ID: EArmObjGicItsIdentifierArray
 648 */
 649 typedef struct CmArmGicItsIdentifier {
 650   /// The ITS Identifier
 651   UINT32    ItsId;
 652 } CM_ARM_ITS_IDENTIFIER;
 653
 654 /** A structure that describes the
 655     ID Mappings for the Platform.
 656
 657     ID: EArmObjIdMappingArray
 658 */
 659 typedef struct CmArmIdMapping {
 660   /// Input base
 661   UINT32             InputBase;
 662   /// Number of input IDs
 663   UINT32             NumIds;
 664   /// Output Base
 665   UINT32             OutputBase;
 666   /// Reference token for the output node
 667   CM_OBJECT_TOKEN    OutputReferenceToken;
 668   /// Flags
 669   UINT32             Flags;
 670 } CM_ARM_ID_MAPPING;
 671
 672 /** A structure that describes the Arm
 673     Generic Interrupts.
 674 */
 675 typedef struct CmArmGenericInterrupt {
 676   /// Interrupt number
 677   UINT32    Interrupt;
 678
 679   /// Flags
 680   /// BIT0: 0: Interrupt is Level triggered
 681   ///       1: Interrupt is Edge triggered
 682   /// BIT1: 0: Interrupt is Active high
 683   ///       1: Interrupt is Active low
 684   UINT32    Flags;
 685 } CM_ARM_GENERIC_INTERRUPT;
 686
 687 /** A structure that describes the SMMU interrupts for the Platform.
 688
 689     Interrupt   Interrupt number.
 690     Flags       Interrupt flags as defined for SMMU node.
 691
 692     ID: EArmObjSmmuInterruptArray
 693 */
 694 typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_SMMU_INTERRUPT;
 695
 696 /** A structure that describes the AML Extended Interrupts.
 697
 698     Interrupt   Interrupt number.
 699     Flags       Interrupt flags as defined by the Interrupt
 700                 Vector Flags (Byte 3) of the Extended Interrupt
 701                 resource descriptor.
 702                 See EFI_ACPI_EXTENDED_INTERRUPT_FLAG_xxx in Acpi10.h
 703 */
 704 typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_EXTENDED_INTERRUPT;
 705
 706 /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT
 707
 708     ID: EArmObjProcHierarchyInfo
 709 */
 710 typedef struct CmArmProcHierarchyInfo {
 711   /// A unique token used to identify this object
 712   CM_OBJECT_TOKEN    Token;
 713   /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)
 714   UINT32             Flags;
 715   /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor
 716   /// topology. A value of CM_NULL_TOKEN means this node has no parent.
 717   CM_OBJECT_TOKEN    ParentToken;
 718   /// Token of the associated CM_ARM_GICC_INFO object which has the
 719   /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this
 720   /// node represents a group of associated processors and it does not have an
 721   /// associated GIC CPU interface.
 722   CM_OBJECT_TOKEN    GicCToken;
 723   /// Number of resources private to this Node
 724   UINT32             NoOfPrivateResources;
 725   /// Token of the array which contains references to the resources private to
 726   /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if
 727   /// the NoOfPrivateResources is 0, in which case it is recommended to set
 728   /// this field to CM_NULL_TOKEN.
 729   CM_OBJECT_TOKEN    PrivateResourcesArrayToken;
 730   /// Optional field: Reference Token for the Lpi state of this processor.
 731   /// Token identifying a CM_ARM_OBJ_REF structure, itself referencing
 732   /// CM_ARM_LPI_INFO objects.
 733   CM_OBJECT_TOKEN    LpiToken;
 734 } CM_ARM_PROC_HIERARCHY_INFO;
 735
 736 /** A structure that describes the Cache Type Structure (Type 1) in PPTT
 737
 738     ID: EArmObjCacheInfo
 739 */
 740 typedef struct CmArmCacheInfo {
 741   /// A unique token used to identify this object
 742   CM_OBJECT_TOKEN    Token;
 743   /// Reference token for the next level of cache that is private to the same
 744   /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this
 745   /// entry represents the last cache level appropriate to the processor
 746   /// hierarchy node structures using this entry.
 747   CM_OBJECT_TOKEN    NextLevelOfCacheToken;
 748   /// Size of the cache in bytes
 749   UINT32             Size;
 750   /// Number of sets in the cache
 751   UINT32             NumberOfSets;
 752   /// Integer number of ways. The maximum associativity supported by
 753   /// ACPI Cache type structure is limited to MAX_UINT8. However,
 754   /// the maximum number of ways supported by the architecture is
 755   /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field
 756   /// is 32-bit wide.
 757   UINT32             Associativity;
 758   /// Cache attributes (ACPI 6.4 - January 2021, PPTT, Table 5.140)
 759   UINT8              Attributes;
 760   /// Line size in bytes
 761   UINT16             LineSize;
 762   /// Unique ID for the cache
 763   UINT32             CacheId;
 764 } CM_ARM_CACHE_INFO;
 765
 766 /** A structure that describes a reference to another Configuration Manager
 767     object.
 768
 769     This is useful for creating an array of reference tokens. The framework
 770     can then query the configuration manager for these arrays using the
 771     object ID EArmObjCmRef.
 772
 773     This can be used is to represent one-to-many relationships between objects.
 774
 775     ID: EArmObjCmRef
 776 */
 777 typedef struct CmArmObjRef {
 778   /// Token of the CM object being referenced
 779   CM_OBJECT_TOKEN    ReferenceToken;
 780 } CM_ARM_OBJ_REF;
 781
 782 /** A structure that describes the Memory Affinity Structure (Type 1) in SRAT
 783
 784     ID: EArmObjMemoryAffinityInfo
 785 */
 786 typedef struct CmArmMemoryAffinityInfo {
 787   /// The proximity domain to which the "range of memory" belongs.
 788   UINT32    ProximityDomain;
 789
 790   /// Base Address
 791   UINT64    BaseAddress;
 792
 793   /// Length
 794   UINT64    Length;
 795
 796   /// Flags
 797   UINT32    Flags;
 798 } CM_ARM_MEMORY_AFFINITY_INFO;
 799
 800 /** A structure that describes the ACPI Device Handle (Type 0) in the
 801     Generic Initiator Affinity structure in SRAT
 802
 803     ID: EArmObjDeviceHandleAcpi
 804 */
 805 typedef struct CmArmDeviceHandleAcpi {
 806   /// Hardware ID
 807   UINT64    Hid;
 808
 809   /// Unique Id
 810   UINT32    Uid;
 811 } CM_ARM_DEVICE_HANDLE_ACPI;
 812
 813 /** A structure that describes the PCI Device Handle (Type 1) in the
 814     Generic Initiator Affinity structure in SRAT
 815
 816     ID: EArmObjDeviceHandlePci
 817 */
 818 typedef struct CmArmDeviceHandlePci {
 819   /// PCI Segment Number
 820   UINT16    SegmentNumber;
 821
 822   /// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)
 823   UINT8     BusNumber;
 824
 825   /// PCI Device Number - Max 32 devices (Bits 7:3 of BDF)
 826   UINT8     DeviceNumber;
 827
 828   /// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)
 829   UINT8     FunctionNumber;
 830 } CM_ARM_DEVICE_HANDLE_PCI;
 831
 832 /** A structure that describes the Generic Initiator Affinity structure in SRAT
 833
 834     ID: EArmObjGenericInitiatorAffinityInfo
 835 */
 836 typedef struct CmArmGenericInitiatorAffinityInfo {
 837   /// The proximity domain to which the generic initiator belongs.
 838   UINT32             ProximityDomain;
 839
 840   /// Flags
 841   UINT32             Flags;
 842
 843   /// Device Handle Type
 844   UINT8              DeviceHandleType;
 845
 846   /// Reference Token for the Device Handle
 847   CM_OBJECT_TOKEN    DeviceHandleToken;
 848 } CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO;
 849
 850 /** A structure that describes the CMN-600 hardware.
 851
 852     ID: EArmObjCmn600Info
 853 */
 854 typedef struct CmArmCmn600Info {
 855   /// The PERIPHBASE address.
 856   /// Corresponds to the Configuration Node Region (CFGR) base address.
 857   UINT64    PeriphBaseAddress;
 858
 859   /// The PERIPHBASE address length.
 860   /// Corresponds to the CFGR base address length.
 861   UINT64    PeriphBaseAddressLength;
 862
 863   /// The ROOTNODEBASE address.
 864   /// Corresponds to the Root node (ROOT) base address.
 865   UINT64    RootNodeBaseAddress;
 866
 867   /// The Debug and Trace Logic Controller (DTC) count.
 868   /// CMN-600 can have maximum 4 DTCs.
 869   UINT8     DtcCount;
 870
 871   /// DTC Interrupt list.
 872   /// The first interrupt resource descriptor pertains to
 873   /// DTC[0], the second to DTC[1] and so on.
 874   /// DtcCount determines the number of DTC Interrupts that
 875   /// are populated. If DTC count is 2 then DtcInterrupt[2]
 876   /// and DtcInterrupt[3] are ignored.
 877   /// Note: The size of CM_ARM_CMN_600_INFO structure remains
 878   /// constant and does not vary with the DTC count.
 879   CM_ARM_EXTENDED_INTERRUPT    DtcInterrupt[4];
 880 } CM_ARM_CMN_600_INFO;
 881
 882 /** A structure that describes the Lpi information.
 883
 884   The Low Power Idle states are described in DSDT/SSDT and associated
 885   to cpus/clusters in the cpu topology.
 886
 887   ID: EArmObjLpiInfo
 888 */
 889 typedef struct CmArmLpiInfo {
 890   /** Minimum Residency. Time in microseconds after which a
 891       state becomes more energy efficient than any shallower state.
 892   */
 893   UINT32                                    MinResidency;
 894
 895   /** Worst case time in microseconds from a wake interrupt
 896       being asserted to the return to a running state
 897   */
 898   UINT32                                    WorstCaseWakeLatency;
 899
 900   /** Flags.
 901   */
 902   UINT32                                    Flags;
 903
 904   /** Architecture specific context loss flags.
 905   */
 906   UINT32                                    ArchFlags;
 907
 908   /** Residency counter frequency in cycles-per-second (Hz).
 909   */
 910   UINT32                                    ResCntFreq;
 911
 912   /** Every shallower power state in the parent is also enabled.
 913   */
 914   UINT32                                    EnableParentState;
 915
 916   /** The EntryMethod _LPI field can be described as an integer
 917       or in a Register resource data descriptor.
 918
 919   If IsInteger is TRUE, the IntegerEntryMethod field is used.
 920   If IsInteger is FALSE, the RegisterEntryMethod field is used.
 921   */
 922   BOOLEAN                                   IsInteger;
 923
 924   /** EntryMethod described as an Integer.
 925   */
 926   UINT64                                    IntegerEntryMethod;
 927
 928   /** EntryMethod described as a EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR.
 929   */
 930   EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE    RegisterEntryMethod;
 931
 932   /** Residency counter register.
 933   */
 934   EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE    ResidencyCounterRegister;
 935
 936   /** Usage counter register.
 937   */
 938   EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE    UsageCounterRegister;
 939
 940   /** String representing the Lpi state
 941   */
 942   CHAR8                                     StateName[16];
 943 } CM_ARM_LPI_INFO;
 944
 945 /** A structure that describes a PCI Address Map.
 946
 947   The memory-ranges used by the PCI bus are described by this object.
 948
 949   ID: EArmObjPciAddressMapInfo
 950 */
 951 typedef struct CmArmPciAddressMapInfo {
 952   /** Pci address space code
 953
 954   Available values are:
 955    - 0: Configuration Space
 956    - 1: I/O Space
 957    - 2: 32-bit-address Memory Space
 958    - 3: 64-bit-address Memory Space
 959   */
 960   UINT8     SpaceCode;
 961
 962   /// PCI address
 963   UINT64    PciAddress;
 964
 965   /// Cpu address
 966   UINT64    CpuAddress;
 967
 968   /// Address size
 969   UINT64    AddressSize;
 970 } CM_ARM_PCI_ADDRESS_MAP_INFO;
 971
 972 /** A structure that describes a PCI Interrupt Map.
 973
 974   The legacy PCI interrupts used by PCI devices are described by this object.
 975
 976   Cf Devicetree Specification - Release v0.3
 977   s2.4.3 "Interrupt Nexus Properties"
 978
 979   ID: EArmObjPciInterruptMapInfo
 980 */
 981 typedef struct CmArmPciInterruptMapInfo {
 982   /// Pci Bus.
 983   /// Value on 8 bits (max 255).
 984   UINT8    PciBus;
 985
 986   /// Pci Bus.
 987   /// Value on 5 bits (max 31).
 988   UINT8    PciDevice;
 989
 990   /** PCI interrupt
 991
 992   ACPI bindings are used:
 993   Cf. ACPI 6.4, s6.2.13 _PRT (PCI Routing Table):
 994       "0-INTA, 1-INTB, 2-INTC, 3-INTD"
 995
 996   Device-tree bindings are shifted by 1:
 997       "INTA=1, INTB=2, INTC=3, INTD=4"
 998   */
 999   UINT8                       PciInterrupt;
1000
1001   /** Interrupt controller interrupt.
1002
1003   Cf Devicetree Specification - Release v0.3
1004   s2.4.3 "Interrupt Nexus Properties": "parent interrupt specifier"
1005   */
1006   CM_ARM_GENERIC_INTERRUPT    IntcInterrupt;
1007 } CM_ARM_PCI_INTERRUPT_MAP_INFO;
1008
1009 #pragma pack()
1010
1011 #endif // ARM_NAMESPACE_OBJECTS_H_