3 Copyright (c) 2017 - 2018, ARM Limited. All rights reserved.
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 - Cm or CM - Configuration Manager
16 - Std or STD - Standard
19 #ifndef ARM_NAMESPACE_OBJECTS_H_
20 #define ARM_NAMESPACE_OBJECTS_H_
22 #include <StandardNameSpaceObjects.h>
26 /** The EARM_OBJECT_ID enum describes the Object IDs
29 typedef enum ArmObjectID
{
30 EArmObjReserved
, ///< 0 - Reserved
31 EArmObjBootArchInfo
, ///< 1 - Boot Architecture Info
32 EArmObjCpuInfo
, ///< 2 - CPU Info
33 EArmObjPowerManagementProfileInfo
, ///< 3 - Power Management Profile Info
34 EArmObjGicCInfo
, ///< 4 - GIC CPU Interface Info
35 EArmObjGicDInfo
, ///< 5 - GIC Distributor Info
36 EArmObjGicMsiFrameInfo
, ///< 6 - GIC MSI Frame Info
37 EArmObjGicRedistributorInfo
, ///< 7 - GIC Redistributor Info
38 EArmObjGicItsInfo
, ///< 8 - GIC ITS Info
39 EArmObjSerialConsolePortInfo
, ///< 9 - Serial Console Port Info
40 EArmObjSerialDebugPortInfo
, ///< 10 - Serial Debug Port Info
41 EArmObjGenericTimerInfo
, ///< 11 - Generic Timer Info
42 EArmObjPlatformGTBlockInfo
, ///< 12 - Platform GT Block Info
43 EArmObjGTBlockTimerFrameInfo
, ///< 13 - Generic Timer Block Frame Info
44 EArmObjPlatformGenericWatchdogInfo
, ///< 14 - Platform Generic Watchdog
45 EArmObjPciConfigSpaceInfo
, ///< 15 - PCI Configuration Space Info
46 EArmObjHypervisorVendorIdentity
, ///< 16 - Hypervisor Vendor Id
47 EArmObjFixedFeatureFlags
, ///< 17 - Fixed feature flags for FADT
48 EArmObjItsGroup
, ///< 18 - ITS Group
49 EArmObjNamedComponent
, ///< 19 - Named Component
50 EArmObjRootComplex
, ///< 20 - Root Complex
51 EArmObjSmmuV1SmmuV2
, ///< 21 - SMMUv1 or SMMUv2
52 EArmObjSmmuV3
, ///< 22 - SMMUv3
53 EArmObjPmcg
, ///< 23 - PMCG
54 EArmObjGicItsIdentifierArray
, ///< 24 - GIC ITS Identifier Array
55 EArmObjIdMapping
, ///< 25 - ID Mapping
56 EArmObjSmmuInterruptArray
, ///< 26 - SMMU Interrupt Array
60 /** A structure that describes the
61 ARM Boot Architecture flags.
63 typedef struct CmArmBootArchInfo
{
64 /** This is the ARM_BOOT_ARCH flags field of the FADT Table
65 described in the ACPI Table Specification.
68 } CM_ARM_BOOT_ARCH_INFO
;
70 typedef struct CmArmCpuInfo
{
71 // Reserved for use when SMBIOS tables are implemented
74 typedef struct CmArmCpuInfoList
{
76 CM_ARM_CPU_INFO
* CpuInfo
;
77 } CM_ARM_CPU_INFO_LIST
;
79 /** A structure that describes the
80 Power Management Profile Information for the Platform.
82 typedef struct CmArmPowerManagementProfileInfo
{
83 /** This is the Preferred_PM_Profile field of the FADT Table
84 described in the ACPI Specification
86 UINT8 PowerManagementProfile
;
87 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO
;
89 /** A structure that describes the
90 GIC CPU Interface for the Platform.
92 typedef struct CmArmGicCInfo
{
93 /// The GIC CPU Interface number.
94 UINT32 CPUInterfaceNumber
;
96 /** The ACPI Processor UID. This must match the
97 _UID of the CPU Device object information described
98 in the DSDT/SSDT for the CPU.
100 UINT32 AcpiProcessorUid
;
102 /** The flags field as described by the GICC structure
103 in the ACPI Specification.
107 /** The parking protocol version field as described by
108 the GICC structure in the ACPI Specification.
110 UINT32 ParkingProtocolVersion
;
112 /** The Performance Interrupt field as described by
113 the GICC structure in the ACPI Specification.
115 UINT32 PerformanceInterruptGsiv
;
117 /** The CPU Parked address field as described by
118 the GICC structure in the ACPI Specification.
120 UINT64 ParkedAddress
;
122 /** The base address for the GIC CPU Interface
123 as described by the GICC structure in the
126 UINT64 PhysicalBaseAddress
;
128 /** The base address for GICV interface
129 as described by the GICC structure in the
134 /** The base address for GICH interface
135 as described by the GICC structure in the
140 /** The GICV maintenance interrupt
141 as described by the GICC structure in the
144 UINT32 VGICMaintenanceInterrupt
;
146 /** The base address for GICR interface
147 as described by the GICC structure in the
150 UINT64 GICRBaseAddress
;
152 /** The MPIDR for the CPU
153 as described by the GICC structure in the
158 /** The Processor Power Efficiency class
159 as described by the GICC structure in the
162 UINT8 ProcessorPowerEfficiencyClass
;
165 /** A structure that describes the
166 GIC Distributor information for the Platform.
168 typedef struct CmArmGicDInfo
{
169 /// The GIC Distributor ID.
172 /// The Physical Base address for the GIC Distributor.
173 UINT64 PhysicalBaseAddress
;
175 /** The global system interrupt
176 number where this GIC Distributor's
177 interrupt inputs start.
179 UINT32 SystemVectorBase
;
181 /** The GIC version as described
182 by the GICD structure in the
188 /** A structure that describes the
189 GIC MSI Frame information for the Platform.
191 typedef struct CmArmGicMsiFrameInfo
{
192 /// The GIC MSI Frame ID
193 UINT32 GicMsiFrameId
;
195 /// The Physical base address for the MSI Frame
196 UINT64 PhysicalBaseAddress
;
198 /** The GIC MSI Frame flags
199 as described by the GIC MSI frame
200 structure in the ACPI Specification.
204 /// SPI Count used by this frame
207 /// SPI Base used by this frame
209 } CM_ARM_GIC_MSI_FRAME_INFO
;
211 /** A structure that describes the
212 GIC Redistributor information for the Platform.
214 typedef struct CmArmGicRedistInfo
{
215 /** The physical address of a page range
216 containing all GIC Redistributors.
218 UINT64 DiscoveryRangeBaseAddress
;
220 /// Length of the GIC Redistributor Discovery page range
221 UINT32 DiscoveryRangeLength
;
222 } CM_ARM_GIC_REDIST_INFO
;
224 /** A structure that describes the
225 GIC Interrupt Translation Service information for the Platform.
227 typedef struct CmArmGicItsInfo
{
231 /// The physical address for the Interrupt Translation Service
232 UINT64 PhysicalBaseAddress
;
233 } CM_ARM_GIC_ITS_INFO
;
235 /** A structure that describes the
236 Serial Port information for the Platform.
238 typedef struct CmArmSerialPortInfo
{
239 /// The physical base address for the serial port
242 /// The serial port interrupt
245 /// The serial port baud rate
248 /// The serial port clock
251 /// Serial Port subtype
253 } CM_ARM_SERIAL_PORT_INFO
;
255 /** A structure that describes the
256 Generic Timer information for the Platform.
258 typedef struct CmArmGenericTimerInfo
{
259 /// The physical base address for the counter control frame
260 UINT64 CounterControlBaseAddress
;
262 /// The physical base address for the counter read frame
263 UINT64 CounterReadBaseAddress
;
265 /// The secure PL1 timer interrupt
266 UINT32 SecurePL1TimerGSIV
;
268 /// The secure PL1 timer flags
269 UINT32 SecurePL1TimerFlags
;
271 /// The non-secure PL1 timer interrupt
272 UINT32 NonSecurePL1TimerGSIV
;
274 /// The non-secure PL1 timer flags
275 UINT32 NonSecurePL1TimerFlags
;
277 /// The virtual timer interrupt
278 UINT32 VirtualTimerGSIV
;
280 /// The virtual timer flags
281 UINT32 VirtualTimerFlags
;
283 /// The non-secure PL2 timer interrupt
284 UINT32 NonSecurePL2TimerGSIV
;
286 /// The non-secure PL2 timer flags
287 UINT32 NonSecurePL2TimerFlags
;
288 } CM_ARM_GENERIC_TIMER_INFO
;
290 /** A structure that describes the
291 Platform Generic Block Timer Frame information for the Platform.
293 typedef struct CmArmGTBlockTimerFrameInfo
{
294 /// The Generic Timer frame number
297 /// The physical base address for the CntBase block
298 UINT64 PhysicalAddressCntBase
;
300 /// The physical base address for the CntEL0Base block
301 UINT64 PhysicalAddressCntEL0Base
;
303 /// The physical timer interrupt
304 UINT32 PhysicalTimerGSIV
;
306 /** The physical timer flags as described by the GT Block
307 Timer frame Structure in the ACPI Specification.
309 UINT32 PhysicalTimerFlags
;
311 /// The virtual timer interrupt
312 UINT32 VirtualTimerGSIV
;
314 /** The virtual timer flags as described by the GT Block
315 Timer frame Structure in the ACPI Specification.
317 UINT32 VirtualTimerFlags
;
319 /** The common timer flags as described by the GT Block
320 Timer frame Structure in the ACPI Specification.
323 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO
;
325 /** A structure that describes the
326 Platform Generic Block Timer information for the Platform.
328 typedef struct CmArmGTBlockInfo
{
329 /// The physical base address for the GT Block Timer structure
330 UINT64 GTBlockPhysicalAddress
;
332 /// The number of timer frames implemented in the GT Block
333 UINT32 GTBlockTimerFrameCount
;
335 /// Reference token for the GT Block timer frame list
336 CM_OBJECT_TOKEN GTBlockTimerFrameToken
;
337 } CM_ARM_GTBLOCK_INFO
;
339 /** A structure that describes the
340 SBSA Generic Watchdog information for the Platform.
342 typedef struct CmArmGenericWatchdogInfo
{
343 /// The physical base address of the SBSA Watchdog control frame
344 UINT64 ControlFrameAddress
;
346 /// The physical base address of the SBSA Watchdog refresh frame
347 UINT64 RefreshFrameAddress
;
349 /// The watchdog interrupt
352 /** The flags for the watchdog as described by the SBSA watchdog
353 structure in the ACPI specification.
356 } CM_ARM_GENERIC_WATCHDOG_INFO
;
358 /** A structure that describes the
359 PCI Configuration Space information for the Platform.
361 typedef struct CmArmPciConfigSpaceInfo
{
362 /// The physical base address for the PCI segment
365 /// The PCI segment group number
366 UINT16 PciSegmentGroupNumber
;
368 /// The start bus number
369 UINT8 StartBusNumber
;
371 /// The end bus number
373 } CM_ARM_PCI_CONFIG_SPACE_INFO
;
375 /** A structure that describes the
376 Hypervisor Vendor ID information for the Platform.
378 typedef struct CmArmHypervisorVendorId
{
379 /// The hypervisor Vendor ID
380 UINT64 HypervisorVendorId
;
381 } CM_ARM_HYPERVISOR_VENDOR_ID
;
383 /** A structure that describes the
384 Fixed feature flags for the Platform.
386 typedef struct CmArmFixedFeatureFlags
{
387 /// The Fixed feature flags
389 } CM_ARM_FIXED_FEATURE_FLAGS
;
391 /** A structure that describes the
392 ITS Group node for the Platform.
394 typedef struct CmArmItsGroupNode
{
395 /// An unique token used to ideintify this object
396 CM_OBJECT_TOKEN Token
;
397 /// The number of ITS identifiers in the ITS node
399 /// Reference token for the ITS identifier array
400 CM_OBJECT_TOKEN ItsIdToken
;
401 } CM_ARM_ITS_GROUP_NODE
;
403 /** A structure that describes the
404 GIC ITS Identifiers for an ITS Group node.
406 typedef struct CmArmGicItsIdentifier
{
407 /// The ITS Identifier
409 } CM_ARM_ITS_IDENTIFIER
;
411 /** A structure that describes the
412 Named component node for the Platform.
414 typedef struct CmArmNamedComponentNode
{
415 /// An unique token used to ideintify this object
416 CM_OBJECT_TOKEN Token
;
417 /// Number of ID mappings
418 UINT32 IdMappingCount
;
419 /// Reference token for the ID mapping array
420 CM_OBJECT_TOKEN IdMappingToken
;
422 /// Flags for the named component
425 /// Memory access properties : Cache coherent attributes
426 UINT32 CacheCoherent
;
427 /// Memory access properties : Allocation hints
428 UINT8 AllocationHints
;
429 /// Memory access properties : Memory access flags
430 UINT8 MemoryAccessFlags
;
432 /// Memory access properties : Address size limit
433 UINT8 AddressSizeLimit
;
434 /** ASCII Null terminated string with the full path to
435 the entry in the namespace for this object.
438 } CM_ARM_NAMED_COMPONENT_NODE
;
440 /** A structure that describes the
441 Root complex node for the Platform.
443 typedef struct CmArmRootComplexNode
{
444 /// An unique token used to ideintify this object
445 CM_OBJECT_TOKEN Token
;
446 /// Number of ID mappings
447 UINT32 IdMappingCount
;
448 /// Reference token for the ID mapping array
449 CM_OBJECT_TOKEN IdMappingToken
;
451 /// Memory access properties : Cache coherent attributes
452 UINT32 CacheCoherent
;
453 /// Memory access properties : Allocation hints
454 UINT8 AllocationHints
;
455 /// Memory access properties : Memory access flags
456 UINT8 MemoryAccessFlags
;
460 /// PCI segment number
461 UINT32 PciSegmentNumber
;
462 /// Memory address size limit
463 UINT8 MemoryAddressSize
;
464 } CM_ARM_ROOT_COMPLEX_NODE
;
466 /** A structure that describes the
467 SMMUv1 or SMMUv2 node for the Platform.
469 typedef struct CmArmSmmuV1SmmuV2Node
{
470 /// An unique token used to ideintify this object
471 CM_OBJECT_TOKEN Token
;
472 /// Number of ID mappings
473 UINT32 IdMappingCount
;
474 /// Reference token for the ID mapping array
475 CM_OBJECT_TOKEN IdMappingToken
;
477 /// SMMU Base Address
479 /// Length of the memory range covered by the SMMU
486 /// Number of context interrupts
487 UINT32 ContextInterruptCount
;
488 /// Reference token for the context interrupt array
489 CM_OBJECT_TOKEN ContextInterruptToken
;
491 /// Number of PMU interrupts
492 UINT32 PmuInterruptCount
;
493 /// Reference token for the PMU interrupt array
494 CM_OBJECT_TOKEN PmuInterruptToken
;
496 /// GSIV of the SMMU_NSgIrpt interrupt
498 /// SMMU_NSgIrpt interrupt flags
499 UINT32 SMMU_NSgIrptFlags
;
500 /// GSIV of the SMMU_NSgCfgIrpt interrupt
501 UINT32 SMMU_NSgCfgIrpt
;
502 /// SMMU_NSgCfgIrpt interrupt flags
503 UINT32 SMMU_NSgCfgIrptFlags
;
504 } CM_ARM_SMMUV1_SMMUV2_NODE
;
506 /** A structure that describes the
507 SMMUv3 node for the Platform.
509 typedef struct CmArmSmmuV3Node
{
510 /// An unique token used to ideintify this object
511 CM_OBJECT_TOKEN Token
;
512 /// Number of ID mappings
513 UINT32 IdMappingCount
;
514 /// Reference token for the ID mapping array
515 CM_OBJECT_TOKEN IdMappingToken
;
517 /// SMMU Base Address
525 /// GSIV of the Event interrupt if SPI based
526 UINT32 EventInterrupt
;
527 /// PRI Interrupt if SPI based
529 /// GERR interrupt if GSIV based
530 UINT32 GerrInterrupt
;
531 /// Sync interrupt if GSIV based
532 UINT32 SyncInterrupt
;
534 /// Proximity domain flag
535 UINT32 ProximityDomain
;
536 /// Index into the array of ID mapping
537 UINT32 DeviceIdMappingIndex
;
538 } CM_ARM_SMMUV3_NODE
;
540 /** A structure that describes the
541 PMCG node for the Platform.
543 typedef struct CmArmPmcgNode
{
544 /// An unique token used to ideintify this object
545 CM_OBJECT_TOKEN Token
;
546 /// Number of ID mappings
547 UINT32 IdMappingCount
;
548 /// Reference token for the ID mapping array
549 CM_OBJECT_TOKEN IdMappingToken
;
551 /// Base Address for performance monitor counter group
553 /// GSIV for the Overflow interrupt
554 UINT32 OverflowInterrupt
;
555 /// Page 1 Base address
556 UINT64 Page1BaseAddress
;
558 /// Reference token for the IORT node associated with this node
559 CM_OBJECT_TOKEN ReferenceToken
;
562 /** A structure that describes the
563 ID Mappings for the Platform.
565 typedef struct CmArmIdMapping
{
568 /// Number of input IDs
572 /// Reference token for the output node
573 CM_OBJECT_TOKEN OutputReferenceToken
;
578 /** A structure that describes the
579 SMMU interrupts for the Platform.
581 typedef struct CmArmSmmuInterrupt
{
587 } CM_ARM_SMMU_INTERRUPT
;
591 #endif // ARM_NAMESPACE_OBJECTS_H_