3 Copyright (c) 2004 - 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
25 #define IA32API __cdecl
36 UINT32 UpdateRevision
;
40 UINT32 LoaderRevision
;
41 UINT32 ProcessorFlags
;
45 } EFI_CPU_MICROCODE_HEADER
;
48 UINT32 ExtendedSignatureCount
;
49 UINT32 ExtendedTableChecksum
;
51 } EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER
;
54 UINT32 ProcessorSignature
;
56 UINT32 ProcessorChecksum
;
57 } EFI_CPU_MICROCODE_EXTENDED_TABLE
;
65 UINT32 ExtendedModel
: 4;
66 UINT32 ExtendedFamily
: 8;
70 #define EFI_CPUID_SIGNATURE 0x0
71 #define EFI_CPUID_VERSION_INFO 0x1
72 #define EFI_CPUID_CACHE_INFO 0x2
73 #define EFI_CPUID_SERIAL_NUMBER 0x3
74 #define EFI_CPUID_EXTENDED_FUNCTION 0x80000000
75 #define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001
76 #define EFI_CPUID_BRAND_STRING1 0x80000002
77 #define EFI_CPUID_BRAND_STRING2 0x80000003
78 #define EFI_CPUID_BRAND_STRING3 0x80000004
80 #define EFI_MSR_IA32_PLATFORM_ID 0x17
81 #define EFI_MSR_IA32_APIC_BASE 0x1B
82 #define EFI_MSR_EBC_HARD_POWERON 0x2A
83 #define EFI_MSR_EBC_SOFT_POWERON 0x2B
84 #define BINIT_DRIVER_DISABLE 0x40
85 #define INTERNAL_MCERR_DISABLE 0x20
86 #define INITIATOR_MCERR_DISABLE 0x10
87 #define EFI_MSR_EBC_FREQUENCY_ID 0x2C
88 #define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79
89 #define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B
90 #define EFI_MSR_PSB_CLOCK_STATUS 0xCD
91 #define EFI_APIC_GLOBAL_ENABLE 0x800
92 #define EFI_MSR_IA32_MISC_ENABLE 0x1A0
93 #define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000
94 #define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008
95 #define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004
96 #define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002
97 #define FAST_STRING_ENABLE_BIT 0x00000001
99 #define EFI_CACHE_VARIABLE_MTRR_BASE 0x200
100 #define EFI_CACHE_VARIABLE_MTRR_END 0x20F
101 #define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF
102 #define EFI_CACHE_MTRR_VALID 0x800
103 #define EFI_CACHE_FIXED_MTRR_VALID 0x400
104 #define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000
105 #define EFI_MSR_VALID_MASK 0xFFFFFFFFF
106 #define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000
107 #define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF
109 #define EFI_IA32_MTRR_FIX64K_00000 0x250
110 #define EFI_IA32_MTRR_FIX16K_80000 0x258
111 #define EFI_IA32_MTRR_FIX16K_A0000 0x259
112 #define EFI_IA32_MTRR_FIX4K_C0000 0x268
113 #define EFI_IA32_MTRR_FIX4K_C8000 0x269
114 #define EFI_IA32_MTRR_FIX4K_D0000 0x26A
115 #define EFI_IA32_MTRR_FIX4K_D8000 0x26B
116 #define EFI_IA32_MTRR_FIX4K_E0000 0x26C
117 #define EFI_IA32_MTRR_FIX4K_E8000 0x26D
118 #define EFI_IA32_MTRR_FIX4K_F0000 0x26E
119 #define EFI_IA32_MTRR_FIX4K_F8000 0x26F
121 #define EFI_IA32_MCG_CAP 0x179
122 #define EFI_IA32_MCG_CTL 0x17B
123 #define EFI_IA32_MC0_CTL 0x400
124 #define EFI_IA32_MC0_STATUS 0x401
126 #define EFI_IA32_PERF_STATUS 0x198
127 #define EFI_IA32_PERF_CTL 0x199
129 #define EFI_CACHE_UNCACHEABLE 0
130 #define EFI_CACHE_WRITECOMBINING 1
131 #define EFI_CACHE_WRITETHROUGH 4
132 #define EFI_CACHE_WRITEPROTECTED 5
133 #define EFI_CACHE_WRITEBACK 6
136 // Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number
138 #define EfiMakeCpuVersion(f, m, s) \
139 (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))
165 Write back and invalidate the Cpu cache
180 Invalidate the Cpu cache
189 IN UINT32 RegisterInEax
,
190 OUT EFI_CPUID_REGISTER
*Regs
196 Get the Cpu info by excute the CPUID instruction
198 RegisterInEax: -The input value to put into register EAX
199 Regs: -The Output value
207 IN UINT32 RegisterInEax
,
208 IN UINT32 CacheLevel
,
209 OUT EFI_CPUID_REGISTER
*Regs
213 When RegisterInEax != 4, the functionality is the same as EfiCpuid.
214 When RegisterInEax == 4, the function return the deterministic cache
215 parameters by excuting the CPUID instruction
217 RegisterInEax: - The input value to put into register EAX
218 CacheLevel: - The deterministic cache level
219 Regs: - The Output value
236 Index: -The index value to select the register
253 Index: -The index value to select the register
254 Value: -The value to write to the selected register
282 Writing back and invalidate the cache,then diable it
297 Invalidate the cache,then Enable it
316 Return the Eflags value
320 EfiDisableInterrupts (
335 EfiEnableInterrupts (
353 IN UINT16
*FamilyId
, OPTIONAL
354 IN UINT8
*Model
, OPTIONAL
355 IN UINT8
*SteppingId
, OPTIONAL
356 IN UINT8
*Processor OPTIONAL
361 Extract CPU detail version infomation
364 FamilyId - FamilyId, including ExtendedFamilyId
365 Model - Model, including ExtendedModel
366 SteppingId - SteppingId
367 Processor - Processor