3 Copyright (c) 2007, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 DMARemappingReportingTable.h
18 The definition for ACPI DMA-Remapping Reporting (DMAR) Table.
19 It is defined in "Intel VT for Direct IO Architecture Specification".
23 #ifndef _EFI_DMA_REMAPPING_REPORTING_TABLE_H_
24 #define _EFI_DMA_REMAPPING_REPORTING_TABLE_H_
26 #include "AcpiCommon.h"
29 // "DMAR" DMAR Description Table Signature
31 #define EFI_ACPI_DMAR_DESCRIPTION_TABLE_SIGNATURE 0x52414d44
36 #define EFI_ACPI_DMAR_DESCRIPTION_TABLE_REVISION 0x01
39 // Ensure proper structure formats
44 // Definition for DMA Remapping Structure Types
46 #define EFI_ACPI_DMA_REMAPPING_STRUCTURE_TYPE_DRHD 0
47 #define EFI_ACPI_DMA_REMAPPING_STRUCTURE_TYPE_RMRR 1
48 #define EFI_ACPI_DMA_REMAPPING_STRUCTURE_TYPE_ATSR 2
51 // Definition for DMA Remapping Structure Header
56 } EFI_ACPI_DMAR_STRUCTURE_HEADER
;
59 // Definition for DMA-Remapping PCI Path
64 } EFI_ACPI_DMAR_PCI_PATH
;
67 // Definition for DMA-Remapping Device Scope Entry Structure
69 #define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ENDPOINT 0x01
70 #define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_BRIDGE 0x02
71 #define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC 0x03
72 #define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET 0x04
74 UINT8 DeviceScopeEntryType
;
78 UINT8 StartingBusNumber
;
79 } EFI_ACPI_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE
;
82 // Definition for DMA-Remapping Hardware Definition (DRHD) Structure
84 #define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_ALL_SET 0x1
85 #define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_ALL_CLEAR 0x0
92 UINT64 RegisterBaseAddress
;
93 } EFI_ACPI_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE
;
96 // Definition for Reserved Memory Region Reporting (RMRR) Structure
102 UINT16 SegmentNumber
;
103 UINT64 ReservedMemoryRegionBaseAddress
;
104 UINT64 ReservedMemoryRegionLimitAddress
;
105 } EFI_ACPI_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE
;
108 // Definition for Root Port ATS Capability Reporting (ATSR) Structure
110 #define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS_SET 0x1
111 #define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS_CLEAR 0x0
117 UINT16 SegmentNumber
;
118 } EFI_ACPI_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE
;
121 // Definition for DMA Remapping Structure
124 EFI_ACPI_DMAR_STRUCTURE_HEADER DMARStructureHeader
;
125 EFI_ACPI_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE DMARHardwareUnitDefinition
;
126 EFI_ACPI_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE DMARReservedMemoryRegionReporting
;
127 EFI_ACPI_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE DMARRootPortATSCapabilityReporting
;
128 } EFI_ACPI_DMA_REMAPPING_STRUCTURE
;
131 // Definition for DMA-Remapping Reporting ACPI Table
133 #define EFI_ACPI_DMAR_TABLE_FLAGS_INTR_REMAP_SET 0x01
135 EFI_ACPI_DESCRIPTION_HEADER Header
;
136 UINT8 HostAddressWidth
;
138 UINT8 Reserved_38
[10];
139 } EFI_ACPI_DMAR_DESCRIPTION_TABLE
;
142 // The Platform specific definition can be as follows:
143 // NOTE: we use /**/ as comment for user convenience to copy it.
152 #define EFI_ACPI_MAX_NUM_PCI_PATH_ENTRIES 0x01 // user need to update
154 EFI_ACPI_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE Header;
155 EFI_ACPI_DMAR_PCI_PATH PciPath[EFI_ACPI_MAX_NUM_PCI_PATH_ENTRIES];
156 } EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE;
158 #define EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_DHRD_ENTRY 0x01 // user need to update
160 EFI_ACPI_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE Header;
161 EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE DeviceScopeEntry[EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_DHRD_ENTRY];
162 } EFI_ACPI_3_0_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE;
164 #define EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_RMRR_ENTRY 0x01 // user need to update
166 EFI_ACPI_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE Header;
167 EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE DeviceScopeEntry[EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_RMRR_ENTRY];
168 } EFI_ACPI_3_0_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE;
170 #define EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_ATSR_ENTRY 0x01 // user need to update
172 EFI_ACPI_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE Header;
173 EFI_ACPI_3_0_DMAR_DEVICE_SCOPE_ENTRY_STRUCTURE DeviceScopeEntry[EFI_ACPI_MAX_NUM_OF_DEVICE_SCOPE_PER_ATSR_ENTRY];
174 } EFI_ACPI_3_0_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE;
176 #define EFI_ACPI_DMAR_DHRD_ENTRY_COUNT 0x1 // user need to update
177 #define EFI_ACPI_DMAR_RMRR_ENTRY_COUNT 0x1 // user need to update
178 #define EFI_ACPI_DMAR_ATSR_ENTRY_COUNT 0x1 // user need to update
181 EFI_ACPI_DMAR_DESCRIPTION_TABLE Header;
183 #if EFI_ACPI_3_0_DMAR_DHRD_ENTRY_COUNT > 0
184 EFI_ACPI_3_0_DMAR_HARDWARE_UNIT_DEFINITION_STRUCTURE Dhrd[EFI_ACPI_DMAR_DHRD_ENTRY_COUNT];
187 #if EFI_ACPI_3_0_DMAR_RMRR_ENTRY_COUNT > 0
188 EFI_ACPI_3_0_DMAR_RESERVED_MEMORY_REGION_REPORTING_STRUCTURE Rmrr[EFI_ACPI_DMAR_RMRR_ENTRY_COUNT];
191 #if EFI_ACPI_3_0_DMAR_ATSR_ENTRY_COUNT > 0
192 EFI_ACPI_3_0_DMAR_ROOT_PORT_ATS_CAPABILITY_REPORTING_STRUCTURE Atsr[EFI_ACPI_DMAR_ATSR_ENTRY_COUNT];
195 } EFI_ACPI_3_0_DMA_REMAPPING_REPORTING_TABLE;