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3 Copyright (c) 2007, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 This file contains definitions for the SPD fields on an SDRAM.
26 // SDRAM SPD field definitions
28 #define SPD_MEMORY_TYPE 2
29 #define SPD_SDRAM_ROW_ADDR 3
30 #define SPD_SDRAM_COL_ADDR 4
31 #define SPD_SDRAM_MODULE_ROWS 5
32 #define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6
33 #define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7
34 #define SPD_SDRAM_ECC_SUPPORT 11
35 #define SPD_SDRAM_REFRESH 12
36 #define SPD_SDRAM_WIDTH 13
37 #define SPD_SDRAM_ERROR_WIDTH 14
38 #define SPD_SDRAM_BURST_LENGTH 16
39 #define SPD_SDRAM_NO_OF_BANKS 17
40 #define SPD_SDRAM_CAS_LATENCY 18
41 #define SPD_SDRAM_MODULE_ATTR 21
43 #define SPD_SDRAM_TCLK1_PULSE 9 // cycle time for highest cas latency
44 #define SPD_SDRAM_TAC1_PULSE 10 // access time for highest cas latency
45 #define SPD_SDRAM_TCLK2_PULSE 23 // cycle time for 2nd highest cas latency
46 #define SPD_SDRAM_TAC2_PULSE 24 // access time for 2nd highest cas latency
47 #define SPD_SDRAM_TCLK3_PULSE 25 // cycle time for 3rd highest cas latency
48 #define SPD_SDRAM_TAC3_PULSE 26 // access time for 3rd highest cas latency
49 #define SPD_SDRAM_MIN_PRECHARGE 27
50 #define SPD_SDRAM_ACTIVE_MIN 28
51 #define SPD_SDRAM_RAS_CAS 29
52 #define SPD_SDRAM_RAS_PULSE 30
53 #define SPD_SDRAM_DENSITY 31
56 // Memory Type Definitions
58 #define SPD_VAL_SDR_TYPE 4 // SDR SDRAM memory
59 #define SPD_VAL_DDR_TYPE 7 // DDR SDRAM memory
60 #define SPD_VAL_DDR2_TYPE 8 // DDR2 SDRAM memory
62 // ECC Type Definitions
64 #define SPD_ECC_TYPE_NONE 0x00 // No error checking
65 #define SPD_ECC_TYPE_PARITY 0x01 // No error checking
66 #define SPD_ECC_TYPE_ECC 0x02 // Error checking only
68 // Module Attributes (Bit positions)
70 #define SPD_BUFFERED 0x01
71 #define SPD_REGISTERED 0x02