3 Copyright (c) 2007, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
30 UINT16 config
; /* General Configuration */
31 UINT16 cylinders
; /* Number of Cylinders */
33 UINT16 heads
; /* Number of logical heads */
36 UINT16 sectors_per_track
;
37 UINT16 vendor_specific_7_9
[3];
38 CHAR8 SerialNo
[20]; /* ASCII */
39 UINT16 vendor_specific_20_21
[2];
40 UINT16 ecc_bytes_available
;
41 CHAR8 FirmwareVer
[8]; /* ASCII */
42 CHAR8 ModelName
[40]; /* ASCII */
43 UINT16 multi_sector_cmd_max_sct_cnt
;
47 UINT16 pio_cycle_timing
;
49 UINT16 field_validity
;
50 UINT16 current_cylinders
;
52 UINT16 current_sectors
;
53 UINT16 CurrentCapacityLsb
;
54 UINT16 CurrentCapacityMsb
;
56 UINT16 user_addressable_sectors_lo
;
57 UINT16 user_addressable_sectors_hi
;
59 UINT16 multi_word_dma_mode
;
60 UINT16 advanced_pio_modes
;
61 UINT16 min_multi_word_dma_cycle_time
;
62 UINT16 rec_multi_word_dma_cycle_time
;
63 UINT16 min_pio_cycle_time_without_flow_control
;
64 UINT16 min_pio_cycle_time_with_flow_control
;
65 UINT16 reserved_69_79
[11];
66 UINT16 major_version_no
;
67 UINT16 minor_version_no
;
68 UINT16 reserved_82_127
[46];
69 UINT16 security_status
;
70 UINT16 vendor_data_129_159
[31];
71 UINT16 reserved_160_255
[96];
75 UINT8 peripheral_type
;
78 UINT8 response_data_format
;
85 UINT8 eeprom_product_code
[4];
86 UINT8 firmware_rev_level
[4];
87 UINT8 firmware_sub_rev_level
[1];
91 UINT8 max_capacity_hi
;
92 UINT8 max_capacity_mid
;
93 UINT8 max_capacity_lo
;
94 UINT8 reserved_43_95
[95 - 43 + 1];
96 UINT8 eeprom_drive_sno
[12];
100 UINT8 error_code
: 7;
104 UINT8 reserved_21
: 1;
106 UINT8 reserved_22
: 2;
107 UINT8 vendor_specific_3
;
108 UINT8 vendor_specific_4
;
109 UINT8 vendor_specific_5
;
110 UINT8 vendor_specific_6
;
111 UINT8 addnl_sense_length
; // n - 7
112 UINT8 vendor_specific_8
;
113 UINT8 vendor_specific_9
;
114 UINT8 vendor_specific_10
;
115 UINT8 vendor_specific_11
;
116 UINT8 addnl_sense_code
; // mandatory
117 UINT8 addnl_sense_code_qualifier
; // mandatory
118 UINT8 field_replaceable_unit_code
; // optional
123 // Followed by additional sense bytes : FIXME
125 } REQUEST_SENSE_DATA
;
136 } READ_CAPACITY_DATA
;
142 UINT8 Capacity_Length
;
148 UINT8 reserved_9
: 6;
152 } READ_FORMAT_CAPACITY_DATA
;
158 #define ATAPI_SOFT_RESET_CMD 0x08
159 #define PACKET_CMD 0xA0
160 #define ATAPI_IDENTIFY_DEVICE_CMD 0xA1
161 #define ATAPI_SERVICE_CMD 0xA2
164 // ATAPI Packet Command
181 } TEST_UNIT_READY_CMD
;
185 UINT8 reserved_1
: 4;
189 UINT8 allocation_length
;
201 UINT8 reserved_1
: 4;
205 UINT8 allocation_length
;
217 UINT8 reserved_1
: 5;
239 UINT8 allocation_length_hi
;
240 UINT8 allocation_length_lo
;
244 } READ_FORMAT_CAP_CMD
;
247 UINT8 peripheral_type
;
250 UINT8 response_data_format
;
255 UINT8 vendor_info
[8];
256 UINT8 product_id
[12];
257 UINT8 eeprom_product_code
[4];
258 UINT8 firmware_rev_level
[4];
263 TEST_UNIT_READY_CMD TestUnitReady
;
265 REQUEST_SENSE_CMD RequestSence
;
267 READ_FORMAT_CAP_CMD ReadFormatCapacity
;
268 } ATAPI_PACKET_COMMAND
;
272 // Packet Command Code
274 #define TEST_UNIT_READY 0x00
275 #define REQUEST_SENSE 0x03
277 #define READ_FORMAT_CAPACITY 0x23
278 #define READ_CAPACITY 0x25
281 #define DEFAULT_CTL (0x0a) // default content of device control register, disable INT
282 #define DEFAULT_CMD (0xa0)
284 #define MAX_ATAPI_BYTE_COUNT (0xfffe)
289 #define REQUEST_SENSE_ERROR (0x70)
290 #define SK_NO_SENSE (0x0)
291 #define SK_RECOVERY_ERROR (0x1)
292 #define SK_NOT_READY (0x2)
293 #define SK_MEDIUM_ERROR (0x3)
294 #define SK_HARDWARE_ERROR (0x4)
295 #define SK_ILLEGAL_REQUEST (0x5)
296 #define SK_UNIT_ATTENTION (0x6)
297 #define SK_DATA_PROTECT (0x7)
298 #define SK_BLANK_CHECK (0x8)
299 #define SK_VENDOR_SPECIFIC (0x9)
300 #define SK_RESERVED_A (0xA)
301 #define SK_ABORT (0xB)
302 #define SK_RESERVED_C (0xC)
303 #define SK_OVERFLOW (0xD)
304 #define SK_MISCOMPARE (0xE)
305 #define SK_RESERVED_F (0xF)
308 // Additional Sense Codes
310 #define ASC_NOT_READY (0x04)
311 #define ASC_MEDIA_ERR1 (0x10)
312 #define ASC_MEDIA_ERR2 (0x11)
313 #define ASC_MEDIA_ERR3 (0x14)
314 #define ASC_MEDIA_ERR4 (0x30)
315 #define ASC_MEDIA_UPSIDE_DOWN (0x06)
316 #define ASC_INVALID_CMD (0x20)
317 #define ASC_LBA_OUT_OF_RANGE (0x21)
318 #define ASC_INVALID_FIELD (0x24)
319 #define ASC_WRITE_PROTECTED (0x27)
320 #define ASC_MEDIA_CHANGE (0x28)
321 #define ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */
322 #define ASC_ILLEGAL_FIELD (0x26)
323 #define ASC_NO_MEDIA (0x3A)
324 #define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
327 // Additional Sense Code Qualifier
329 #define ASCQ_IN_PROGRESS (0x01)