1 /// Copyright (c) 2004, Intel Corporation
2 /// All rights reserved. This program and the accompanying materials
3 /// are licensed and made available under the terms and conditions of the BSD License
4 /// which accompanies this distribution. The full text of the license may be found at
5 /// http://opensource.org/licenses/bsd-license.php
7 /// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
8 /// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 #include "IpfDefines.h"
24 // Invalidates a range of instruction cache lines in the cache coherency domain
25 // of the calling CPU.
27 // Invalidates the instruction cache lines specified by Address and Length. If
28 // Address is not aligned on a cache line boundary, then entire instruction
29 // cache line containing Address is invalidated. If Address + Length is not
30 // aligned on a cache line boundary, then the entire instruction cache line
31 // containing Address + Length -1 is invalidated. This function may choose to
32 // invalidate the entire instruction cache if that is more efficient than
33 // invalidating the specified range. If Length is 0, the no instruction cache
34 // lines are invalidated. Address is returned.
35 // This function is only available on IPF.
37 // If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
39 // @param Address The base address of the instruction cache lines to
40 // invalidate. If the CPU is in a physical addressing mode, then
41 // Address is a physical address. If the CPU is in a virtual
42 // addressing mode, then Address is a virtual address.
44 // @param Length The number of bytes to invalidate from the instruction cache.
50 // AsmFlushCacheRange (
55 PROCEDURE_ENTRY (AsmFlushCacheRange)
57 NESTED_SETUP (5,8,0,0)
61 mov loc3 = in0 // Start address.
62 mov loc4 = in1;; // Length in bytes.
64 cmp.eq p6,p7 = loc4, r0;; // If Length is zero then don't flush any cache
65 (p6) br.spnt.many DoneFlushingC;;
69 sub loc4 = loc4, loc5 ;; // the End address to flush
71 dep loc3 = r0,loc3,0,5
72 dep loc4 = r0,loc4,0,5;;
74 shr loc4 = loc4,5;; // 32 byte cache line
76 sub loc4 = loc4,loc3;; // total flush count, It should be add 1 but
77 // the br.cloop will first execute one time
86 add loc3 = loc5,loc3;;
87 br.cloop.sptk.few StillFlushingC;;
91 mov r8 = in0 // return *Address
94 PROCEDURE_EXIT (AsmFlushCacheRange)