3 Copyright (c) 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
26 // Universal Host Controller Interface data structures and defines
28 #include <IndustryStandard/pci22.h>
31 extern UINTN gEHCDebugLevel
;
32 extern UINTN gEHCErrorLevel
;
35 #define STALL_1_MACRO_SECOND 1
36 #define STALL_1_MILLI_SECOND 1000 * STALL_1_MACRO_SECOND
37 #define STALL_1_SECOND 1000 * STALL_1_MILLI_SECOND
39 #define SETUP_PACKET_PID_CODE 0x02
40 #define INPUT_PACKET_PID_CODE 0x01
41 #define OUTPUT_PACKET_PID_CODE 0x0
43 #define ITD_SELECT_TYPE 0x0
44 #define QH_SELECT_TYPE 0x01
45 #define SITD_SELECT_TYPE 0x02
46 #define FSTN_SELECT_TYPE 0x03
48 #define EHCI_SET_PORT_RESET_RECOVERY_TIME 50 * STALL_1_MILLI_SECOND
49 #define EHCI_CLEAR_PORT_RESET_RECOVERY_TIME STALL_1_MILLI_SECOND
50 #define EHCI_GENERIC_TIMEOUT 50 * STALL_1_MILLI_SECOND
51 #define EHCI_GENERIC_RECOVERY_TIME 50 * STALL_1_MACRO_SECOND
52 #define EHCI_SYNC_REQUEST_POLLING_TIME 50 * STALL_1_MACRO_SECOND
53 #define EHCI_ASYNC_REQUEST_POLLING_TIME 50 * STALL_1_MILLI_SECOND
55 #define USB_BAR_INDEX 0 /* how many bytes away from USB_BASE to 0x10 */
57 #define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 1
59 #define EHCI_MIN_PACKET_SIZE 8
60 #define EHCI_MAX_PACKET_SIZE 1024
61 #define EHCI_MAX_FRAME_LIST_LENGTH 1024
62 #define EHCI_BLOCK_SIZE_WITH_TT 64
63 #define EHCI_BLOCK_SIZE 512
64 #define EHCI_MAX_QTD_CAPACITY (EFI_PAGE_SIZE * 5)
66 #define NAK_COUNT_RELOAD 3
67 #define QTD_ERROR_COUNTER 1
68 #define HIGH_BANDWIDTH_PIPE_MULTIPLIER 1
70 #define QTD_STATUS_ACTIVE 0x80
71 #define QTD_STATUS_HALTED 0x40
72 #define QTD_STATUS_BUFFER_ERR 0x20
73 #define QTD_STATUS_BABBLE_ERR 0x10
74 #define QTD_STATUS_TRANSACTION_ERR 0x08
75 #define QTD_STATUS_DO_STOP_SPLIT 0x02
76 #define QTD_STATUS_DO_START_SPLIT 0
77 #define QTD_STATUS_DO_PING 0x01
78 #define QTD_STATUS_DO_OUT 0
83 #define MICRO_FRAME_0_CHANNEL 0x01
84 #define MICRO_FRAME_1_CHANNEL 0x02
85 #define MICRO_FRAME_2_CHANNEL 0x04
86 #define MICRO_FRAME_3_CHANNEL 0x08
87 #define MICRO_FRAME_4_CHANNEL 0x10
88 #define MICRO_FRAME_5_CHANNEL 0x20
89 #define MICRO_FRAME_6_CHANNEL 0x40
90 #define MICRO_FRAME_7_CHANNEL 0x80
92 #define CONTROL_TRANSFER 0x01
93 #define BULK_TRANSFER 0x02
94 #define SYNC_INTERRUPT_TRANSFER 0x04
95 #define ASYNC_INTERRUPT_TRANSFER 0x08
96 #define SYNC_ISOCHRONOUS_TRANSFER 0x10
97 #define ASYNC_ISOCHRONOUS_TRANSFER 0x20
101 // Enhanced Host Controller Registers definitions
103 extern UINT32 mUsbCapabilityLen
;
104 extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding
;
105 extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName
;
107 #define USBCMD 0x0 /* Command Register Offset 00-03h */
108 #define USBCMD_RS 0x01 /* Run / Stop */
109 #define USBCMD_HCRESET 0x02 /* Host controller reset */
110 #define USBCMD_FLS_512 0x04 /* 512 elements (2048bytes) in Frame List */
111 #define USBCMD_FLS_256 0x08 /* 256 elements (1024bytes) in Frame List */
112 #define USBCMD_PSE 0x10 /* Periodic schedule enable */
113 #define USBCMD_ASE 0x20 /* Asynchronous schedule enable */
114 #define USBCMD_IAAD 0x40 /* Interrupt on async advance doorbell */
116 #define USBSTS 0x04 /* Statue Register Offset 04-07h */
117 #define USBSTS_HSE 0x10 /* Host system error */
118 #define USBSTS_IAA 0x20 /* Interrupt on async advance */
119 #define USBSTS_HCH 0x1000 /* Host controller halted */
120 #define USBSTS_PSS 0x4000 /* Periodic schedule status */
121 #define USBSTS_ASS 0x8000 /* Asynchronous schedule status */
123 #define USBINTR 0x08 /* Command Register Offset 08-0bh */
125 #define FRINDEX 0x0c /* Frame Index Offset 0c-0fh */
127 #define CTRLDSSGMENT 0x10 /* 4G Segment Selector Offset 10-13h */
129 #define PERIODICLISTBASE 0x14 /* Frame List Base Address Offset 14-17h */
131 #define ASYNCLISTADDR 0x18 /* Next Asynchronous List Address Offset 18-1bh */
133 #define CONFIGFLAG 0x40 /* Configured Flag Register Offset 40-43h */
134 #define CONFIGFLAG_CF 0x01 /* Configure Flag */
136 #define PORTSC 0x44 /* Port Status/Control Offset 44-47h */
137 #define PORTSC_CCS 0x01 /* Current Connect Status*/
138 #define PORTSC_CSC 0x02 /* Connect Status Change */
139 #define PORTSC_PED 0x04 /* Port Enable / Disable */
140 #define PORTSC_PEDC 0x08 /* Port Enable / Disable Change */
141 #define PORTSC_OCA 0x10 /* Over current Active */
142 #define PORTSC_OCC 0x20 /* Over current Change */
143 #define PORTSC_FPR 0x40 /* Force Port Resume */
144 #define PORTSC_SUSP 0x80 /* Port Suspend State */
145 #define PORTSC_PR 0x100 /* Port Reset */
146 #define PORTSC_LS_KSTATE 0x400 /* Line Status K-state */
147 #define PORTSC_LS_JSTATE 0x800 /* Line Status J-state */
148 #define PORTSC_PP 0x1000 /* Port Power */
149 #define PORTSC_PO 0x2000 /* Port Owner */
151 #define CAPLENGTH 0 /* Capability Register Length 00h */
153 #define HCIVERSION 0x02 /* Interface Version Number 02-03h */
155 #define HCSPARAMS 0x04 /* Structural Parameters 04-07h */
156 #define HCSP_NPORTS 0x0f /* Number of physical downstream ports on host controller */
158 #define HCCPARAMS 0x08 /* Capability Parameters 08-0bh */
159 #define HCCP_64BIT 0x01 /* 64-bit Addressing Capability */
160 #define HCCP_PFLF 0x02 /* Programmable Frame List Flag */
161 #define HCCP_EECP 0xff00 /* EHCI Extemded Capabilities Pointer */
163 #define HCSPPORTROUTE 0x0c /* Companion Port Route Description 60b */
165 #define CLASSC 0x09 /* Class Code 09-0bh */
167 #define USBBASE 0x10 /* Base Address to Memory-mapped Host Controller Register Space 10-13h */
169 #define SBRN 0x60 /* Serial Bus Release Number 60h */
171 #define FLADJ 0x61 /* Frame Length Adjustment Register 61h */
173 #define PORTWAKECAP 0x62 /* Port wake capablilities register(OPIONAL) 61-62h */
176 // PCI Configuration Registers
178 #define EHCI_PCI_CLASSC 0x09
179 #define EHCI_PCI_MEMORY_BASE 0x10
182 // Memory Offset Registers
184 #define EHCI_MEMORY_CAPLENGTH 0x0
185 #define EHCI_MEMORY_CONFIGFLAG 0x40
188 // USB Base Class Code,Sub-Class Code and Programming Interface
190 #define PCI_CLASSC_PI_EHCI 0x20
192 #define SETUP_PACKET_ID 0x2D
193 #define INPUT_PACKET_ID 0x69
194 #define OUTPUT_PACKET_ID 0xE1
195 #define ERROR_PACKET_ID 0x55
197 #define bit(a) (1 << (a))
199 #define GET_0B_TO_31B(Addr) (((UINTN) Addr) & (0xffffffff))
200 #define GET_32B_TO_63B(Addr) ((UINTN)RShiftU64((UINTN) Addr, 32) & (0xffffffff))
204 // Ehci Data and Ctrl Structures
215 UINT32 NextQtdTerminate
: 1;
217 UINT32 NextQtdPointer
: 27;
219 UINT32 AltNextQtdTerminate
: 1;
221 UINT32 AltNextQtdPointer
: 27;
225 UINT32 ErrorCount
: 2;
226 UINT32 CurrentPage
: 3;
227 UINT32 InterruptOnComplete
: 1;
228 UINT32 TotalBytes
: 15;
229 UINT32 DataToggle
: 1;
231 UINT32 CurrentOffset
: 12;
232 UINT32 BufferPointer0
: 20;
235 UINT32 BufferPointer1
: 20;
238 UINT32 BufferPointer2
: 20;
241 UINT32 BufferPointer3
: 20;
244 UINT32 BufferPointer4
: 20;
246 UINT32 ExtBufferPointer0
;
247 UINT32 ExtBufferPointer1
;
248 UINT32 ExtBufferPointer2
;
249 UINT32 ExtBufferPointer3
;
250 UINT32 ExtBufferPointer4
;
254 UINT32 QhTerminate
: 1;
255 UINT32 SelectType
: 2;
257 UINT32 QhHorizontalPointer
: 27;
259 UINT32 DeviceAddr
: 7;
261 UINT32 EndpointNum
: 4;
262 UINT32 EndpointSpeed
: 2;
263 UINT32 DataToggleControl
: 1;
264 UINT32 HeadReclamationFlag
: 1;
265 UINT32 MaxPacketLen
: 11;
266 UINT32 ControlEndpointFlag
: 1;
267 UINT32 NakCountReload
: 4;
269 UINT32 InerruptScheduleMask
: 8;
270 UINT32 SplitComletionMask
: 8;
273 UINT32 Multiplier
: 2;
276 UINT32 CurrentQtdPointer
: 27;
278 UINT32 NextQtdTerminate
: 1;
280 UINT32 NextQtdPointer
: 27;
282 UINT32 AltNextQtdTerminate
: 1;
284 UINT32 AltNextQtdPointer
: 27;
288 UINT32 ErrorCount
: 2;
289 UINT32 CurrentPage
: 3;
290 UINT32 InterruptOnComplete
: 1;
291 UINT32 TotalBytes
: 15;
292 UINT32 DataToggle
: 1;
294 UINT32 CurrentOffset
: 12;
295 UINT32 BufferPointer0
: 20;
297 UINT32 CompleteSplitMask
: 8;
299 UINT32 BufferPointer1
: 20;
302 UINT32 SplitBytes
: 7;
303 UINT32 BufferPointer2
: 20;
306 UINT32 BufferPointer3
: 20;
309 UINT32 BufferPointer4
: 20;
311 UINT32 ExtBufferPointer0
;
312 UINT32 ExtBufferPointer1
;
313 UINT32 ExtBufferPointer2
;
314 UINT32 ExtBufferPointer3
;
315 UINT32 ExtBufferPointer4
;
319 UINT32 LinkTerminate
: 1;
320 UINT32 SelectType
: 2;
322 UINT32 LinkPointer
: 27;
327 typedef struct _EHCI_QTD_ENTITY EHCI_QTD_ENTITY
;
328 typedef struct _EHCI_QH_ENTITY EHCI_QH_ENTITY
;
329 typedef struct _EHCI_ASYNC_REQUEST EHCI_ASYNC_REQUEST
;
331 struct _EHCI_QTD_ENTITY
{
334 UINT32 StaticTotalBytes
;
335 UINT32 StaticCurrentOffset
;
336 EHCI_QTD_ENTITY
*Prev
;
337 EHCI_QTD_ENTITY
*Next
;
338 EHCI_QTD_ENTITY
*AltNext
;
339 EHCI_QH_ENTITY
*SelfQh
;
342 struct _EHCI_QH_ENTITY
{
344 EHCI_QH_ENTITY
*Next
;
345 EHCI_QH_ENTITY
*Prev
;
346 EHCI_QTD_ENTITY
*FirstQtdPtr
;
347 EHCI_QTD_ENTITY
*LastQtdPtr
;
348 EHCI_QTD_ENTITY
*AltQtdPtr
;
353 #define GET_QH_ENTITY_ADDR(a) ((EHCI_QH_ENTITY *) a)
354 #define GET_QTD_ENTITY_ADDR(a) ((EHCI_QTD_ENTITY *) a)
358 // Ehci Managment Structures
360 #define USB2_HC_DEV_FROM_THIS(a) CR (a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)
362 #define USB2_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('e', 'h', 'c', 'i')
364 struct _EHCI_ASYNC_REQUEST
{
366 EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunc
;
368 EHCI_ASYNC_REQUEST
*Prev
;
369 EHCI_ASYNC_REQUEST
*Next
;
370 EHCI_QH_ENTITY
*QhPtr
;
373 typedef struct _MEMORY_MANAGE_HEADER
{
375 UINTN BitArraySizeInBytes
;
376 UINT8
*MemoryBlockPtr
;
377 UINTN MemoryBlockSizeInBytes
;
379 struct _MEMORY_MANAGE_HEADER
*Next
;
380 } MEMORY_MANAGE_HEADER
;
382 typedef struct _USB2_HC_DEV
{
384 EFI_PCI_IO_PROTOCOL
*PciIo
;
385 EFI_USB2_HC_PROTOCOL Usb2Hc
;
386 UINTN PeriodicFrameListLength
;
387 VOID
*PeriodicFrameListBuffer
;
388 VOID
*PeriodicFrameListMap
;
390 EHCI_ASYNC_REQUEST
*AsyncRequestList
;
391 EFI_EVENT AsyncRequestEvent
;
392 EFI_UNICODE_STRING_TABLE
*ControllerNameTable
;
393 MEMORY_MANAGE_HEADER
*MemoryHeader
;
394 UINT8 Is64BitCapable
;
395 UINT32 High32BitAddr
;
400 // Internal Functions Declaration
408 IN USB2_HC_DEV
*HcDev
,
409 OUT MEMORY_MANAGE_HEADER
**MemoryHeader
,
410 IN UINTN MemoryBlockSizeInPages
416 Use PciIo->AllocateBuffer to allocate common buffer for the memory block,
417 and use PciIo->Map to map the common buffer for Bus Master Read/Write.
422 MemoryHeader - MEMORY_MANAGE_HEADER to output
423 MemoryBlockSizeInPages - MemoryBlockSizeInPages
428 EFI_OUT_OF_RESOURCES Fail for no resources
429 EFI_UNSUPPORTED Unsupported currently
436 IN USB2_HC_DEV
*HcDev
,
437 IN MEMORY_MANAGE_HEADER
*MemoryHeader
448 MemoryHeader - MemoryHeader to be freed
453 EFI_INVALID_PARAMETER Parameter is error
459 InsertMemoryHeaderToList (
460 IN MEMORY_MANAGE_HEADER
*MemoryHeader
,
461 IN MEMORY_MANAGE_HEADER
*NewMemoryHeader
467 Insert Memory Header To List
471 MemoryHeader - MEMORY_MANAGE_HEADER
472 NewMemoryHeader - MEMORY_MANAGE_HEADER
482 AllocMemInMemoryBlock (
483 IN MEMORY_MANAGE_HEADER
*MemoryHeader
,
485 IN UINTN NumberOfMemoryUnit
491 Alloc Memory In MemoryBlock
495 MemoryHeader - MEMORY_MANAGE_HEADER
496 Pool - Place to store pointer to memory
497 NumberOfMemoryUnit - Number Of Memory Unit
502 EFI_NOT_FOUND Can't find the free memory
508 IsMemoryBlockEmptied (
509 IN MEMORY_MANAGE_HEADER
*MemoryHeaderPtr
515 Is Memory Block Emptied
519 MemoryHeaderPtr - MEMORY_MANAGE_HEADER
531 IN MEMORY_MANAGE_HEADER
*FirstMemoryHeader
,
532 IN MEMORY_MANAGE_HEADER
*NeedFreeMemoryHeader
542 FirstMemoryHeader - MEMORY_MANAGE_HEADER
543 NeedFreeMemoryHeader - MEMORY_MANAGE_HEADER
553 InitialMemoryManagement (
554 IN USB2_HC_DEV
*HcDev
560 Initialize Memory Management
569 EFI_DEVICE_ERROR Fail
575 DeinitialMemoryManagement (
576 IN USB2_HC_DEV
*HcDev
582 Deinitialize Memory Management
591 EFI_DEVICE_ERROR Fail
598 IN USB2_HC_DEV
*HcDev
,
611 Pool - Place to store pointer to the memory buffer
612 AllocSize - Alloc Size
617 EFI_DEVICE_ERROR Fail
624 IN USB2_HC_DEV
*HcDev
,
638 AllocSize - Pool size
651 ReadEhcCapabiltiyReg (
652 IN USB2_HC_DEV
*HcDev
,
653 IN UINT32 CapabiltiyRegAddr
,
660 Read Ehc Capabitlity register
665 CapabiltiyRegAddr - Ehc Capability register address
666 Data - A pointer to data read from register
671 EFI_DEVICE_ERROR Fail
677 ReadEhcOperationalReg (
678 IN USB2_HC_DEV
*HcDev
,
679 IN UINT32 OperationalRegAddr
,
686 Read Ehc Operation register
691 OperationalRegAddr - Ehc Operation register address
692 Data - A pointer to data read from register
697 EFI_DEVICE_ERROR Fail
703 WriteEhcOperationalReg (
704 IN USB2_HC_DEV
*HcDev
,
705 IN UINT32 OperationalRegAddr
,
712 Write Ehc Operation register
717 OperationalRegAddr - Ehc Operation register address
718 Data - 32bit write to register
723 EFI_DEVICE_ERROR Fail
730 IN USB2_HC_DEV
*HcDev
736 Set Ehc door bell bit
745 EFI_DEVICE_ERROR Fail
752 IN USB2_HC_DEV
*HcDev
,
759 Set the length of Frame List
764 Length - the required length of frame list
769 EFI_INVALID_PARAMETER Invalid parameter
770 EFI_DEVICE_ERROR Fail
776 IsFrameListProgrammable (
777 IN USB2_HC_DEV
*HcDev
783 Whether frame list is programmable
798 IsPeriodicScheduleEnabled (
799 IN USB2_HC_DEV
*HcDev
805 Whether periodic schedule is enabled
820 IsAsyncScheduleEnabled (
821 IN USB2_HC_DEV
*HcDev
827 Whether asynchronous schedule is enabled
843 IN USB2_HC_DEV
*HcDev
,
850 Whether port is enabled
866 IN USB2_HC_DEV
*HcDev
872 Whether Ehc is halted
888 IN USB2_HC_DEV
*HcDev
894 Whether Ehc is halted
910 IN USB2_HC_DEV
*HcDev
916 Whether Ehc is system error
925 FALSE No system error
932 IN EFI_USB2_HC_PROTOCOL
*This
,
939 Whether high speed device attached
955 IN USB2_HC_DEV
*HcDev
,
962 wait for Ehc reset or timeout
967 Timeout - timeout threshold
979 IN USB2_HC_DEV
*HcDev
,
986 wait for Ehc halt or timeout
991 Timeout - timeout threshold
1003 IN USB2_HC_DEV
*HcDev
,
1008 Routine Description:
1010 wait for Ehc not halt or timeout
1015 Timeout - timeout threshold
1026 WaitForEhcDoorbell (
1027 IN USB2_HC_DEV
*HcDev
,
1032 Routine Description:
1034 Wait for periodic schedule disable or timeout
1039 Timeout - timeout threshold
1050 WaitForAsyncScheduleEnable (
1051 IN USB2_HC_DEV
*HcDev
,
1056 Routine Description:
1058 Wait for Ehc asynchronous schedule enable or timeout
1063 Timeout - timeout threshold
1074 WaitForAsyncScheduleDisable (
1075 IN USB2_HC_DEV
*HcDev
,
1080 Routine Description:
1082 Wait for Ehc asynchronous schedule disable or timeout
1087 Timeout - timeout threshold
1098 WaitForPeriodicScheduleEnable (
1099 IN USB2_HC_DEV
*HcDev
,
1104 Routine Description:
1106 Wait for Ehc periodic schedule enable or timeout
1111 Timeout - timeout threshold
1122 WaitForPeriodicScheduleDisable (
1123 IN USB2_HC_DEV
*HcDev
,
1128 Routine Description:
1130 Wait for periodic schedule disable or timeout
1135 Timeout - timeout threshold
1147 IN USB2_HC_DEV
*HcDev
1151 Routine Description:
1153 Get the length of capability register
1162 EFI_DEVICE_ERROR Fail
1168 SetFrameListBaseAddr (
1169 IN USB2_HC_DEV
*HcDev
,
1170 IN UINT32 FrameBuffer
1174 Routine Description:
1176 Set base address of frame list first entry
1181 FrameBuffer - base address of first entry of frame list
1186 EFI_DEVICE_ERROR Fail
1193 IN USB2_HC_DEV
*HcDev
,
1194 IN EHCI_QH_ENTITY
*QhPtr
1198 Routine Description:
1200 Set address of first Async schedule Qh
1205 QhPtr - A pointer to first Qh in the Async schedule
1210 EFI_DEVICE_ERROR Fail
1216 SetCtrlDataStructSeg (
1217 IN USB2_HC_DEV
*HcDev
1221 Routine Description:
1223 Set address of first Async schedule Qh
1228 QhPtr - A pointer to first Qh in the Async schedule
1233 EFI_DEVICE_ERROR Fail
1240 IN USB2_HC_DEV
*HcDev
1244 Routine Description:
1246 Set Ehc port routing bit
1255 EFI_DEVICE_ERROR Fail
1261 EnablePeriodicSchedule (
1262 IN USB2_HC_DEV
*HcDev
1266 Routine Description:
1268 Enable periodic schedule
1277 EFI_DEVICE_ERROR Fail
1283 DisablePeriodicSchedule (
1284 IN USB2_HC_DEV
*HcDev
1288 Routine Description:
1290 Disable periodic schedule
1299 EFI_DEVICE_ERROR Fail
1305 EnableAsynchronousSchedule (
1306 IN USB2_HC_DEV
*HcDev
1310 Routine Description:
1312 Enable asynchrounous schedule
1321 EFI_DEVICE_ERROR Fail
1327 DisableAsynchronousSchedule (
1328 IN USB2_HC_DEV
*HcDev
1332 Routine Description:
1334 Disable asynchrounous schedule
1343 EFI_DEVICE_ERROR Fail
1349 StartScheduleExecution (
1350 IN USB2_HC_DEV
*HcDev
1354 Routine Description:
1356 Start Ehc schedule execution
1365 EFI_DEVICE_ERROR Fail
1372 IN USB2_HC_DEV
*HcDev
1376 Routine Description:
1387 EFI_DEVICE_ERROR Fail
1394 IN USB2_HC_DEV
*HcDev
1398 Routine Description:
1400 Clear Ehc all status bits
1409 EFI_DEVICE_ERROR Fail
1415 // EhciSched Functions
1418 InitialPeriodicFrameList (
1419 IN USB2_HC_DEV
*HcDev
,
1424 Routine Description:
1426 Initialize Periodic Schedule Frame List
1431 Length - Frame List Length
1436 EFI_DEVICE_ERROR Fail
1442 DeinitialPeriodicFrameList (
1443 IN USB2_HC_DEV
*HcDev
1447 Routine Description:
1449 Deinitialize Periodic Schedule Frame List
1463 CreatePollingTimer (
1464 IN USB2_HC_DEV
*HcDev
,
1465 IN EFI_EVENT_NOTIFY NotifyFunction
1469 Routine Description:
1471 Create Async Request Polling Timer
1476 NotifyFunction - Timer Notify Function
1481 EFI_DEVICE_ERROR Fail
1487 DestoryPollingTimer (
1488 IN USB2_HC_DEV
*HcDev
1492 Routine Description:
1494 Destory Async Request Polling Timer
1503 EFI_DEVICE_ERROR Fail
1510 IN USB2_HC_DEV
*HcDev
1514 Routine Description:
1516 Start Async Request Polling Timer
1525 EFI_DEVICE_ERROR Fail
1532 IN USB2_HC_DEV
*HcDev
1536 Routine Description:
1538 Stop Async Request Polling Timer
1547 EFI_DEVICE_ERROR Fail
1554 IN USB2_HC_DEV
*HcDev
,
1555 IN UINT8 DeviceAddr
,
1557 IN UINT8 DeviceSpeed
,
1558 IN UINTN MaxPacketLen
,
1559 OUT EHCI_QH_ENTITY
**QhPtrPtr
1563 Routine Description:
1565 Create Qh Structure and Pre-Initialize
1570 DeviceAddr - Address of Device
1571 Endpoint - Endpoint Number
1572 DeviceSpeed - Device Speed
1573 MaxPacketLen - Max Length of one Packet
1574 QhPtrPtr - A pointer of pointer to Qh for return
1579 EFI_DEVICE_ERROR Fail
1586 IN USB2_HC_DEV
*HcDev
,
1587 IN UINT8 DeviceAddr
,
1588 IN UINT8 DeviceSpeed
,
1589 IN UINTN MaxPacketLen
,
1590 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR
*Translator
,
1591 OUT EHCI_QH_ENTITY
**QhPtrPtr
1595 Routine Description:
1597 Create Qh for Control Transfer
1602 DeviceAddr - Address of Device
1603 DeviceSpeed - Device Speed
1604 MaxPacketLen - Max Length of one Packet
1605 Translator - Translator Transaction for SplitX
1606 QhPtrPtr - A pointer of pointer to Qh for return
1611 EFI_DEVICE_ERROR Fail
1618 IN USB2_HC_DEV
*HcDev
,
1619 IN UINT8 DeviceAddr
,
1620 IN UINT8 EndPointAddr
,
1621 IN UINT8 DeviceSpeed
,
1622 IN UINT8 DataToggle
,
1623 IN UINTN MaxPacketLen
,
1624 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR
*Translator
,
1625 OUT EHCI_QH_ENTITY
**QhPtrPtr
1629 Routine Description:
1631 Create Qh for Bulk Transfer
1636 DeviceAddr - Address of Device
1637 EndPointAddr - Address of Endpoint
1638 DeviceSpeed - Device Speed
1639 MaxPacketLen - Max Length of one Packet
1640 Translator - Translator Transaction for SplitX
1641 QhPtrPtr - A pointer of pointer to Qh for return
1646 EFI_DEVICE_ERROR Fail
1653 IN USB2_HC_DEV
*HcDev
,
1654 IN UINT8 DeviceAddr
,
1655 IN UINT8 EndPointAddr
,
1656 IN UINT8 DeviceSpeed
,
1657 IN UINT8 DataToggle
,
1658 IN UINTN MaxPacketLen
,
1660 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR
*Translator
,
1661 OUT EHCI_QH_ENTITY
**QhPtrPtr
1665 Routine Description:
1667 Create Qh for Control Transfer
1672 DeviceAddr - Address of Device
1673 EndPointAddr - Address of Endpoint
1674 DeviceSpeed - Device Speed
1675 MaxPacketLen - Max Length of one Packet
1676 Interval - value of interval
1677 Translator - Translator Transaction for SplitX
1678 QhPtrPtr - A pointer of pointer to Qh for return
1683 EFI_DEVICE_ERROR Fail
1690 IN USB2_HC_DEV
*HcDev
,
1691 IN EHCI_QH_ENTITY
*QhPtr
1695 Routine Description:
1697 Destory Qh Structure
1702 QhPtr - A pointer to Qh
1713 IN USB2_HC_DEV
*HcDev
,
1719 OUT EHCI_QTD_ENTITY
**QtdPtrPtr
1723 Routine Description:
1725 Create Qtd Structure and Pre-Initialize it
1730 DataPtr - A pointer to user data buffer to transfer
1731 DataLen - Length of user data to transfer
1732 PktId - Packet Identification of this Qtd
1733 Toggle - Data Toggle of this Qtd
1734 QtdStatus - Default value of status of this Qtd
1735 QtdPtrPtr - A pointer of pointer to Qtd for return
1740 EFI_OUT_OF_RESOURCES Cannot allocate resources
1747 IN USB2_HC_DEV
*HcDev
,
1748 IN UINT8
*DevReqPtr
,
1749 OUT EHCI_QTD_ENTITY
**QtdPtrPtr
1753 Routine Description:
1755 Create Qtd Structure for Setup
1760 DevReqPtr - A pointer to Device Request Data
1761 QtdPtrPtr - A pointer of pointer to Qtd for return
1766 EFI_OUT_OF_RESOURCES Cannot allocate resources
1773 IN USB2_HC_DEV
*HcDev
,
1778 OUT EHCI_QTD_ENTITY
**QtdPtrPtr
1782 Routine Description:
1784 Create Qtd Structure for data
1789 DataPtr - A pointer to user data buffer to transfer
1790 DataLen - Length of user data to transfer
1791 PktId - Packet Identification of this Qtd
1792 Toggle - Data Toggle of this Qtd
1793 QtdPtrPtr - A pointer of pointer to Qtd for return
1798 EFI_OUT_OF_RESOURCES Cannot allocate resources
1805 IN USB2_HC_DEV
*HcDev
,
1807 OUT EHCI_QTD_ENTITY
**QtdPtrPtr
1811 Routine Description:
1813 Create Qtd Structure for status
1818 PktId - Packet Identification of this Qtd
1819 QtdPtrPtr - A pointer of pointer to Qtd for return
1824 EFI_OUT_OF_RESOURCES Cannot allocate resources
1831 IN USB2_HC_DEV
*HcDev
,
1833 OUT EHCI_QTD_ENTITY
**QtdPtrPtr
1837 Routine Description:
1839 Create Qtd Structure for Alternative
1844 PktId - Packet Identification of this Qtd
1845 QtdPtrPtr - A pointer of pointer to Qtd for return
1850 EFI_OUT_OF_RESOURCES Cannot allocate resources
1857 IN USB2_HC_DEV
*HcDev
,
1859 IN UINT8
*RequestCursor
,
1860 IN UINT8
*DataCursor
,
1862 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR
*Translator
,
1863 OUT EHCI_QTD_ENTITY
**ControlQtdsHead
1867 Routine Description:
1869 Create Qtds list for Control Transfer
1874 DataPktId - Packet Identification of Data Qtds
1875 RequestCursor - A pointer to request structure buffer to transfer
1876 DataCursor - A pointer to user data buffer to transfer
1877 DataLen - Length of user data to transfer
1878 ControlQtdsHead - A pointer of pointer to first Qtd for control tranfer for return
1883 EFI_DEVICE_ERROR Fail
1889 CreateBulkOrInterruptQtds (
1890 IN USB2_HC_DEV
*HcDev
,
1892 IN UINT8
*DataCursor
,
1894 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR
*Translator
,
1895 OUT EHCI_QTD_ENTITY
**QtdsHead
1899 Routine Description:
1901 Create Qtds list for Bulk or Interrupt Transfer
1906 PktId - Packet Identification of Qtds
1907 DataCursor - A pointer to user data buffer to transfer
1908 DataLen - Length of user data to transfer
1909 DataToggle - Data Toggle to start
1910 Translator - Translator Transaction for SplitX
1911 QtdsHead - A pointer of pointer to first Qtd for control tranfer for return
1916 EFI_DEVICE_ERROR Fail
1923 IN USB2_HC_DEV
*HcDev
,
1924 IN EHCI_QTD_ENTITY
*FirstQtdPtr
1928 Routine Description:
1930 Destory all Qtds in the list
1935 FirstQtdPtr - A pointer to first Qtd in the list
1946 IN EHCI_QTD_ENTITY
*PreQtdPtr
,
1947 IN EHCI_QTD_ENTITY
*QtdPtr
1951 Routine Description:
1957 PreQtdPtr - A pointer to pre Qtd
1958 QtdPtr - A pointer to next Qtd
1969 IN EHCI_QTD_ENTITY
*FirstQtdPtr
,
1970 IN EHCI_QTD_ENTITY
*AltQtdPtr
1974 Routine Description:
1976 Link AlterQtds together
1980 FirstQtdPtr - A pointer to first Qtd in the list
1981 AltQtdPtr - A pointer to alternative Qtd
1991 IN EHCI_QH_ENTITY
*QhPtr
,
1992 IN EHCI_QTD_ENTITY
*QtdEntryPtr
1996 Routine Description:
1998 Link Qtds list to Qh
2002 QhPtr - A pointer to Qh
2003 QtdPtr - A pointer to first Qtd in the list
2014 IN USB2_HC_DEV
*HcDev
,
2015 IN EHCI_QH_ENTITY
*QhPtr
2019 Routine Description:
2021 Link Qh to Async Schedule List
2026 QhPtr - A pointer to Qh
2031 EFI_DEVICE_ERROR Fail
2037 UnlinkQhFromAsyncList (
2038 IN USB2_HC_DEV
*HcDev
,
2039 IN EHCI_QH_ENTITY
*QhPtr
2043 Routine Description:
2045 Unlink Qh from Async Schedule List
2050 QhPtr - A pointer to Qh
2055 EFI_DEVICE_ERROR Fail
2061 LinkQhToPeriodicList (
2062 IN USB2_HC_DEV
*HcDev
,
2063 IN EHCI_QH_ENTITY
*QhPtr
2067 Routine Description:
2069 Link Qh to Periodic Schedule List
2074 QhPtr - A pointer to Qh
2084 UnlinkQhFromPeriodicList (
2085 IN USB2_HC_DEV
*HcDev
,
2086 IN EHCI_QH_ENTITY
*QhPtr
,
2091 Routine Description:
2093 Unlink Qh from Periodic Schedule List
2098 QhPtr - A pointer to Qh
2099 Interval - Interval of this periodic transfer
2109 LinkToAsyncReqeust (
2110 IN USB2_HC_DEV
*HcDev
,
2111 IN EHCI_ASYNC_REQUEST
*AsyncRequestPtr
2115 Routine Description:
2117 Llink AsyncRequest Entry to Async Request List
2122 AsyncRequestPtr - A pointer to Async Request Entry
2132 UnlinkFromAsyncReqeust (
2133 IN USB2_HC_DEV
*HcDev
,
2134 IN EHCI_ASYNC_REQUEST
*AsyncRequestPtr
2138 Routine Description:
2140 Unlink AsyncRequest Entry from Async Request List
2145 AsyncRequestPtr - A pointer to Async Request Entry
2156 IN EHCI_QTD_ENTITY
*FirstQtdPtr
2160 Routine Description:
2162 Number of Qtds in the list
2166 FirstQtdPtr - A pointer to first Qtd in the list
2170 Number of Qtds in the list
2176 GetNumberOfTransaction (
2177 IN UINTN SizeOfData
,
2178 IN UINTN SizeOfTransaction
2182 Routine Description:
2184 Number of Transactions in one Qtd
2188 SizeOfData - Size of one Qtd
2189 SizeOfTransaction - Size of one Transaction
2193 Number of Transactions in this Qtd
2200 IN UINT8
*BufferCursor
2204 Routine Description:
2210 BufferCursor - BufferCursor of the Qtd
2220 GetApproxiOfInterval (
2225 Routine Description:
2227 Get the approximate value in the 2 index sequence
2231 Interval - the value of interval
2235 approximate value of interval in the 2 index sequence
2242 IN EHCI_QTD_HW
*HwQtdPtr
2246 Routine Description:
2248 Get Qtd next pointer field
2252 HwQtdPtr - A pointer to hardware Qtd structure
2256 A pointer to next hardware Qtd structure
2263 IN EHCI_QTD_HW
*HwQtdPtr
2267 Routine Description:
2269 Whether Qtd status is active or not
2273 HwQtdPtr - A pointer to hardware Qtd structure
2285 IN EHCI_QTD_HW
*HwQtdPtr
2289 Routine Description:
2291 Whether Qtd status is halted or not
2295 HwQtdPtr - A pointer to hardware Qtd structure
2306 IsQtdStatusBufferError (
2307 IN EHCI_QTD_HW
*HwQtdPtr
2311 Routine Description:
2313 Whether Qtd status is buffer error or not
2317 HwQtdPtr - A pointer to hardware Qtd structure
2322 FALSE No buffer error
2328 IsQtdStatusBabbleError (
2329 IN EHCI_QTD_HW
*HwQtdPtr
2333 Routine Description:
2335 Whether Qtd status is babble error or not
2339 HwQtdPtr - A pointer to hardware Qtd structure
2344 FALSE No babble error
2350 IsQtdStatusTransactionError (
2351 IN EHCI_QTD_HW
*HwQtdPtr
2355 Routine Description:
2357 Whether Qtd status is transaction error or not
2361 HwQtdPtr - A pointer to hardware Qtd structure
2365 TRUE Transaction error
2366 FALSE No transaction error
2373 IN UINT8 EndPointAddress
2377 Routine Description:
2379 Whether is a DataIn direction transfer
2383 EndPointAddress - address of the endpoint
2395 IN USB2_HC_DEV
*HcDev
,
2396 IN EFI_USB_DATA_DIRECTION TransferDirection
,
2398 IN OUT UINTN
*DataLength
,
2400 OUT UINT8
**DataCursor
,
2405 Routine Description:
2407 Map address of user data buffer
2412 TransferDirection - direction of transfer
2413 Data - A pointer to user data buffer
2414 DataLength - length of user data
2415 PktId - Packte Identificaion
2416 DataCursor - mapped address to return
2417 DataMap - identificaion of this mapping to return
2422 EFI_DEVICE_ERROR Fail
2429 IN USB2_HC_DEV
*HcDev
,
2430 IN OUT VOID
*Request
,
2431 OUT UINT8
**RequestCursor
,
2432 OUT VOID
**RequestMap
2436 Routine Description:
2438 Map address of request structure buffer
2443 Request - A pointer to request structure
2444 RequestCursor - Mapped address of request structure to return
2445 RequestMap - Identificaion of this mapping to return
2450 EFI_DEVICE_ERROR Fail
2456 SetQtdBufferPointer (
2457 IN EHCI_QTD_HW
*QtdHwPtr
,
2463 Routine Description:
2465 Set data buffer pointers in Qtd
2469 QtdHwPtr - A pointer to Qtd hardware structure
2470 DataPtr - A pointer to user data buffer
2471 DataLen - Length of the user data buffer
2481 GetQtdAlternateNextPointer (
2482 IN EHCI_QTD_HW
*HwQtdPtr
2486 Routine Description:
2488 Get Qtd alternate next pointer field
2492 HwQtdPtr - A pointer to hardware Qtd structure
2496 A pointer to hardware alternate Qtd
2503 IN EHCI_QH_ENTITY
*QhPtr
2507 Routine Description:
2509 Zero out the fields in Qh structure
2513 QhPtr - A pointer to Qh structure
2523 UpdateAsyncRequestTransfer (
2524 IN EHCI_ASYNC_REQUEST
*AsyncRequestPtr
,
2525 IN UINT32 TransferResult
,
2530 Routine Description:
2532 Update asynchronous request transfer
2536 AsyncRequestPtr - A pointer to async request
2537 TransferResult - transfer result
2538 ErrQtdPos - postion of error Qtd
2549 DeleteAsyncRequestTransfer (
2550 IN USB2_HC_DEV
*HcDev
,
2551 IN UINT8 DeviceAddress
,
2552 IN UINT8 EndPointAddress
,
2553 OUT UINT8
*DataToggle
2557 Routine Description:
2559 Delete all asynchronous request transfer
2564 DeviceAddress - address of usb device
2565 EndPointAddress - address of endpoint
2566 DataToggle - stored data toggle
2571 EFI_DEVICE_ERROR Fail
2577 CleanUpAllAsyncRequestTransfer (
2578 IN USB2_HC_DEV
*HcDev
2582 Routine Description:
2584 Clean up all asynchronous request transfer
2598 IN USB2_HC_DEV
*HcDev
,
2599 IN BOOLEAN IsControl
,
2600 IN EHCI_QH_ENTITY
*QhPtr
,
2601 IN OUT UINTN
*ActualLen
,
2602 OUT UINT8
*DataToggle
,
2604 OUT UINT32
*TransferResult
2608 Routine Description:
2610 Execute Bulk or SyncInterrupt Transfer
2615 IsControl - Is control transfer or not
2616 QhPtr - A pointer to Qh
2617 ActualLen - Actual transfered Len
2618 DataToggle - Data Toggle
2619 TimeOut - TimeOut threshold
2620 TransferResult - Transfer result
2625 EFI_DEVICE_ERROR Error
2631 CheckQtdsTransferResult (
2632 IN BOOLEAN IsControl
,
2633 IN EHCI_QH_ENTITY
*QhPtr
,
2635 OUT UINTN
*ErrQtdPos
,
2636 OUT UINTN
*ActualLen
2640 Routine Description:
2642 Check transfer result of Qtds
2646 IsControl - Is control transfer or not
2647 QhPtr - A pointer to Qh
2648 Result - Transfer result
2649 ErrQtdPos - Error TD Position
2650 ActualLen - Actual Transfer Size
2661 AsyncRequestMoniter (
2667 Routine Description:
2669 Interrupt transfer periodic check handler
2673 Event - Interrupt event
2674 Context - Pointer to USB2_HC_DEV
2679 EFI_DEVICE_ERROR Fail