3 Copyright (c) 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
26 // Universal Host Controller Interface data structures and defines
28 #include <IndustryStandard/pci22.h>
30 extern UINTN gEHCDebugLevel
;
31 extern UINTN gEHCErrorLevel
;
33 #define STALL_1_MACRO_SECOND 1
34 #define STALL_1_MILLI_SECOND 1000 * STALL_1_MACRO_SECOND
35 #define STALL_1_SECOND 1000 * STALL_1_MILLI_SECOND
37 #define SETUP_PACKET_PID_CODE 0x02
38 #define INPUT_PACKET_PID_CODE 0x01
39 #define OUTPUT_PACKET_PID_CODE 0x0
41 #define ITD_SELECT_TYPE 0x0
42 #define QH_SELECT_TYPE 0x01
43 #define SITD_SELECT_TYPE 0x02
44 #define FSTN_SELECT_TYPE 0x03
46 #define EHCI_SET_PORT_RESET_RECOVERY_TIME 50 * STALL_1_MILLI_SECOND
47 #define EHCI_CLEAR_PORT_RESET_RECOVERY_TIME STALL_1_MILLI_SECOND
48 #define EHCI_GENERIC_TIMEOUT 50 * STALL_1_MILLI_SECOND
49 #define EHCI_GENERIC_RECOVERY_TIME 50 * STALL_1_MACRO_SECOND
50 #define EHCI_SYNC_REQUEST_POLLING_TIME 50 * STALL_1_MACRO_SECOND
51 #define EHCI_ASYNC_REQUEST_POLLING_TIME 50 * STALL_1_MILLI_SECOND
53 #define USB_BAR_INDEX 0 /* how many bytes away from USB_BASE to 0x10 */
55 #define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 1
57 #define EHCI_MIN_PACKET_SIZE 8
58 #define EHCI_MAX_PACKET_SIZE 1024
59 #define EHCI_MAX_FRAME_LIST_LENGTH 1024
60 #define EHCI_BLOCK_SIZE_WITH_TT 64
61 #define EHCI_BLOCK_SIZE 512
62 #define EHCI_MAX_QTD_CAPACITY (EFI_PAGE_SIZE * 5)
64 #define NAK_COUNT_RELOAD 3
65 #define QTD_ERROR_COUNTER 1
66 #define HIGH_BANDWIDTH_PIPE_MULTIPLIER 1
68 #define QTD_STATUS_ACTIVE 0x80
69 #define QTD_STATUS_HALTED 0x40
70 #define QTD_STATUS_BUFFER_ERR 0x20
71 #define QTD_STATUS_BABBLE_ERR 0x10
72 #define QTD_STATUS_TRANSACTION_ERR 0x08
73 #define QTD_STATUS_DO_STOP_SPLIT 0x02
74 #define QTD_STATUS_DO_START_SPLIT 0
75 #define QTD_STATUS_DO_PING 0x01
76 #define QTD_STATUS_DO_OUT 0
81 #define MICRO_FRAME_0_CHANNEL 0x01
82 #define MICRO_FRAME_1_CHANNEL 0x02
83 #define MICRO_FRAME_2_CHANNEL 0x04
84 #define MICRO_FRAME_3_CHANNEL 0x08
85 #define MICRO_FRAME_4_CHANNEL 0x10
86 #define MICRO_FRAME_5_CHANNEL 0x20
87 #define MICRO_FRAME_6_CHANNEL 0x40
88 #define MICRO_FRAME_7_CHANNEL 0x80
90 #define CONTROL_TRANSFER 0x01
91 #define BULK_TRANSFER 0x02
92 #define SYNC_INTERRUPT_TRANSFER 0x04
93 #define ASYNC_INTERRUPT_TRANSFER 0x08
94 #define SYNC_ISOCHRONOUS_TRANSFER 0x10
95 #define ASYNC_ISOCHRONOUS_TRANSFER 0x20
99 // Enhanced Host Controller Registers definitions
101 extern UINT32 mUsbCapabilityLen
;
102 extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding
;
103 extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName
;
105 #define USBCMD 0x0 /* Command Register Offset 00-03h */
106 #define USBCMD_RS 0x01 /* Run / Stop */
107 #define USBCMD_HCRESET 0x02 /* Host controller reset */
108 #define USBCMD_FLS_512 0x04 /* 512 elements (2048bytes) in Frame List */
109 #define USBCMD_FLS_256 0x08 /* 256 elements (1024bytes) in Frame List */
110 #define USBCMD_PSE 0x10 /* Periodic schedule enable */
111 #define USBCMD_ASE 0x20 /* Asynchronous schedule enable */
112 #define USBCMD_IAAD 0x40 /* Interrupt on async advance doorbell */
114 #define USBSTS 0x04 /* Statue Register Offset 04-07h */
115 #define USBSTS_HSE 0x10 /* Host system error */
116 #define USBSTS_IAA 0x20 /* Interrupt on async advance */
117 #define USBSTS_HCH 0x1000 /* Host controller halted */
118 #define USBSTS_PSS 0x4000 /* Periodic schedule status */
119 #define USBSTS_ASS 0x8000 /* Asynchronous schedule status */
121 #define USBINTR 0x08 /* Command Register Offset 08-0bh */
123 #define FRINDEX 0x0c /* Frame Index Offset 0c-0fh */
125 #define CTRLDSSGMENT 0x10 /* 4G Segment Selector Offset 10-13h */
127 #define PERIODICLISTBASE 0x14 /* Frame List Base Address Offset 14-17h */
129 #define ASYNCLISTADDR 0x18 /* Next Asynchronous List Address Offset 18-1bh */
131 #define CONFIGFLAG 0x40 /* Configured Flag Register Offset 40-43h */
132 #define CONFIGFLAG_CF 0x01 /* Configure Flag */
134 #define PORTSC 0x44 /* Port Status/Control Offset 44-47h */
135 #define PORTSC_CCS 0x01 /* Current Connect Status*/
136 #define PORTSC_CSC 0x02 /* Connect Status Change */
137 #define PORTSC_PED 0x04 /* Port Enable / Disable */
138 #define PORTSC_PEDC 0x08 /* Port Enable / Disable Change */
139 #define PORTSC_OCA 0x10 /* Over current Active */
140 #define PORTSC_OCC 0x20 /* Over current Change */
141 #define PORTSC_FPR 0x40 /* Force Port Resume */
142 #define PORTSC_SUSP 0x80 /* Port Suspend State */
143 #define PORTSC_PR 0x100 /* Port Reset */
144 #define PORTSC_LS_KSTATE 0x400 /* Line Status K-state */
145 #define PORTSC_LS_JSTATE 0x800 /* Line Status J-state */
146 #define PORTSC_PP 0x1000 /* Port Power */
147 #define PORTSC_PO 0x2000 /* Port Owner */
149 #define CAPLENGTH 0 /* Capability Register Length 00h */
151 #define HCIVERSION 0x02 /* Interface Version Number 02-03h */
153 #define HCSPARAMS 0x04 /* Structural Parameters 04-07h */
154 #define HCSP_NPORTS 0x0f /* Number of physical downstream ports on host controller */
156 #define HCCPARAMS 0x08 /* Capability Parameters 08-0bh */
157 #define HCCP_64BIT 0x01 /* 64-bit Addressing Capability */
158 #define HCCP_PFLF 0x02 /* Programmable Frame List Flag */
159 #define HCCP_EECP 0xff00 /* EHCI Extemded Capabilities Pointer */
161 #define HCSPPORTROUTE 0x0c /* Companion Port Route Description 60b */
163 #define CLASSC 0x09 /* Class Code 09-0bh */
165 #define USBBASE 0x10 /* Base Address to Memory-mapped Host Controller Register Space 10-13h */
167 #define SBRN 0x60 /* Serial Bus Release Number 60h */
169 #define FLADJ 0x61 /* Frame Length Adjustment Register 61h */
171 #define PORTWAKECAP 0x62 /* Port wake capablilities register(OPIONAL) 61-62h */
174 // PCI Configuration Registers
176 #define EHCI_PCI_CLASSC 0x09
177 #define EHCI_PCI_MEMORY_BASE 0x10
180 // Memory Offset Registers
182 #define EHCI_MEMORY_CAPLENGTH 0x0
183 #define EHCI_MEMORY_CONFIGFLAG 0x40
186 // USB Base Class Code,Sub-Class Code and Programming Interface
188 #define PCI_CLASSC_PI_EHCI 0x20
190 #define SETUP_PACKET_ID 0x2D
191 #define INPUT_PACKET_ID 0x69
192 #define OUTPUT_PACKET_ID 0xE1
193 #define ERROR_PACKET_ID 0x55
195 #define bit(a) 1 << (a)
197 #define GET_0B_TO_31B(Addr) (UINT32) (UINTN) (Addr)
198 #define GET_32B_TO_63B(Addr) (UINT32) (RShiftU64(((UINT64) (UINTN) (Addr)), 32) & 0xffffffff)
201 // Ehci Data and Ctrl Structures
212 UINT32 NextQtdTerminate
: 1;
214 UINT32 NextQtdPointer
: 27;
216 UINT32 AltNextQtdTerminate
: 1;
218 UINT32 AltNextQtdPointer
: 27;
222 UINT32 ErrorCount
: 2;
223 UINT32 CurrentPage
: 3;
224 UINT32 InterruptOnComplete
: 1;
225 UINT32 TotalBytes
: 15;
226 UINT32 DataToggle
: 1;
228 UINT32 CurrentOffset
: 12;
229 UINT32 BufferPointer0
: 20;
232 UINT32 BufferPointer1
: 20;
235 UINT32 BufferPointer2
: 20;
238 UINT32 BufferPointer3
: 20;
241 UINT32 BufferPointer4
: 20;
243 UINT32 ExtBufferPointer0
;
244 UINT32 ExtBufferPointer1
;
245 UINT32 ExtBufferPointer2
;
246 UINT32 ExtBufferPointer3
;
247 UINT32 ExtBufferPointer4
;
251 UINT32 QhTerminate
: 1;
252 UINT32 SelectType
: 2;
254 UINT32 QhHorizontalPointer
: 27;
256 UINT32 DeviceAddr
: 7;
258 UINT32 EndpointNum
: 4;
259 UINT32 EndpointSpeed
: 2;
260 UINT32 DataToggleControl
: 1;
261 UINT32 HeadReclamationFlag
: 1;
262 UINT32 MaxPacketLen
: 11;
263 UINT32 ControlEndpointFlag
: 1;
264 UINT32 NakCountReload
: 4;
266 UINT32 InerruptScheduleMask
: 8;
267 UINT32 SplitComletionMask
: 8;
270 UINT32 Multiplier
: 2;
273 UINT32 CurrentQtdPointer
: 27;
275 UINT32 NextQtdTerminate
: 1;
277 UINT32 NextQtdPointer
: 27;
279 UINT32 AltNextQtdTerminate
: 1;
281 UINT32 AltNextQtdPointer
: 27;
285 UINT32 ErrorCount
: 2;
286 UINT32 CurrentPage
: 3;
287 UINT32 InterruptOnComplete
: 1;
288 UINT32 TotalBytes
: 15;
289 UINT32 DataToggle
: 1;
291 UINT32 CurrentOffset
: 12;
292 UINT32 BufferPointer0
: 20;
294 UINT32 CompleteSplitMask
: 8;
296 UINT32 BufferPointer1
: 20;
299 UINT32 SplitBytes
: 7;
300 UINT32 BufferPointer2
: 20;
303 UINT32 BufferPointer3
: 20;
306 UINT32 BufferPointer4
: 20;
308 UINT32 ExtBufferPointer0
;
309 UINT32 ExtBufferPointer1
;
310 UINT32 ExtBufferPointer2
;
311 UINT32 ExtBufferPointer3
;
312 UINT32 ExtBufferPointer4
;
316 UINT32 LinkTerminate
: 1;
317 UINT32 SelectType
: 2;
319 UINT32 LinkPointer
: 27;
324 typedef struct _EHCI_QTD_ENTITY EHCI_QTD_ENTITY
;
325 typedef struct _EHCI_QH_ENTITY EHCI_QH_ENTITY
;
326 typedef struct _EHCI_ASYNC_REQUEST EHCI_ASYNC_REQUEST
;
328 struct _EHCI_QTD_ENTITY
{
331 UINT32 StaticTotalBytes
;
332 UINT32 StaticCurrentOffset
;
333 EHCI_QTD_ENTITY
*Prev
;
334 EHCI_QTD_ENTITY
*Next
;
335 EHCI_QTD_ENTITY
*AltNext
;
336 EHCI_QH_ENTITY
*SelfQh
;
339 struct _EHCI_QH_ENTITY
{
341 EHCI_QH_ENTITY
*Next
;
342 EHCI_QH_ENTITY
*Prev
;
343 EHCI_QTD_ENTITY
*FirstQtdPtr
;
344 EHCI_QTD_ENTITY
*LastQtdPtr
;
345 EHCI_QTD_ENTITY
*AltQtdPtr
;
350 #define GET_QH_ENTITY_ADDR(a) ((EHCI_QH_ENTITY *) a)
351 #define GET_QTD_ENTITY_ADDR(a) ((EHCI_QTD_ENTITY *) a)
355 // Ehci Managment Structures
357 #define USB2_HC_DEV_FROM_THIS(a) CR (a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)
359 #define USB2_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('e', 'h', 'c', 'i')
361 struct _EHCI_ASYNC_REQUEST
{
363 EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunc
;
365 EHCI_ASYNC_REQUEST
*Prev
;
366 EHCI_ASYNC_REQUEST
*Next
;
367 EHCI_QH_ENTITY
*QhPtr
;
370 typedef struct _MEMORY_MANAGE_HEADER
{
372 UINTN BitArraySizeInBytes
;
373 UINT8
*MemoryBlockPtr
;
374 UINTN MemoryBlockSizeInBytes
;
376 struct _MEMORY_MANAGE_HEADER
*Next
;
377 } MEMORY_MANAGE_HEADER
;
379 typedef struct _USB2_HC_DEV
{
381 EFI_PCI_IO_PROTOCOL
*PciIo
;
382 EFI_USB2_HC_PROTOCOL Usb2Hc
;
383 UINTN PeriodicFrameListLength
;
384 VOID
*PeriodicFrameListBuffer
;
385 VOID
*PeriodicFrameListMap
;
387 EHCI_ASYNC_REQUEST
*AsyncRequestList
;
388 EFI_EVENT AsyncRequestEvent
;
389 EFI_UNICODE_STRING_TABLE
*ControllerNameTable
;
390 MEMORY_MANAGE_HEADER
*MemoryHeader
;
391 UINT8 Is64BitCapable
;
392 UINT32 High32BitAddr
;
397 // Internal Functions Declaration
405 IN USB2_HC_DEV
*HcDev
,
406 OUT MEMORY_MANAGE_HEADER
**MemoryHeader
,
407 IN UINTN MemoryBlockSizeInPages
413 Use PciIo->AllocateBuffer to allocate common buffer for the memory block,
414 and use PciIo->Map to map the common buffer for Bus Master Read/Write.
419 MemoryHeader - MEMORY_MANAGE_HEADER to output
420 MemoryBlockSizeInPages - MemoryBlockSizeInPages
425 EFI_OUT_OF_RESOURCES Fail for no resources
426 EFI_UNSUPPORTED Unsupported currently
433 IN USB2_HC_DEV
*HcDev
,
434 IN MEMORY_MANAGE_HEADER
*MemoryHeader
445 MemoryHeader - MemoryHeader to be freed
450 EFI_INVALID_PARAMETER Parameter is error
456 InsertMemoryHeaderToList (
457 IN MEMORY_MANAGE_HEADER
*MemoryHeader
,
458 IN MEMORY_MANAGE_HEADER
*NewMemoryHeader
464 Insert Memory Header To List
468 MemoryHeader - MEMORY_MANAGE_HEADER
469 NewMemoryHeader - MEMORY_MANAGE_HEADER
479 AllocMemInMemoryBlock (
480 IN MEMORY_MANAGE_HEADER
*MemoryHeader
,
482 IN UINTN NumberOfMemoryUnit
488 Alloc Memory In MemoryBlock
492 MemoryHeader - MEMORY_MANAGE_HEADER
493 Pool - Place to store pointer to memory
494 NumberOfMemoryUnit - Number Of Memory Unit
499 EFI_NOT_FOUND Can't find the free memory
505 IsMemoryBlockEmptied (
506 IN MEMORY_MANAGE_HEADER
*MemoryHeaderPtr
512 Is Memory Block Emptied
516 MemoryHeaderPtr - MEMORY_MANAGE_HEADER
528 IN MEMORY_MANAGE_HEADER
*FirstMemoryHeader
,
529 IN MEMORY_MANAGE_HEADER
*NeedFreeMemoryHeader
539 FirstMemoryHeader - MEMORY_MANAGE_HEADER
540 NeedFreeMemoryHeader - MEMORY_MANAGE_HEADER
550 InitialMemoryManagement (
551 IN USB2_HC_DEV
*HcDev
557 Initialize Memory Management
566 EFI_DEVICE_ERROR Fail
572 DeinitialMemoryManagement (
573 IN USB2_HC_DEV
*HcDev
579 Deinitialize Memory Management
588 EFI_DEVICE_ERROR Fail
595 IN USB2_HC_DEV
*HcDev
,
608 Pool - Place to store pointer to the memory buffer
609 AllocSize - Alloc Size
614 EFI_DEVICE_ERROR Fail
621 IN USB2_HC_DEV
*HcDev
,
635 AllocSize - Pool size
648 ReadEhcCapabiltiyReg (
649 IN USB2_HC_DEV
*HcDev
,
650 IN UINT32 CapabiltiyRegAddr
,
657 Read Ehc Capabitlity register
662 CapabiltiyRegAddr - Ehc Capability register address
663 Data - A pointer to data read from register
668 EFI_DEVICE_ERROR Fail
674 ReadEhcOperationalReg (
675 IN USB2_HC_DEV
*HcDev
,
676 IN UINT32 OperationalRegAddr
,
683 Read Ehc Operation register
688 OperationalRegAddr - Ehc Operation register address
689 Data - A pointer to data read from register
694 EFI_DEVICE_ERROR Fail
700 WriteEhcOperationalReg (
701 IN USB2_HC_DEV
*HcDev
,
702 IN UINT32 OperationalRegAddr
,
709 Write Ehc Operation register
714 OperationalRegAddr - Ehc Operation register address
715 Data - 32bit write to register
720 EFI_DEVICE_ERROR Fail
727 IN USB2_HC_DEV
*HcDev
733 Set Ehc door bell bit
742 EFI_DEVICE_ERROR Fail
749 IN USB2_HC_DEV
*HcDev
,
756 Set the length of Frame List
761 Length - the required length of frame list
766 EFI_INVALID_PARAMETER Invalid parameter
767 EFI_DEVICE_ERROR Fail
773 IsFrameListProgrammable (
774 IN USB2_HC_DEV
*HcDev
780 Whether frame list is programmable
795 IsPeriodicScheduleEnabled (
796 IN USB2_HC_DEV
*HcDev
802 Whether periodic schedule is enabled
817 IsAsyncScheduleEnabled (
818 IN USB2_HC_DEV
*HcDev
824 Whether asynchronous schedule is enabled
840 IN USB2_HC_DEV
*HcDev
,
847 Whether port is enabled
863 IN USB2_HC_DEV
*HcDev
869 Whether Ehc is halted
885 IN USB2_HC_DEV
*HcDev
891 Whether Ehc is halted
907 IN USB2_HC_DEV
*HcDev
913 Whether Ehc is system error
922 FALSE No system error
929 IN EFI_USB2_HC_PROTOCOL
*This
,
936 Whether high speed device attached
952 IN USB2_HC_DEV
*HcDev
,
959 wait for Ehc reset or timeout
964 Timeout - timeout threshold
976 IN USB2_HC_DEV
*HcDev
,
983 wait for Ehc halt or timeout
988 Timeout - timeout threshold
1000 IN USB2_HC_DEV
*HcDev
,
1005 Routine Description:
1007 wait for Ehc not halt or timeout
1012 Timeout - timeout threshold
1023 WaitForEhcDoorbell (
1024 IN USB2_HC_DEV
*HcDev
,
1029 Routine Description:
1031 Wait for periodic schedule disable or timeout
1036 Timeout - timeout threshold
1047 WaitForAsyncScheduleEnable (
1048 IN USB2_HC_DEV
*HcDev
,
1053 Routine Description:
1055 Wait for Ehc asynchronous schedule enable or timeout
1060 Timeout - timeout threshold
1071 WaitForAsyncScheduleDisable (
1072 IN USB2_HC_DEV
*HcDev
,
1077 Routine Description:
1079 Wait for Ehc asynchronous schedule disable or timeout
1084 Timeout - timeout threshold
1095 WaitForPeriodicScheduleEnable (
1096 IN USB2_HC_DEV
*HcDev
,
1101 Routine Description:
1103 Wait for Ehc periodic schedule enable or timeout
1108 Timeout - timeout threshold
1119 WaitForPeriodicScheduleDisable (
1120 IN USB2_HC_DEV
*HcDev
,
1125 Routine Description:
1127 Wait for periodic schedule disable or timeout
1132 Timeout - timeout threshold
1144 IN USB2_HC_DEV
*HcDev
1148 Routine Description:
1150 Get the length of capability register
1159 EFI_DEVICE_ERROR Fail
1165 SetFrameListBaseAddr (
1166 IN USB2_HC_DEV
*HcDev
,
1167 IN UINT32 FrameBuffer
1171 Routine Description:
1173 Set base address of frame list first entry
1178 FrameBuffer - base address of first entry of frame list
1183 EFI_DEVICE_ERROR Fail
1190 IN USB2_HC_DEV
*HcDev
,
1191 IN EHCI_QH_ENTITY
*QhPtr
1195 Routine Description:
1197 Set address of first Async schedule Qh
1202 QhPtr - A pointer to first Qh in the Async schedule
1207 EFI_DEVICE_ERROR Fail
1213 SetCtrlDataStructSeg (
1214 IN USB2_HC_DEV
*HcDev
1218 Routine Description:
1220 Set address of first Async schedule Qh
1225 QhPtr - A pointer to first Qh in the Async schedule
1230 EFI_DEVICE_ERROR Fail
1237 IN USB2_HC_DEV
*HcDev
1241 Routine Description:
1243 Set Ehc port routing bit
1252 EFI_DEVICE_ERROR Fail
1258 EnablePeriodicSchedule (
1259 IN USB2_HC_DEV
*HcDev
1263 Routine Description:
1265 Enable periodic schedule
1274 EFI_DEVICE_ERROR Fail
1280 DisablePeriodicSchedule (
1281 IN USB2_HC_DEV
*HcDev
1285 Routine Description:
1287 Disable periodic schedule
1296 EFI_DEVICE_ERROR Fail
1302 EnableAsynchronousSchedule (
1303 IN USB2_HC_DEV
*HcDev
1307 Routine Description:
1309 Enable asynchrounous schedule
1318 EFI_DEVICE_ERROR Fail
1324 DisableAsynchronousSchedule (
1325 IN USB2_HC_DEV
*HcDev
1329 Routine Description:
1331 Disable asynchrounous schedule
1340 EFI_DEVICE_ERROR Fail
1346 StartScheduleExecution (
1347 IN USB2_HC_DEV
*HcDev
1351 Routine Description:
1353 Start Ehc schedule execution
1362 EFI_DEVICE_ERROR Fail
1369 IN USB2_HC_DEV
*HcDev
1373 Routine Description:
1384 EFI_DEVICE_ERROR Fail
1391 IN USB2_HC_DEV
*HcDev
1395 Routine Description:
1397 Clear Ehc all status bits
1406 EFI_DEVICE_ERROR Fail
1412 // EhciSched Functions
1415 InitialPeriodicFrameList (
1416 IN USB2_HC_DEV
*HcDev
,
1421 Routine Description:
1423 Initialize Periodic Schedule Frame List
1428 Length - Frame List Length
1433 EFI_DEVICE_ERROR Fail
1439 DeinitialPeriodicFrameList (
1440 IN USB2_HC_DEV
*HcDev
1444 Routine Description:
1446 Deinitialize Periodic Schedule Frame List
1460 CreatePollingTimer (
1461 IN USB2_HC_DEV
*HcDev
,
1462 IN EFI_EVENT_NOTIFY NotifyFunction
1466 Routine Description:
1468 Create Async Request Polling Timer
1473 NotifyFunction - Timer Notify Function
1478 EFI_DEVICE_ERROR Fail
1484 DestoryPollingTimer (
1485 IN USB2_HC_DEV
*HcDev
1489 Routine Description:
1491 Destory Async Request Polling Timer
1500 EFI_DEVICE_ERROR Fail
1507 IN USB2_HC_DEV
*HcDev
1511 Routine Description:
1513 Start Async Request Polling Timer
1522 EFI_DEVICE_ERROR Fail
1529 IN USB2_HC_DEV
*HcDev
1533 Routine Description:
1535 Stop Async Request Polling Timer
1544 EFI_DEVICE_ERROR Fail
1551 IN USB2_HC_DEV
*HcDev
,
1552 IN UINT8 DeviceAddr
,
1554 IN UINT8 DeviceSpeed
,
1555 IN UINTN MaxPacketLen
,
1556 OUT EHCI_QH_ENTITY
**QhPtrPtr
1560 Routine Description:
1562 Create Qh Structure and Pre-Initialize
1567 DeviceAddr - Address of Device
1568 Endpoint - Endpoint Number
1569 DeviceSpeed - Device Speed
1570 MaxPacketLen - Max Length of one Packet
1571 QhPtrPtr - A pointer of pointer to Qh for return
1576 EFI_DEVICE_ERROR Fail
1583 IN USB2_HC_DEV
*HcDev
,
1584 IN UINT8 DeviceAddr
,
1585 IN UINT8 DeviceSpeed
,
1586 IN UINTN MaxPacketLen
,
1587 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR
*Translator
,
1588 OUT EHCI_QH_ENTITY
**QhPtrPtr
1592 Routine Description:
1594 Create Qh for Control Transfer
1599 DeviceAddr - Address of Device
1600 DeviceSpeed - Device Speed
1601 MaxPacketLen - Max Length of one Packet
1602 Translator - Translator Transaction for SplitX
1603 QhPtrPtr - A pointer of pointer to Qh for return
1608 EFI_DEVICE_ERROR Fail
1615 IN USB2_HC_DEV
*HcDev
,
1616 IN UINT8 DeviceAddr
,
1617 IN UINT8 EndPointAddr
,
1618 IN UINT8 DeviceSpeed
,
1619 IN UINT8 DataToggle
,
1620 IN UINTN MaxPacketLen
,
1621 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR
*Translator
,
1622 OUT EHCI_QH_ENTITY
**QhPtrPtr
1626 Routine Description:
1628 Create Qh for Bulk Transfer
1633 DeviceAddr - Address of Device
1634 EndPointAddr - Address of Endpoint
1635 DeviceSpeed - Device Speed
1636 MaxPacketLen - Max Length of one Packet
1637 Translator - Translator Transaction for SplitX
1638 QhPtrPtr - A pointer of pointer to Qh for return
1643 EFI_DEVICE_ERROR Fail
1650 IN USB2_HC_DEV
*HcDev
,
1651 IN UINT8 DeviceAddr
,
1652 IN UINT8 EndPointAddr
,
1653 IN UINT8 DeviceSpeed
,
1654 IN UINT8 DataToggle
,
1655 IN UINTN MaxPacketLen
,
1657 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR
*Translator
,
1658 OUT EHCI_QH_ENTITY
**QhPtrPtr
1662 Routine Description:
1664 Create Qh for Control Transfer
1669 DeviceAddr - Address of Device
1670 EndPointAddr - Address of Endpoint
1671 DeviceSpeed - Device Speed
1672 MaxPacketLen - Max Length of one Packet
1673 Interval - value of interval
1674 Translator - Translator Transaction for SplitX
1675 QhPtrPtr - A pointer of pointer to Qh for return
1680 EFI_DEVICE_ERROR Fail
1687 IN USB2_HC_DEV
*HcDev
,
1688 IN EHCI_QH_ENTITY
*QhPtr
1692 Routine Description:
1694 Destory Qh Structure
1699 QhPtr - A pointer to Qh
1710 IN USB2_HC_DEV
*HcDev
,
1716 OUT EHCI_QTD_ENTITY
**QtdPtrPtr
1720 Routine Description:
1722 Create Qtd Structure and Pre-Initialize it
1727 DataPtr - A pointer to user data buffer to transfer
1728 DataLen - Length of user data to transfer
1729 PktId - Packet Identification of this Qtd
1730 Toggle - Data Toggle of this Qtd
1731 QtdStatus - Default value of status of this Qtd
1732 QtdPtrPtr - A pointer of pointer to Qtd for return
1737 EFI_OUT_OF_RESOURCES Cannot allocate resources
1744 IN USB2_HC_DEV
*HcDev
,
1745 IN UINT8
*DevReqPtr
,
1746 OUT EHCI_QTD_ENTITY
**QtdPtrPtr
1750 Routine Description:
1752 Create Qtd Structure for Setup
1757 DevReqPtr - A pointer to Device Request Data
1758 QtdPtrPtr - A pointer of pointer to Qtd for return
1763 EFI_OUT_OF_RESOURCES Cannot allocate resources
1770 IN USB2_HC_DEV
*HcDev
,
1775 OUT EHCI_QTD_ENTITY
**QtdPtrPtr
1779 Routine Description:
1781 Create Qtd Structure for data
1786 DataPtr - A pointer to user data buffer to transfer
1787 DataLen - Length of user data to transfer
1788 PktId - Packet Identification of this Qtd
1789 Toggle - Data Toggle of this Qtd
1790 QtdPtrPtr - A pointer of pointer to Qtd for return
1795 EFI_OUT_OF_RESOURCES Cannot allocate resources
1802 IN USB2_HC_DEV
*HcDev
,
1804 OUT EHCI_QTD_ENTITY
**QtdPtrPtr
1808 Routine Description:
1810 Create Qtd Structure for status
1815 PktId - Packet Identification of this Qtd
1816 QtdPtrPtr - A pointer of pointer to Qtd for return
1821 EFI_OUT_OF_RESOURCES Cannot allocate resources
1828 IN USB2_HC_DEV
*HcDev
,
1830 OUT EHCI_QTD_ENTITY
**QtdPtrPtr
1834 Routine Description:
1836 Create Qtd Structure for Alternative
1841 PktId - Packet Identification of this Qtd
1842 QtdPtrPtr - A pointer of pointer to Qtd for return
1847 EFI_OUT_OF_RESOURCES Cannot allocate resources
1854 IN USB2_HC_DEV
*HcDev
,
1856 IN UINT8
*RequestCursor
,
1857 IN UINT8
*DataCursor
,
1859 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR
*Translator
,
1860 OUT EHCI_QTD_ENTITY
**ControlQtdsHead
1864 Routine Description:
1866 Create Qtds list for Control Transfer
1871 DataPktId - Packet Identification of Data Qtds
1872 RequestCursor - A pointer to request structure buffer to transfer
1873 DataCursor - A pointer to user data buffer to transfer
1874 DataLen - Length of user data to transfer
1875 ControlQtdsHead - A pointer of pointer to first Qtd for control tranfer for return
1880 EFI_DEVICE_ERROR Fail
1886 CreateBulkOrInterruptQtds (
1887 IN USB2_HC_DEV
*HcDev
,
1889 IN UINT8
*DataCursor
,
1891 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR
*Translator
,
1892 OUT EHCI_QTD_ENTITY
**QtdsHead
1896 Routine Description:
1898 Create Qtds list for Bulk or Interrupt Transfer
1903 PktId - Packet Identification of Qtds
1904 DataCursor - A pointer to user data buffer to transfer
1905 DataLen - Length of user data to transfer
1906 DataToggle - Data Toggle to start
1907 Translator - Translator Transaction for SplitX
1908 QtdsHead - A pointer of pointer to first Qtd for control tranfer for return
1913 EFI_DEVICE_ERROR Fail
1920 IN USB2_HC_DEV
*HcDev
,
1921 IN EHCI_QTD_ENTITY
*FirstQtdPtr
1925 Routine Description:
1927 Destory all Qtds in the list
1932 FirstQtdPtr - A pointer to first Qtd in the list
1943 IN EHCI_QTD_ENTITY
*PreQtdPtr
,
1944 IN EHCI_QTD_ENTITY
*QtdPtr
1948 Routine Description:
1954 PreQtdPtr - A pointer to pre Qtd
1955 QtdPtr - A pointer to next Qtd
1966 IN EHCI_QTD_ENTITY
*FirstQtdPtr
,
1967 IN EHCI_QTD_ENTITY
*AltQtdPtr
1971 Routine Description:
1973 Link AlterQtds together
1977 FirstQtdPtr - A pointer to first Qtd in the list
1978 AltQtdPtr - A pointer to alternative Qtd
1988 IN EHCI_QH_ENTITY
*QhPtr
,
1989 IN EHCI_QTD_ENTITY
*QtdEntryPtr
1993 Routine Description:
1995 Link Qtds list to Qh
1999 QhPtr - A pointer to Qh
2000 QtdPtr - A pointer to first Qtd in the list
2011 IN USB2_HC_DEV
*HcDev
,
2012 IN EHCI_QH_ENTITY
*QhPtr
2016 Routine Description:
2018 Link Qh to Async Schedule List
2023 QhPtr - A pointer to Qh
2028 EFI_DEVICE_ERROR Fail
2034 UnlinkQhFromAsyncList (
2035 IN USB2_HC_DEV
*HcDev
,
2036 IN EHCI_QH_ENTITY
*QhPtr
2040 Routine Description:
2042 Unlink Qh from Async Schedule List
2047 QhPtr - A pointer to Qh
2052 EFI_DEVICE_ERROR Fail
2058 LinkQhToPeriodicList (
2059 IN USB2_HC_DEV
*HcDev
,
2060 IN EHCI_QH_ENTITY
*QhPtr
2064 Routine Description:
2066 Link Qh to Periodic Schedule List
2071 QhPtr - A pointer to Qh
2081 UnlinkQhFromPeriodicList (
2082 IN USB2_HC_DEV
*HcDev
,
2083 IN EHCI_QH_ENTITY
*QhPtr
,
2088 Routine Description:
2090 Unlink Qh from Periodic Schedule List
2095 QhPtr - A pointer to Qh
2096 Interval - Interval of this periodic transfer
2106 LinkToAsyncReqeust (
2107 IN USB2_HC_DEV
*HcDev
,
2108 IN EHCI_ASYNC_REQUEST
*AsyncRequestPtr
2112 Routine Description:
2114 Llink AsyncRequest Entry to Async Request List
2119 AsyncRequestPtr - A pointer to Async Request Entry
2129 UnlinkFromAsyncReqeust (
2130 IN USB2_HC_DEV
*HcDev
,
2131 IN EHCI_ASYNC_REQUEST
*AsyncRequestPtr
2135 Routine Description:
2137 Unlink AsyncRequest Entry from Async Request List
2142 AsyncRequestPtr - A pointer to Async Request Entry
2153 IN EHCI_QTD_ENTITY
*FirstQtdPtr
2157 Routine Description:
2159 Number of Qtds in the list
2163 FirstQtdPtr - A pointer to first Qtd in the list
2167 Number of Qtds in the list
2173 GetNumberOfTransaction (
2174 IN UINTN SizeOfData
,
2175 IN UINTN SizeOfTransaction
2179 Routine Description:
2181 Number of Transactions in one Qtd
2185 SizeOfData - Size of one Qtd
2186 SizeOfTransaction - Size of one Transaction
2190 Number of Transactions in this Qtd
2197 IN UINT8
*BufferCursor
2201 Routine Description:
2207 BufferCursor - BufferCursor of the Qtd
2217 GetApproxiOfInterval (
2222 Routine Description:
2224 Get the approximate value in the 2 index sequence
2228 Interval - the value of interval
2232 approximate value of interval in the 2 index sequence
2239 IN EHCI_QTD_HW
*HwQtdPtr
2243 Routine Description:
2245 Get Qtd next pointer field
2249 HwQtdPtr - A pointer to hardware Qtd structure
2253 A pointer to next hardware Qtd structure
2260 IN EHCI_QTD_HW
*HwQtdPtr
2264 Routine Description:
2266 Whether Qtd status is active or not
2270 HwQtdPtr - A pointer to hardware Qtd structure
2282 IN EHCI_QTD_HW
*HwQtdPtr
2286 Routine Description:
2288 Whether Qtd status is halted or not
2292 HwQtdPtr - A pointer to hardware Qtd structure
2303 IsQtdStatusBufferError (
2304 IN EHCI_QTD_HW
*HwQtdPtr
2308 Routine Description:
2310 Whether Qtd status is buffer error or not
2314 HwQtdPtr - A pointer to hardware Qtd structure
2319 FALSE No buffer error
2325 IsQtdStatusBabbleError (
2326 IN EHCI_QTD_HW
*HwQtdPtr
2330 Routine Description:
2332 Whether Qtd status is babble error or not
2336 HwQtdPtr - A pointer to hardware Qtd structure
2341 FALSE No babble error
2347 IsQtdStatusTransactionError (
2348 IN EHCI_QTD_HW
*HwQtdPtr
2352 Routine Description:
2354 Whether Qtd status is transaction error or not
2358 HwQtdPtr - A pointer to hardware Qtd structure
2362 TRUE Transaction error
2363 FALSE No transaction error
2370 IN UINT8 EndPointAddress
2374 Routine Description:
2376 Whether is a DataIn direction transfer
2380 EndPointAddress - address of the endpoint
2392 IN USB2_HC_DEV
*HcDev
,
2393 IN EFI_USB_DATA_DIRECTION TransferDirection
,
2395 IN OUT UINTN
*DataLength
,
2397 OUT UINT8
**DataCursor
,
2402 Routine Description:
2404 Map address of user data buffer
2409 TransferDirection - direction of transfer
2410 Data - A pointer to user data buffer
2411 DataLength - length of user data
2412 PktId - Packte Identificaion
2413 DataCursor - mapped address to return
2414 DataMap - identificaion of this mapping to return
2419 EFI_DEVICE_ERROR Fail
2426 IN USB2_HC_DEV
*HcDev
,
2427 IN OUT VOID
*Request
,
2428 OUT UINT8
**RequestCursor
,
2429 OUT VOID
**RequestMap
2433 Routine Description:
2435 Map address of request structure buffer
2440 Request - A pointer to request structure
2441 RequestCursor - Mapped address of request structure to return
2442 RequestMap - Identificaion of this mapping to return
2447 EFI_DEVICE_ERROR Fail
2453 SetQtdBufferPointer (
2454 IN EHCI_QTD_HW
*QtdHwPtr
,
2460 Routine Description:
2462 Set data buffer pointers in Qtd
2466 QtdHwPtr - A pointer to Qtd hardware structure
2467 DataPtr - A pointer to user data buffer
2468 DataLen - Length of the user data buffer
2478 GetQtdAlternateNextPointer (
2479 IN EHCI_QTD_HW
*HwQtdPtr
2483 Routine Description:
2485 Get Qtd alternate next pointer field
2489 HwQtdPtr - A pointer to hardware Qtd structure
2493 A pointer to hardware alternate Qtd
2500 IN EHCI_QH_ENTITY
*QhPtr
2504 Routine Description:
2506 Zero out the fields in Qh structure
2510 QhPtr - A pointer to Qh structure
2520 UpdateAsyncRequestTransfer (
2521 IN EHCI_ASYNC_REQUEST
*AsyncRequestPtr
,
2522 IN UINT32 TransferResult
,
2527 Routine Description:
2529 Update asynchronous request transfer
2533 AsyncRequestPtr - A pointer to async request
2534 TransferResult - transfer result
2535 ErrQtdPos - postion of error Qtd
2546 DeleteAsyncRequestTransfer (
2547 IN USB2_HC_DEV
*HcDev
,
2548 IN UINT8 DeviceAddress
,
2549 IN UINT8 EndPointAddress
,
2550 OUT UINT8
*DataToggle
2554 Routine Description:
2556 Delete all asynchronous request transfer
2561 DeviceAddress - address of usb device
2562 EndPointAddress - address of endpoint
2563 DataToggle - stored data toggle
2568 EFI_DEVICE_ERROR Fail
2574 CleanUpAllAsyncRequestTransfer (
2575 IN USB2_HC_DEV
*HcDev
2579 Routine Description:
2581 Clean up all asynchronous request transfer
2595 IN USB2_HC_DEV
*HcDev
,
2596 IN BOOLEAN IsControl
,
2597 IN EHCI_QH_ENTITY
*QhPtr
,
2598 IN OUT UINTN
*ActualLen
,
2599 OUT UINT8
*DataToggle
,
2601 OUT UINT32
*TransferResult
2605 Routine Description:
2607 Execute Bulk or SyncInterrupt Transfer
2612 IsControl - Is control transfer or not
2613 QhPtr - A pointer to Qh
2614 ActualLen - Actual transfered Len
2615 DataToggle - Data Toggle
2616 TimeOut - TimeOut threshold
2617 TransferResult - Transfer result
2622 EFI_DEVICE_ERROR Error
2628 CheckQtdsTransferResult (
2629 IN BOOLEAN IsControl
,
2630 IN EHCI_QH_ENTITY
*QhPtr
,
2632 OUT UINTN
*ErrQtdPos
,
2633 OUT UINTN
*ActualLen
2637 Routine Description:
2639 Check transfer result of Qtds
2643 IsControl - Is control transfer or not
2644 QhPtr - A pointer to Qh
2645 Result - Transfer result
2646 ErrQtdPos - Error TD Position
2647 ActualLen - Actual Transfer Size
2658 AsyncRequestMoniter (
2664 Routine Description:
2666 Interrupt transfer periodic check handler
2670 Event - Interrupt event
2671 Context - Pointer to USB2_HC_DEV
2676 EFI_DEVICE_ERROR Fail