2 Copyright (c) 2006, Intel Corporation
3 All rights reserved. This program and the accompanying materials
4 are licensed and made available under the terms and conditions of the BSD License
5 which accompanies this distribution. The full text of the license may be found at
6 http://opensource.org/licenses/bsd-license.php
8 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 Header file for IDE Bus Driver's Data Structures
22 // TODO: fix comment to end with --*/
39 #define bit10 (1 << 10)
40 #define bit11 (1 << 11)
41 #define bit12 (1 << 12)
42 #define bit13 (1 << 13)
43 #define bit14 (1 << 14)
44 #define bit15 (1 << 15)
45 #define bit16 (1 << 16)
46 #define bit17 (1 << 17)
47 #define bit18 (1 << 18)
48 #define bit19 (1 << 19)
49 #define bit20 (1 << 20)
50 #define bit21 (1 << 21)
51 #define bit22 (1 << 22)
52 #define bit23 (1 << 23)
53 #define bit24 (1 << 24)
54 #define bit25 (1 << 25)
55 #define bit26 (1 << 26)
56 #define bit27 (1 << 27)
57 #define bit28 (1 << 28)
58 #define bit29 (1 << 29)
59 #define bit30 (1 << 30)
60 #define bit31 (1 << 31)
65 #define STALL_1_MILLI_SECOND 1000 // stall 1 ms
66 #define STALL_1_SECOND 1000000 // stall 1 second
80 IdeMagnetic
, /* ZIP Drive or LS120 Floppy Drive */
81 IdeCdRom
, /* ATAPI CDROM */
82 IdeHardDisk
, /* Hard Disk */
83 Ide48bitAddressingHardDisk
, /* Hard Disk larger than 120GB */
91 UINT16 Command
; /* when write */
92 UINT16 Status
; /* when read */
96 UINT16 Error
; /* when read */
97 UINT16 Feature
; /* when write */
98 } IDE_ERROR_OR_FEATURE
;
101 UINT16 AltStatus
; /* when read */
102 UINT16 DeviceControl
; /* when write */
103 } IDE_AltStatus_OR_DeviceControl
;
110 IDE_ERROR_OR_FEATURE Reg1
;
116 IDE_CMD_OR_STATUS Reg
;
118 IDE_AltStatus_OR_DeviceControl Alt
;
122 UINT16 BusMasterBaseAddr
;
123 } IDE_BASE_REGISTERS
;
126 // IDE registers' base addresses
129 UINT16 CommandBlockBaseAddr
;
130 UINT16 ControlBlockBaseAddr
;
131 UINT16 BusMasterBaseAddr
;
132 } IDE_REGISTERS_BASE_ADDR
;
135 // Bit definitions in Programming Interface byte of the Class Code field
136 // in PCI IDE controller's Configuration Space
138 #define IDE_PRIMARY_OPERATING_MODE bit0
139 #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR bit1
140 #define IDE_SECONDARY_OPERATING_MODE bit2
141 #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR bit3
144 // IDE registers bit definitions
150 #define BBK_ERR bit7 /* Bad block detected */
151 #define UNC_ERR bit6 /* Uncorrectable Data */
152 #define MC_ERR bit5 /* Media Change */
153 #define IDNF_ERR bit4 /* ID Not Found */
154 #define MCR_ERR bit3 /* Media Change Requested */
155 #define ABRT_ERR bit2 /* Aborted Command */
156 #define TK0NF_ERR bit1 /* Track 0 Not Found */
157 #define AMNF_ERR bit0 /* Address Mark Not Found */
162 #define LBA_MODE bit6
177 #define BSY bit7 /* Controller Busy */
178 #define DRDY bit6 /* Drive Ready */
179 #define DWF bit5 /* Drive Write Fault */
180 #define DSC bit4 /* Disk Seek Complete */
181 #define DRQ bit3 /* Data Request */
182 #define CORR bit2 /* Corrected Data */
183 #define IDX bit1 /* Index */
184 #define ERR bit0 /* Error */
187 // Device Control Reg
189 #define SRST bit2 /* Software Reset */
190 #define IEN_L bit1 /* Interrupt Enable #*/
195 #define BMIC_nREAD bit3
196 #define BMIC_START bit0
197 #define BMIS_INTERRUPT bit2
198 #define BMIS_ERROR bit1
200 #define BMICP_OFFSET 0x00
201 #define BMISP_OFFSET 0x02
202 #define BMIDP_OFFSET 0x04
203 #define BMICS_OFFSET 0x08
204 #define BMISS_OFFSET 0x0A
205 #define BMIDS_OFFSET 0x0C
208 // Time Out Value For IDE Device Polling
212 // ATATIMEOUT is used for waiting time out for ATA device
218 #define ATATIMEOUT 1000
221 // ATAPITIMEOUT is used for waiting operation
222 // except read and write time out for ATAPI device
228 #define ATAPITIMEOUT 1000
231 // ATAPILONGTIMEOUT is used for waiting read and
232 // write operation timeout for ATAPI device
238 #define CDROMLONGTIMEOUT 2000
243 #define ATAPILONGTIMEOUT 5000
248 #define ATA_INITIALIZE_DEVICE 0x91
253 #define IDENTIFY_DRIVE_CMD 0xec
254 #define READ_BUFFER_CMD 0xe4
255 #define READ_SECTORS_CMD 0x20
256 #define READ_SECTORS_WITH_RETRY_CMD 0x21
257 #define READ_LONG_CMD 0x22
258 #define READ_LONG_WITH_RETRY_CMD 0x23
260 // Class 1 - Atapi6 enhanced commands
262 #define READ_SECTORS_EXT_CMD 0x24
267 #define FORMAT_TRACK_CMD 0x50
268 #define WRITE_BUFFER_CMD 0xe8
269 #define WRITE_SECTORS_CMD 0x30
270 #define WRITE_SECTORS_WITH_RETRY_CMD 0x31
271 #define WRITE_LONG_CMD 0x32
272 #define WRITE_LONG_WITH_RETRY_CMD 0x33
273 #define WRITE_VERIFY_CMD 0x3c
275 // Class 2 - Atapi6 enhanced commands
277 #define WRITE_SECTORS_EXT_CMD 0x34
282 #define ACK_MEDIA_CHANGE_CMD 0xdb
283 #define BOOT_POST_BOOT_CMD 0xdc
284 #define BOOT_PRE_BOOT_CMD 0xdd
285 #define CHECK_POWER_MODE_CMD 0x98
286 #define CHECK_POWER_MODE_CMD_ALIAS 0xe5
287 #define DOOR_LOCK_CMD 0xde
288 #define DOOR_UNLOCK_CMD 0xdf
289 #define EXEC_DRIVE_DIAG_CMD 0x90
290 #define IDLE_CMD_ALIAS 0x97
291 #define IDLE_CMD 0xe3
292 #define IDLE_IMMEDIATE_CMD 0x95
293 #define IDLE_IMMEDIATE_CMD_ALIAS 0xe1
294 #define INIT_DRIVE_PARAM_CMD 0x91
295 #define RECALIBRATE_CMD 0x10 /* aliased to 1x */
296 #define READ_DRIVE_STATE_CMD 0xe9
297 #define SET_MULTIPLE_MODE_CMD 0xC6
298 #define READ_DRIVE_STATE_CMD 0xe9
299 #define READ_VERIFY_CMD 0x40
300 #define READ_VERIFY_WITH_RETRY_CMD 0x41
301 #define SEEK_CMD 0x70 /* aliased to 7x */
302 #define SET_FEATURES_CMD 0xef
303 #define STANDBY_CMD 0x96
304 #define STANDBY_CMD_ALIAS 0xe2
305 #define STANDBY_IMMEDIATE_CMD 0x94
306 #define STANDBY_IMMEDIATE_CMD_ALIAS 0xe0
311 #define READ_DMA_CMD 0xc8
312 #define READ_DMA_WITH_RETRY_CMD 0xc9
313 #define READ_DMA_EXT_CMD 0x25
314 #define WRITE_DMA_CMD 0xca
315 #define WRITE_DMA_WITH_RETRY_CMD 0xcb
316 #define WRITE_DMA_EXT_CMD 0x35
321 #define READ_MULTIPLE_CMD 0xc4
322 #define REST_CMD 0xe7
323 #define RESTORE_DRIVE_STATE_CMD 0xea
324 #define SET_SLEEP_MODE_CMD 0x99
325 #define SET_SLEEP_MODE_CMD_ALIAS 0xe6
326 #define WRITE_MULTIPLE_CMD 0xc5
327 #define WRITE_SAME_CMD 0xe9
330 // Class 6 - Host protected area access feature set
332 #define READ_NATIVE_MAX_ADDRESS_CMD 0xf8
333 #define SET_MAX_ADDRESS_CMD 0xf9
336 // Class 6 - ATA/ATAPI-6 enhanced commands
338 #define READ_NATIVE_MAX_ADDRESS_EXT_CMD 0x27
339 #define SET_MAX_ADDRESS_CMD_EXT 0x37
342 // Class 6 - SET_MAX related sub command (in feature register)
344 #define PARTIES_SET_MAX_ADDRESS_SUB_CMD 0x00
345 #define PARTIES_SET_PASSWORD_SUB_CMD 0x01
346 #define PARTIES_LOCK_SUB_CMD 0x02
347 #define PARTIES_UNLOCK_SUB_CMD 0x03
348 #define PARTIES_FREEZE_SUB_CMD 0x04
353 #define ATA_SMART_CMD 0xb0
354 #define ATA_CONSTANT_C2 0xc2
355 #define ATA_CONSTANT_4F 0x4f
356 #define ATA_SMART_ENABLE_OPERATION 0xd8
357 #define ATA_SMART_RETURN_STATUS 0xda
360 // Error codes for Exec Drive Diag
362 #define DRIV_DIAG_NO_ERROR (0x01)
363 #define DRIV_DIAG_FORMATTER_ERROR (0x02)
364 #define DRIV_DIAG_DATA_BUFFER_ERROR (0x03)
365 #define DRIV_DIAG_ECC_CKT_ERRROR (0x04)
366 #define DRIV_DIAG_UP_ERROR (0x05)
367 #define DRIV_DIAG_SLAVE_DRV_ERROR (0x80) /* aliased to 0x8x */
370 // Codes for Format Track
372 #define FORMAT_GOOD_SECTOR (0x00)
373 #define FORMAT_SUSPEND_ALLOC (0x01)
374 #define FORMAT_REALLOC_SECTOR (0x02)
375 #define FORMAT_MARK_SECTOR_DEFECTIVE (0x03)
381 #define ID_CONFIG_RESERVED0 bit0
382 #define ID_CONFIG_HARD_SECTORED_DRIVE bit1
383 #define ID_CONFIG_SOFT_SECTORED_DRIVE bit2
384 #define ID_CONFIG_NON_MFM bit3
385 #define ID_CONFIG_15uS_HEAD_SWITCHING bit4
386 #define ID_CONFIG_SPINDLE_MOTOR_CONTROL bit5
387 #define ID_CONFIG_HARD_DRIVE bit6
388 #define ID_CONFIG_CHANGEABLE_MEDIUM bit7
389 #define ID_CONFIG_DATA_RATE_TO_5MHZ bit8
390 #define ID_CONFIG_DATA_RATE_5_TO_10MHZ bit9
391 #define ID_CONFIG_DATA_RATE_ABOVE_10MHZ bit10
392 #define ID_CONFIG_MOTOR_SPEED_TOLERANCE_ABOVE_0_5_PERC bit11
393 #define ID_CONFIG_DATA_CLK_OFFSET_AVAIL bit12
394 #define ID_CONFIG_TRACK_OFFSET_AVAIL bit13
395 #define ID_CONFIG_SPEED_TOLERANCE_GAP_NECESSARY bit14
396 #define ID_CONFIG_RESERVED1 bit15
398 #define ID_DOUBLE_WORD_IO_POSSIBLE bit01
399 #define ID_LBA_SUPPORTED bit9
400 #define ID_DMA_SUPPORTED bit8
402 #define SET_FEATURE_ENABLE_8BIT_TRANSFER (0x01)
403 #define SET_FEATURE_ENABLE_WRITE_CACHE (0x02)
404 #define SET_FEATURE_TRANSFER_MODE (0x03)
405 #define SET_FEATURE_WRITE_SAME_WRITE_SPECIFIC_AREA (0x22)
406 #define SET_FEATURE_DISABLE_RETRIES (0x33)
408 // for Read & Write Longs
410 #define SET_FEATURE_VENDOR_SPEC_ECC_LENGTH (0x44)
411 #define SET_FEATURE_PLACE_NO_OF_CACHE_SEGMENTS_IN_SECTOR_NO_REG (0x54)
412 #define SET_FEATURE_DISABLE_READ_AHEAD (0x55)
413 #define SET_FEATURE_MAINTAIN_PARAM_AFTER_RESET (0x66)
414 #define SET_FEATURE_DISABLE_ECC (0x77)
415 #define SET_FEATURE_DISABLE_8BIT_TRANSFER (0x81)
416 #define SET_FEATURE_DISABLE_WRITE_CACHE (0x82)
417 #define SET_FEATURE_ENABLE_ECC (0x88)
418 #define SET_FEATURE_ENABLE_RETRIES (0x99)
419 #define SET_FEATURE_ENABLE_READ_AHEAD (0xaa)
420 #define SET_FEATURE_SET_SECTOR_CNT_REG_AS_NO_OF_READ_AHEAD_SECTORS (0xab)
421 #define SET_FEATURE_ALLOW_REST_MODE (0xac)
423 // for Read & Write Longs
425 #define SET_FEATURE_4BYTE_ECC (0xbb)
426 #define SET_FEATURE_DEFALUT_FEATURES_ON_SOFTWARE_RESET (0xcc)
427 #define SET_FEATURE_WRITE_SAME_TO_WRITE_ENTIRE_MEDIUM (0xdd)
429 #define BLOCK_TRANSFER_MODE (0x00)
430 #define SINGLE_WORD_DMA_TRANSFER_MODE (0x10)
431 #define MULTI_WORD_DMA_TRANSFER_MODE (0x20)
432 #define TRANSFER_MODE_MASK (0x07) // 3 LSBs
437 #define DEFAULT_DRIVE (0x00)
438 #define DEFAULT_CMD (0xa0)
440 // default content of device control register, disable INT
442 #define DEFAULT_CTL (0x0a)
443 #define DEFAULT_IDE_BM_IO_BASE_ADR (0xffa0)
446 // ATAPI6 related data structure definition
450 // The maximum sectors count in 28 bit addressing mode
452 #define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff
455 // Move the IDENTIFY section to DXE\Protocol\IdeControllerInit
461 #define ATAPI_SOFT_RESET_CMD 0x08
462 #define ATAPI_PACKET_CMD 0xA0
463 #define PACKET_CMD 0xA0
464 #define ATAPI_IDENTIFY_DEVICE_CMD 0xA1
465 #define ATAPI_SERVICE_CMD 0xA2
468 // ATAPI Packet Command
485 } TEST_UNIT_READY_CMD
;
489 UINT8 reserved_1
: 4;
493 UINT8 allocation_length
;
505 UINT8 reserved_1
: 4;
509 UINT8 allocation_length
;
521 UINT8 reserved_1
: 4;
524 UINT8 page_control
: 4;
529 UINT8 parameter_list_length_hi
;
530 UINT8 parameter_list_length_lo
;
538 UINT8 reserved_1
: 5;
560 UINT8 allocation_length_hi
;
561 UINT8 allocation_length_lo
;
565 } READ_FORMAT_CAP_CMD
;
569 TEST_UNIT_READY_CMD TestUnitReady
;
571 REQUEST_SENSE_CMD RequestSence
;
573 MODE_SENSE_CMD ModeSense
;
574 READ_FORMAT_CAP_CMD ReadFormatCapacity
;
575 } ATAPI_PACKET_COMMAND
;
578 UINT32 RegionBaseAddr
;
583 #define MAX_DMA_EXT_COMMAND_SECTORS 0x10000
584 #define MAX_DMA_COMMAND_SECTORS 0x100
589 // Packet Command Code
591 #define TEST_UNIT_READY 0x00
593 #define REQUEST_SENSE 0x03
594 #define FORMAT_UNIT 0x04
595 #define REASSIGN_BLOCKS 0x07
597 #define START_STOP_UNIT 0x1B
598 #define PREVENT_ALLOW_MEDIA_REMOVAL 0x1E
599 #define READ_FORMAT_CAPACITY 0x23
600 #define OLD_FORMAT_UNIT 0x24
601 #define READ_CAPACITY 0x25
603 #define WRITE_10 0x2A
605 #define SEND_DIAGNOSTICS 0x3D
606 #define WRITE_VERIFY 0x2E
608 #define READ_DEFECT_DATA 0x37
609 #define WRITE_BUFFER 0x38
610 #define READ_BUFFER 0x3C
611 #define READ_LONG 0x3E
612 #define WRITE_LONG 0x3F
613 #define MODE_SELECT 0x55
614 #define MODE_SENSE 0x5A
616 #define WRITE_12 0xAA
617 #define MAX_ATAPI_BYTE_COUNT (0xfffe)
622 #define REQUEST_SENSE_ERROR (0x70)
623 #define SK_NO_SENSE (0x0)
624 #define SK_RECOVERY_ERROR (0x1)
625 #define SK_NOT_READY (0x2)
626 #define SK_MEDIUM_ERROR (0x3)
627 #define SK_HARDWARE_ERROR (0x4)
628 #define SK_ILLEGAL_REQUEST (0x5)
629 #define SK_UNIT_ATTENTION (0x6)
630 #define SK_DATA_PROTECT (0x7)
631 #define SK_BLANK_CHECK (0x8)
632 #define SK_VENDOR_SPECIFIC (0x9)
633 #define SK_RESERVED_A (0xA)
634 #define SK_ABORT (0xB)
635 #define SK_RESERVED_C (0xC)
636 #define SK_OVERFLOW (0xD)
637 #define SK_MISCOMPARE (0xE)
638 #define SK_RESERVED_F (0xF)
641 // Additional Sense Codes
643 #define ASC_NOT_READY (0x04)
644 #define ASC_MEDIA_ERR1 (0x10)
645 #define ASC_MEDIA_ERR2 (0x11)
646 #define ASC_MEDIA_ERR3 (0x14)
647 #define ASC_MEDIA_ERR4 (0x30)
648 #define ASC_MEDIA_UPSIDE_DOWN (0x06)
649 #define ASC_INVALID_CMD (0x20)
650 #define ASC_LBA_OUT_OF_RANGE (0x21)
651 #define ASC_INVALID_FIELD (0x24)
652 #define ASC_WRITE_PROTECTED (0x27)
653 #define ASC_MEDIA_CHANGE (0x28)
654 #define ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */
655 #define ASC_ILLEGAL_FIELD (0x26)
656 #define ASC_NO_MEDIA (0x3A)
657 #define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
660 // Additional Sense Code Qualifier
662 #define ASCQ_IN_PROGRESS (0x01)
664 #define SETFEATURE TRUE
665 #define CLEARFEATURE FALSE
668 // ATAPI Data structure
673 UINT8 peripheral_type
;
676 UINT8 response_data_format
;
681 UINT8 vendor_info
[8];
682 UINT8 product_id
[12];
683 UINT8 eeprom_product_code
[4];
684 UINT8 firmware_rev_level
[4];
685 UINT8 firmware_sub_rev_level
[1];
689 UINT8 max_capacity_hi
;
690 UINT8 max_capacity_mid
;
691 UINT8 max_capacity_lo
;
692 UINT8 reserved_43_95
[95 - 43 + 1];
696 UINT8 peripheral_type
;
699 UINT8 response_data_format
;
704 UINT8 vendor_info
[8];
705 UINT8 product_id
[16];
706 UINT8 product_revision_level
[4];
707 UINT8 vendor_specific
[20];
708 UINT8 reserved_56_95
[40];
709 } CDROM_INQUIRY_DATA
;
712 UINT8 error_code
: 7;
716 UINT8 reserved_21
: 1;
718 UINT8 reserved_22
: 2;
719 UINT8 vendor_specific_3
;
720 UINT8 vendor_specific_4
;
721 UINT8 vendor_specific_5
;
722 UINT8 vendor_specific_6
;
723 UINT8 addnl_sense_length
; // n - 7
724 UINT8 vendor_specific_8
;
725 UINT8 vendor_specific_9
;
726 UINT8 vendor_specific_10
;
727 UINT8 vendor_specific_11
;
728 UINT8 addnl_sense_code
; // mandatory
729 UINT8 addnl_sense_code_qualifier
; // mandatory
730 UINT8 field_replaceable_unit_code
; // optional
735 // Followed by additional sense bytes : FIXME
737 } REQUEST_SENSE_DATA
;
748 } READ_CAPACITY_DATA
;
754 UINT8 Capacity_Length
;
760 UINT8 reserved_9
: 6;
764 } READ_FORMAT_CAPACITY_DATA
;
769 // PIO mode definition
772 ATA_PIO_MODE_BELOW_2
,
779 // Multi word DMA definition
788 // UDMA mode definition
799 #define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00
800 #define ATA_MODE_CATEGORY_FLOW_PIO 0x01
801 #define ATA_MODE_CATEGORY_MDMA 0x04
802 #define ATA_MODE_CATEGORY_UDMA 0x08
807 UINT8 ModeNumber
: 3;
808 UINT8 ModeCategory
: 5;
814 UINT8 MultipleSector
;
819 // IORDY Sample Point field value
827 // Recovery Time field value
829 #define RECVY_4_CLK 0
830 #define RECVY_3_CLK 1
831 #define RECVY_2_CLK 2
832 #define RECVY_1_CLK 3
835 // Slave IDE Timing Register Enable
840 // DMA Timing Enable Only Select 1
845 // Pre-fetch and Posting Enable Select 1
850 // IORDY Sample Point Enable Select 1
855 // Fast Timing Bank Drive Select 1
860 // DMA Timing Enable Only Select 0
865 // Pre-fetch and Posting Enable Select 0
870 // IOREY Sample Point Enable Select 0
875 // Fast Timing Bank Drive Select 0