3 Copyright (c) 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 x64 Long Mode Virtual Memory Management Definitions
20 1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel
21 2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
22 3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
23 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
25 #ifndef _VIRTUAL_MEMORY_H_
26 #define _VIRTUAL_MEMORY_H_
32 // Page-Map Level-4 Offset (PML4) and
33 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
38 UINT64 Present
:1; // 0 = Not present in memory, 1 = Present in memory
39 UINT64 ReadWrite
:1; // 0 = Read-Only, 1= Read/Write
40 UINT64 UserSupervisor
:1; // 0 = Supervisor, 1=User
41 UINT64 WriteThrough
:1; // 0 = Write-Back caching, 1=Write-Through caching
42 UINT64 CacheDisabled
:1; // 0 = Cached, 1=Non-Cached
43 UINT64 Accessed
:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
44 UINT64 Reserved
:1; // Reserved
45 UINT64 MustBeZero
:2; // Must Be Zero
46 UINT64 Available
:3; // Available for use by system software
47 UINT64 PageTableBaseAddress
:40; // Page Table Base Address
48 UINT64 AvabilableHigh
:11; // Available for use by system software
49 UINT64 Nx
:1; // No Execute bit
52 } PAGE_MAP_AND_DIRECTORY_POINTER
;
55 // Page Table Entry 2MB
59 UINT64 Present
:1; // 0 = Not present in memory, 1 = Present in memory
60 UINT64 ReadWrite
:1; // 0 = Read-Only, 1= Read/Write
61 UINT64 UserSupervisor
:1; // 0 = Supervisor, 1=User
62 UINT64 WriteThrough
:1; // 0 = Write-Back caching, 1=Write-Through caching
63 UINT64 CacheDisabled
:1; // 0 = Cached, 1=Non-Cached
64 UINT64 Accessed
:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
65 UINT64 Dirty
:1; // 0 = Not Dirty, 1 = written by processor on access to page
66 UINT64 MustBe1
:1; // Must be 1
67 UINT64 Global
:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
68 UINT64 Available
:3; // Available for use by system software
70 UINT64 MustBeZero
:8; // Must be zero;
71 UINT64 PageTableBaseAddress
:31; // Page Table Base Address
72 UINT64 AvabilableHigh
:11; // Available for use by system software
73 UINT64 Nx
:1; // 0 = Execute Code, 1 = No Code Execution
81 CreateIdentityMappingPageTables (