2 Header file for IDE Bus Driver's Data Structures
4 Copyright (c) 2006 - 2007 Intel Corporation. <BR>
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <IndustryStandard/Atapi.h>
23 #define STALL_1_MILLI_SECOND 1000 // stall 1 ms
24 #define STALL_1_SECOND 1000000 // stall 1 second
38 IdeMagnetic
, /* ZIP Drive or LS120 Floppy Drive */
39 IdeCdRom
, /* ATAPI CDROM */
40 IdeHardDisk
, /* Hard Disk */
41 Ide48bitAddressingHardDisk
, /* Hard Disk larger than 120GB */
47 SenseDeviceNotReadyNoRetry
,
48 SenseDeviceNotReadyNeedRetry
,
66 UINT16 Command
; /* when write */
67 UINT16 Status
; /* when read */
71 UINT16 Error
; /* when read */
72 UINT16 Feature
; /* when write */
73 } IDE_ERROR_OR_FEATURE
;
76 UINT16 AltStatus
; /* when read */
77 UINT16 DeviceControl
; /* when write */
78 } IDE_ALTSTATUS_OR_DEVICECONTROL
;
85 IDE_ERROR_OR_FEATURE Reg1
;
91 IDE_CMD_OR_STATUS Reg
;
93 IDE_ALTSTATUS_OR_DEVICECONTROL Alt
;
97 UINT16 BusMasterBaseAddr
;
101 // IDE registers' base addresses
104 UINT16 CommandBlockBaseAddr
;
105 UINT16 ControlBlockBaseAddr
;
106 UINT16 BusMasterBaseAddr
;
107 } IDE_REGISTERS_BASE_ADDR
;
110 // Bit definitions in Programming Interface byte of the Class Code field
111 // in PCI IDE controller's Configuration Space
113 #define IDE_PRIMARY_OPERATING_MODE BIT0
114 #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1
115 #define IDE_SECONDARY_OPERATING_MODE BIT2
116 #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR BIT3
122 #define BMIC_NREAD BIT3
123 #define BMIC_START BIT0
124 #define BMIS_INTERRUPT BIT2
125 #define BMIS_ERROR BIT1
127 #define BMICP_OFFSET 0x00
128 #define BMISP_OFFSET 0x02
129 #define BMIDP_OFFSET 0x04
130 #define BMICS_OFFSET 0x08
131 #define BMISS_OFFSET 0x0A
132 #define BMIDS_OFFSET 0x0C
135 // Time Out Value For IDE Device Polling
139 // ATATIMEOUT is used for waiting time out for ATA device
145 #define ATATIMEOUT 1000
148 // ATAPITIMEOUT is used for waiting operation
149 // except read and write time out for ATAPI device
155 #define ATAPITIMEOUT 1000
158 // ATAPILONGTIMEOUT is used for waiting read and
159 // write operation timeout for ATAPI device
165 #define CDROMLONGTIMEOUT 2000
170 #define ATAPILONGTIMEOUT 5000
175 #define ATASMARTTIMEOUT 10000
179 // ATAPI6 related data structure definition
183 // The maximum sectors count in 28 bit addressing mode
185 #define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff
190 UINT32 RegionBaseAddr
;
197 #define SETFEATURE TRUE
198 #define CLEARFEATURE FALSE
201 // PIO mode definition
204 ATA_PIO_MODE_BELOW_2
,
211 // Multi word DMA definition
220 // UDMA mode definition
231 #define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00
232 #define ATA_MODE_CATEGORY_FLOW_PIO 0x01
233 #define ATA_MODE_CATEGORY_MDMA 0x04
234 #define ATA_MODE_CATEGORY_UDMA 0x08
239 UINT8 ModeNumber
: 3;
240 UINT8 ModeCategory
: 5;
246 UINT8 MultipleSector
;
251 // IORDY Sample Point field value
259 // Recovery Time field value
261 #define RECVY_4_CLK 0
262 #define RECVY_3_CLK 1
263 #define RECVY_2_CLK 2
264 #define RECVY_1_CLK 3
267 // Slave IDE Timing Register Enable
272 // DMA Timing Enable Only Select 1
277 // Pre-fetch and Posting Enable Select 1
282 // IORDY Sample Point Enable Select 1
287 // Fast Timing Bank Drive Select 1
292 // DMA Timing Enable Only Select 0
297 // Pre-fetch and Posting Enable Select 0
302 // IOREY Sample Point Enable Select 0
307 // Fast Timing Bank Drive Select 0