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1 /**@file
2
3 Copyright (c) 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 **/
13
14
15 #include "PciBus.h"
16 #include "PciEnumeratorSupport.h"
17 #include "PciCommand.h"
18 #include "PciIo.h"
19
20 /**
21 This routine is used to check whether the pci device is present.
22
23 @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
24 @param Pci Output buffer for PCI device structure
25 @param Bus PCI bus NO
26 @param Device PCI device NO
27 @param Func PCI Func NO
28
29 @retval EFI_NOT_FOUND device not present
30 @retval EFI_SUCCESS device is found.
31 **/
32 EFI_STATUS
33 PciDevicePresent (
34 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
35 PCI_TYPE00 *Pci,
36 UINT8 Bus,
37 UINT8 Device,
38 UINT8 Func
39 )
40 {
41 UINT64 Address;
42 EFI_STATUS Status;
43
44 //
45 // Create PCI address map in terms of Bus, Device and Func
46 //
47 Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);
48
49 //
50 // Read the Vendor Id register
51 //
52 Status = PciRootBridgeIoRead (
53 PciRootBridgeIo,
54 NULL,
55 EfiPciWidthUint32,
56 Address,
57 1,
58 Pci
59 );
60
61 if (!EFI_ERROR (Status) && (Pci->Hdr).VendorId != 0xffff) {
62
63 //
64 // Read the entire config header for the device
65 //
66
67 Status = PciRootBridgeIoRead (
68 PciRootBridgeIo,
69 NULL,
70 EfiPciWidthUint32,
71 Address,
72 sizeof (PCI_TYPE00) / sizeof (UINT32),
73 Pci
74 );
75
76 return EFI_SUCCESS;
77 }
78
79 return EFI_NOT_FOUND;
80 }
81
82 /**
83 Collect all the resource information under this root bridge
84 A database that records all the information about pci device subject to this
85 root bridge will then be created.
86
87 @param Bridge Parent bridge instance
88 @param StartBusNumer Bus number of begining
89 **/
90 EFI_STATUS
91 PciPciDeviceInfoCollector (
92 IN PCI_IO_DEVICE *Bridge,
93 UINT8 StartBusNumber
94 )
95 {
96 EFI_STATUS Status;
97 PCI_TYPE00 Pci;
98 UINT8 Device;
99 UINT8 Func;
100 UINT8 SecBus;
101 PCI_IO_DEVICE *PciIoDevice;
102 EFI_PCI_IO_PROTOCOL *PciIo;
103
104 Status = EFI_SUCCESS;
105 SecBus = 0;
106
107 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
108
109 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
110
111 //
112 // Check to see whether PCI device is present
113 //
114
115 Status = PciDevicePresent (
116 Bridge->PciRootBridgeIo,
117 &Pci,
118 (UINT8) StartBusNumber,
119 (UINT8) Device,
120 (UINT8) Func
121 );
122
123 if (!EFI_ERROR (Status)) {
124
125 //
126 // Call back to host bridge function
127 //
128 PreprocessController (Bridge, (UINT8) StartBusNumber, Device, Func, EfiPciBeforeResourceCollection);
129
130 //
131 // Collect all the information about the PCI device discovered
132 //
133 Status = PciSearchDevice (
134 Bridge,
135 &Pci,
136 (UINT8) StartBusNumber,
137 Device,
138 Func,
139 &PciIoDevice
140 );
141
142 //
143 // Recursively scan PCI busses on the other side of PCI-PCI bridges
144 //
145 //
146
147 if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {
148
149 //
150 // If it is PPB, we need to get the secondary bus to continue the enumeration
151 //
152 PciIo = &(PciIoDevice->PciIo);
153
154 Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &SecBus);
155
156 if (EFI_ERROR (Status)) {
157 return Status;
158 }
159
160 //
161 // Get resource padding for PPB
162 //
163 GetResourcePaddingPpb (PciIoDevice);
164
165 //
166 // Deep enumerate the next level bus
167 //
168 Status = PciPciDeviceInfoCollector (
169 PciIoDevice,
170 (UINT8) (SecBus)
171 );
172
173 }
174
175 if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
176
177 //
178 // Skip sub functions, this is not a multi function device
179 //
180 Func = PCI_MAX_FUNC;
181 }
182 }
183
184 }
185 }
186
187 return EFI_SUCCESS;
188 }
189
190 /**
191 Seach required device and get PCI device info block
192
193 @param Bridge Parent bridge instance
194 @param Pci Output of PCI device info block
195 @param Bus PCI bus NO.
196 @param Device PCI device NO.
197 @param Func PCI func NO.
198 @param PciDevice output of searched PCI device instance
199 **/
200 EFI_STATUS
201 PciSearchDevice (
202 IN PCI_IO_DEVICE *Bridge,
203 IN PCI_TYPE00 *Pci,
204 IN UINT8 Bus,
205 IN UINT8 Device,
206 IN UINT8 Func,
207 OUT PCI_IO_DEVICE **PciDevice
208 )
209 {
210 PCI_IO_DEVICE *PciIoDevice;
211
212 PciIoDevice = NULL;
213
214 if (!IS_PCI_BRIDGE (Pci)) {
215
216 if (IS_CARDBUS_BRIDGE (Pci)) {
217 PciIoDevice = GatherP2CInfo (
218 Bridge,
219 Pci,
220 Bus,
221 Device,
222 Func
223 );
224 if ((PciIoDevice != NULL) && gFullEnumeration) {
225 InitializeP2C (PciIoDevice);
226 }
227 } else {
228
229 //
230 // Create private data for Pci Device
231 //
232 PciIoDevice = GatherDeviceInfo (
233 Bridge,
234 Pci,
235 Bus,
236 Device,
237 Func
238 );
239
240 }
241
242 } else {
243
244 //
245 // Create private data for PPB
246 //
247 PciIoDevice = GatherPpbInfo (
248 Bridge,
249 Pci,
250 Bus,
251 Device,
252 Func
253 );
254
255 //
256 // Special initialization for PPB including making the PPB quiet
257 //
258 if ((PciIoDevice != NULL) && gFullEnumeration) {
259 InitializePpb (PciIoDevice);
260 }
261 }
262
263 if (!PciIoDevice) {
264 return EFI_OUT_OF_RESOURCES;
265 }
266
267 //
268 // Update the bar information for this PCI device so as to support some specific device
269 //
270 UpdatePciInfo (PciIoDevice);
271
272 if (PciIoDevice->DevicePath == NULL) {
273 return EFI_OUT_OF_RESOURCES;
274 }
275
276 //
277 // Detect this function has option rom
278 //
279 if (gFullEnumeration) {
280
281 if (!IS_CARDBUS_BRIDGE (Pci)) {
282
283 GetOpRomInfo (PciIoDevice);
284
285 }
286
287 ResetPowerManagementFeature (PciIoDevice);
288
289 }
290
291 //
292 // Insert it into a global tree for future reference
293 //
294 InsertPciDevice (Bridge, PciIoDevice);
295
296 //
297 // Determine PCI device attributes
298 //
299
300 if (PciDevice != NULL) {
301 *PciDevice = PciIoDevice;
302 }
303
304 return EFI_SUCCESS;
305 }
306
307 /**
308 Create PCI private data for PCI device
309
310 @param Bridge Parent bridge instance
311 @param Pci PCI bar block
312 @param Bus PCI device Bus NO.
313 @param Device PCI device DeviceNO.
314 @param Func PCI device's func NO.
315
316 @return new PCI device's private date structure.
317 **/
318 PCI_IO_DEVICE *
319 GatherDeviceInfo (
320 IN PCI_IO_DEVICE *Bridge,
321 IN PCI_TYPE00 *Pci,
322 UINT8 Bus,
323 UINT8 Device,
324 UINT8 Func
325 )
326 {
327 UINTN Offset;
328 UINTN BarIndex;
329 PCI_IO_DEVICE *PciIoDevice;
330 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
331
332 PciRootBridgeIo = Bridge->PciRootBridgeIo;
333 PciIoDevice = CreatePciIoDevice (
334 PciRootBridgeIo,
335 Pci,
336 Bus,
337 Device,
338 Func
339 );
340
341 if (!PciIoDevice) {
342 return NULL;
343 }
344
345 //
346 // Create a device path for this PCI device and store it into its private data
347 //
348 CreatePciDevicePath (
349 Bridge->DevicePath,
350 PciIoDevice
351 );
352
353 //
354 // If it is a full enumeration, disconnect the device in advance
355 //
356 if (gFullEnumeration) {
357
358 PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
359
360 }
361
362 //
363 // Start to parse the bars
364 //
365 for (Offset = 0x10, BarIndex = 0; Offset <= 0x24; BarIndex++) {
366 Offset = PciParseBar (PciIoDevice, Offset, BarIndex);
367 }
368
369 return PciIoDevice;
370 }
371
372 /**
373 Create private data for bridge device's PPB.
374
375 @param Bridge Parent bridge
376 @param Pci Pci device block
377 @param Bus Bridge device's bus NO.
378 @param Device Bridge device's device NO.
379 @param Func Bridge device's func NO.
380
381 @return bridge device instance
382 **/
383 PCI_IO_DEVICE *
384 GatherPpbInfo (
385 IN PCI_IO_DEVICE *Bridge,
386 IN PCI_TYPE00 *Pci,
387 UINT8 Bus,
388 UINT8 Device,
389 UINT8 Func
390 )
391 {
392 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
393 PCI_IO_DEVICE *PciIoDevice;
394 EFI_STATUS Status;
395 UINT32 Value;
396 EFI_PCI_IO_PROTOCOL *PciIo;
397 UINT8 Temp;
398
399 PciRootBridgeIo = Bridge->PciRootBridgeIo;
400 PciIoDevice = CreatePciIoDevice (
401 PciRootBridgeIo,
402 Pci,
403 Bus,
404 Device,
405 Func
406 );
407
408 if (!PciIoDevice) {
409 return NULL;
410 }
411
412 //
413 // Create a device path for this PCI device and store it into its private data
414 //
415 CreatePciDevicePath (
416 Bridge->DevicePath,
417 PciIoDevice
418 );
419
420 if (gFullEnumeration) {
421 PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
422
423 //
424 // Initalize the bridge control register
425 //
426 PciDisableBridgeControlRegister (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);
427
428 }
429
430 //
431 // PPB can have two BARs
432 //
433 if (PciParseBar (PciIoDevice, 0x10, PPB_BAR_0) == 0x14) {
434 //
435 // Not 64-bit bar
436 //
437 PciParseBar (PciIoDevice, 0x14, PPB_BAR_1);
438 }
439
440 PciIo = &PciIoDevice->PciIo;
441
442 //
443 // Test whether it support 32 decode or not
444 //
445 PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
446 PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
447 PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);
448 PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
449
450 if (Value) {
451 if (Value & 0x01) {
452 PciIoDevice->Decodes |= EFI_BRIDGE_IO32_DECODE_SUPPORTED;
453 } else {
454 PciIoDevice->Decodes |= EFI_BRIDGE_IO16_DECODE_SUPPORTED;
455 }
456 }
457
458 Status = BarExisted (
459 PciIoDevice,
460 0x24,
461 NULL,
462 NULL
463 );
464
465 //
466 // test if it supports 64 memory or not
467 //
468 if (!EFI_ERROR (Status)) {
469
470 Status = BarExisted (
471 PciIoDevice,
472 0x28,
473 NULL,
474 NULL
475 );
476
477 if (!EFI_ERROR (Status)) {
478 PciIoDevice->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;
479 PciIoDevice->Decodes |= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED;
480 } else {
481 PciIoDevice->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;
482 }
483 }
484
485 //
486 // Memory 32 code is required for ppb
487 //
488 PciIoDevice->Decodes |= EFI_BRIDGE_MEM32_DECODE_SUPPORTED;
489
490 GetResourcePaddingPpb (PciIoDevice);
491
492 return PciIoDevice;
493 }
494
495 /**
496 Create private data for hotplug bridge device
497
498 @param Bridge Parent bridge instance
499 @param Pci PCI bar block
500 @param Bus hotplug bridge device's bus NO.
501 @param Device hotplug bridge device's device NO.
502 @param Func hotplug bridge device's Func NO.
503
504 @return hotplug bridge device instance
505 **/
506 PCI_IO_DEVICE *
507 GatherP2CInfo (
508 IN PCI_IO_DEVICE *Bridge,
509 IN PCI_TYPE00 *Pci,
510 UINT8 Bus,
511 UINT8 Device,
512 UINT8 Func
513 )
514 {
515 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
516 PCI_IO_DEVICE *PciIoDevice;
517
518 PciRootBridgeIo = Bridge->PciRootBridgeIo;
519 PciIoDevice = CreatePciIoDevice (
520 PciRootBridgeIo,
521 Pci,
522 Bus,
523 Device,
524 Func
525 );
526
527 if (!PciIoDevice) {
528 return NULL;
529 }
530
531 //
532 // Create a device path for this PCI device and store it into its private data
533 //
534 CreatePciDevicePath (
535 Bridge->DevicePath,
536 PciIoDevice
537 );
538
539 if (gFullEnumeration) {
540 PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
541
542 //
543 // Initalize the bridge control register
544 //
545 PciDisableBridgeControlRegister (PciIoDevice, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED);
546
547 }
548 //
549 // P2C only has one bar that is in 0x10
550 //
551 PciParseBar (PciIoDevice, 0x10, P2C_BAR_0);
552
553 //
554 // Read PciBar information from the bar register
555 //
556 GetBackPcCardBar (PciIoDevice);
557 PciIoDevice->Decodes = EFI_BRIDGE_MEM32_DECODE_SUPPORTED |
558 EFI_BRIDGE_PMEM32_DECODE_SUPPORTED |
559 EFI_BRIDGE_IO32_DECODE_SUPPORTED;
560
561 return PciIoDevice;
562 }
563
564 /**
565 Create device path for pci deivce
566
567 @param ParentDevicePath Parent bridge's path
568 @param PciIoDevice Pci device instance
569
570 @return device path protocol instance for specific pci device.
571 **/
572 EFI_DEVICE_PATH_PROTOCOL *
573 CreatePciDevicePath (
574 IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
575 IN PCI_IO_DEVICE *PciIoDevice
576 )
577 {
578
579 PCI_DEVICE_PATH PciNode;
580
581 //
582 // Create PCI device path
583 //
584 PciNode.Header.Type = HARDWARE_DEVICE_PATH;
585 PciNode.Header.SubType = HW_PCI_DP;
586 SetDevicePathNodeLength (&PciNode.Header, sizeof (PciNode));
587
588 PciNode.Device = PciIoDevice->DeviceNumber;
589 PciNode.Function = PciIoDevice->FunctionNumber;
590 PciIoDevice->DevicePath = AppendDevicePathNode (ParentDevicePath, &PciNode.Header);
591
592 return PciIoDevice->DevicePath;
593 }
594
595 /**
596 Check the bar is existed or not.
597
598 @param PciIoDevice - A pointer to the PCI_IO_DEVICE.
599 @param Offset - The offset.
600 @param BarLengthValue - The bar length value.
601 @param OriginalBarValue - The original bar value.
602
603 @retval EFI_NOT_FOUND - The bar don't exist.
604 @retval EFI_SUCCESS - The bar exist.
605
606 **/
607 EFI_STATUS
608 BarExisted (
609 IN PCI_IO_DEVICE *PciIoDevice,
610 IN UINTN Offset,
611 OUT UINT32 *BarLengthValue,
612 OUT UINT32 *OriginalBarValue
613 )
614
615 {
616 EFI_PCI_IO_PROTOCOL *PciIo;
617 UINT32 OriginalValue;
618 UINT32 Value;
619 EFI_TPL OldTpl;
620
621 PciIo = &PciIoDevice->PciIo;
622
623 //
624 // Preserve the original value
625 //
626
627 PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
628
629 //
630 // Raise TPL to high level to disable timer interrupt while the BAR is probed
631 //
632 OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
633
634 PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);
635 PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);
636
637 //
638 // Write back the original value
639 //
640 PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
641
642 //
643 // Restore TPL to its original level
644 //
645 gBS->RestoreTPL (OldTpl);
646
647 if (BarLengthValue != NULL) {
648 *BarLengthValue = Value;
649 }
650
651 if (OriginalBarValue != NULL) {
652 *OriginalBarValue = OriginalValue;
653 }
654
655 if (Value == 0) {
656 return EFI_NOT_FOUND;
657 } else {
658 return EFI_SUCCESS;
659 }
660 }
661
662 /**
663 Test whether the device can support attributes
664
665 @param PciIoDevice Pci device instance
666 @param Command Command register value.
667 @param BridgeControl Bridge control value for PPB or P2C.
668 @param OldCommand Old command register offset
669 @param OldBridgeControl Old Bridge control value for PPB or P2C.
670
671 @return EFI_SUCCESS
672 **/
673 EFI_STATUS
674 PciTestSupportedAttribute (
675 IN PCI_IO_DEVICE *PciIoDevice,
676 IN UINT16 *Command,
677 IN UINT16 *BridgeControl,
678 IN UINT16 *OldCommand,
679 IN UINT16 *OldBridgeControl
680 )
681 {
682 EFI_TPL OldTpl;
683
684 //
685 // Preserve the original value
686 //
687 PciReadCommandRegister (PciIoDevice, OldCommand);
688
689 //
690 // Raise TPL to high level to disable timer interrupt while the BAR is probed
691 //
692 OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
693
694 PciSetCommandRegister (PciIoDevice, *Command);
695 PciReadCommandRegister (PciIoDevice, Command);
696
697 //
698 // Write back the original value
699 //
700 PciSetCommandRegister (PciIoDevice, *OldCommand);
701
702 //
703 // Restore TPL to its original level
704 //
705 gBS->RestoreTPL (OldTpl);
706
707 if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
708
709 //
710 // Preserve the original value
711 //
712 PciReadBridgeControlRegister (PciIoDevice, OldBridgeControl);
713
714 //
715 // Raise TPL to high level to disable timer interrupt while the BAR is probed
716 //
717 OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
718
719 PciSetBridgeControlRegister (PciIoDevice, *BridgeControl);
720 PciReadBridgeControlRegister (PciIoDevice, BridgeControl);
721
722 //
723 // Write back the original value
724 //
725 PciSetBridgeControlRegister (PciIoDevice, *OldBridgeControl);
726
727 //
728 // Restore TPL to its original level
729 //
730 gBS->RestoreTPL (OldTpl);
731
732 } else {
733 *OldBridgeControl = 0;
734 *BridgeControl = 0;
735 }
736
737 return EFI_SUCCESS;
738 }
739
740 /**
741 Set the supported or current attributes of a PCI device
742
743 @param PciIoDevice - Structure pointer for PCI device.
744 @param Command - Command register value.
745 @param BridgeControl - Bridge control value for PPB or P2C.
746 @param Option - Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.
747
748 **/
749 EFI_STATUS
750 PciSetDeviceAttribute (
751 IN PCI_IO_DEVICE *PciIoDevice,
752 IN UINT16 Command,
753 IN UINT16 BridgeControl,
754 IN UINTN Option
755 )
756 {
757 UINT64 Attributes;
758
759 Attributes = 0;
760
761 if (Command & EFI_PCI_COMMAND_IO_SPACE) {
762 Attributes |= EFI_PCI_IO_ATTRIBUTE_IO;
763 }
764
765 if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {
766 Attributes |= EFI_PCI_IO_ATTRIBUTE_MEMORY;
767 }
768
769 if (Command & EFI_PCI_COMMAND_BUS_MASTER) {
770 Attributes |= EFI_PCI_IO_ATTRIBUTE_BUS_MASTER;
771 }
772
773 if (Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) {
774 Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;
775 }
776
777 if (BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA) {
778 Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_IO;
779 }
780
781 if (BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA) {
782 Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_IO;
783 Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY;
784 Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;
785 }
786
787 if (BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16) {
788 Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_IO_16;
789 Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16;
790 }
791
792 if (Option == EFI_SET_SUPPORTS) {
793
794 Attributes |= EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE |
795 EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED |
796 EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE |
797 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
798 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
799 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE;
800
801 if (Attributes & EFI_PCI_IO_ATTRIBUTE_IO) {
802 Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO;
803 Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_IO;
804 }
805
806 if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
807 //
808 // For bridge, it should support IDE attributes
809 //
810 Attributes |= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO;
811 Attributes |= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO;
812 } else {
813
814 if (IS_PCI_IDE (&PciIoDevice->Pci)) {
815 Attributes |= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO;
816 Attributes |= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO;
817 }
818
819 if (IS_PCI_VGA (&PciIoDevice->Pci)) {
820 Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY;
821 Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_IO;
822 }
823 }
824
825 PciIoDevice->Supports = Attributes;
826 PciIoDevice->Supports &= ( (PciIoDevice->Parent->Supports) | \
827 EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | \
828 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER );
829
830 } else {
831 PciIoDevice->Attributes = Attributes;
832 }
833
834 return EFI_SUCCESS;
835 }
836
837 /**
838 Determine if the device can support Fast Back to Back attribute
839
840 @param PciIoDevice Pci device instance
841 @param StatusIndex Status register value
842 **/
843 EFI_STATUS
844 GetFastBackToBackSupport (
845 IN PCI_IO_DEVICE *PciIoDevice,
846 IN UINT8 StatusIndex
847 )
848 {
849 EFI_PCI_IO_PROTOCOL *PciIo;
850 EFI_STATUS Status;
851 UINT32 StatusRegister;
852
853 //
854 // Read the status register
855 //
856 PciIo = &PciIoDevice->PciIo;
857 Status = PciIoRead (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);
858 if (EFI_ERROR (Status)) {
859 return EFI_UNSUPPORTED;
860 }
861
862 //
863 // Check the Fast B2B bit
864 //
865 if (StatusRegister & EFI_PCI_FAST_BACK_TO_BACK_CAPABLE) {
866 return EFI_SUCCESS;
867 } else {
868 return EFI_UNSUPPORTED;
869 }
870
871 }
872
873 /**
874 Process the option ROM for all the children of the specified parent PCI device.
875 It can only be used after the first full Option ROM process.
876
877 @param PciIoDevice Pci device instance
878
879 @retval EFI_SUCCESS Success Operation.
880 **/
881 STATIC
882 EFI_STATUS
883 ProcessOptionRomLight (
884 IN PCI_IO_DEVICE *PciIoDevice
885 )
886 {
887 PCI_IO_DEVICE *Temp;
888 LIST_ENTRY *CurrentLink;
889
890 //
891 // For RootBridge, PPB , P2C, go recursively to traverse all its children
892 //
893 CurrentLink = PciIoDevice->ChildList.ForwardLink;
894 while (CurrentLink && CurrentLink != &PciIoDevice->ChildList) {
895
896 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
897
898 if (!IsListEmpty (&Temp->ChildList)) {
899 ProcessOptionRomLight (Temp);
900 }
901
902 PciRomGetImageMapping (Temp);
903
904 //
905 // The OpRom has already been processed in the first round
906 //
907 Temp->AllOpRomProcessed = TRUE;
908
909 CurrentLink = CurrentLink->ForwardLink;
910 }
911
912 return EFI_SUCCESS;
913 }
914
915 /**
916 Determine the related attributes of all devices under a Root Bridge
917
918 @param PciIoDevice PCI device instance
919
920 **/
921 EFI_STATUS
922 DetermineDeviceAttribute (
923 IN PCI_IO_DEVICE *PciIoDevice
924 )
925 {
926 UINT16 Command;
927 UINT16 BridgeControl;
928 UINT16 OldCommand;
929 UINT16 OldBridgeControl;
930 BOOLEAN FastB2BSupport;
931
932 /*
933 UINT8 IdePI;
934 EFI_PCI_IO_PROTOCOL *PciIo;
935 */
936 PCI_IO_DEVICE *Temp;
937 LIST_ENTRY *CurrentLink;
938 EFI_STATUS Status;
939
940 //
941 // For Root Bridge, just copy it by RootBridgeIo proctocol
942 // so as to keep consistent with the actual attribute
943 //
944 if (!PciIoDevice->Parent) {
945 Status = PciIoDevice->PciRootBridgeIo->GetAttributes (
946 PciIoDevice->PciRootBridgeIo,
947 &PciIoDevice->Supports,
948 &PciIoDevice->Attributes
949 );
950 if (EFI_ERROR (Status)) {
951 return Status;
952 }
953 } else {
954
955 //
956 // Set the attributes to be checked for common PCI devices and PPB or P2C
957 // Since some devices only support part of them, it is better to set the
958 // attribute according to its command or bridge control register
959 //
960 Command = EFI_PCI_COMMAND_IO_SPACE |
961 EFI_PCI_COMMAND_MEMORY_SPACE |
962 EFI_PCI_COMMAND_BUS_MASTER |
963 EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;
964
965 BridgeControl = EFI_PCI_BRIDGE_CONTROL_ISA | EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_16;
966
967 //
968 // Test whether the device can support attributes above
969 //
970 PciTestSupportedAttribute (PciIoDevice, &Command, &BridgeControl, &OldCommand, &OldBridgeControl);
971
972 //
973 // Set the supported attributes for specified PCI device
974 //
975 PciSetDeviceAttribute (PciIoDevice, Command, BridgeControl, EFI_SET_SUPPORTS);
976
977 //
978 // Set the current attributes for specified PCI device
979 //
980 PciSetDeviceAttribute (PciIoDevice, OldCommand, OldBridgeControl, EFI_SET_ATTRIBUTES);
981
982 //
983 // Enable other supported attributes but not defined in PCI_IO_PROTOCOL
984 //
985 PciEnableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE);
986
987 //
988 // Enable IDE native mode
989 //
990 /*
991 if (IS_PCI_IDE(&PciIoDevice->Pci)) {
992
993 PciIo = &PciIoDevice->PciIo;
994
995 PciIoRead (
996 PciIo,
997 EfiPciIoWidthUint8,
998 0x09,
999 1,
1000 &IdePI
1001 );
1002
1003 //
1004 // Set native mode if it can be supported
1005 //
1006 IdePI |= (((IdePI & 0x0F) >> 1) & 0x05);
1007
1008 PciIoWrite (
1009 PciIo,
1010 EfiPciIoWidthUint8,
1011 0x09,
1012 1,
1013 &IdePI
1014 );
1015
1016 }
1017 */
1018 }
1019
1020 FastB2BSupport = TRUE;
1021
1022 //
1023 // P2C can not support FB2B on the secondary side
1024 //
1025 if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
1026 FastB2BSupport = FALSE;
1027 }
1028
1029 //
1030 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1031 //
1032 CurrentLink = PciIoDevice->ChildList.ForwardLink;
1033 while (CurrentLink && CurrentLink != &PciIoDevice->ChildList) {
1034
1035 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
1036 Status = DetermineDeviceAttribute (Temp);
1037 if (EFI_ERROR (Status)) {
1038 return Status;
1039 }
1040 //
1041 // Detect Fast Bact to Bact support for the device under the bridge
1042 //
1043 Status = GetFastBackToBackSupport (Temp, PCI_PRIMARY_STATUS_OFFSET);
1044 if (FastB2BSupport && EFI_ERROR (Status)) {
1045 FastB2BSupport = FALSE;
1046 }
1047
1048 CurrentLink = CurrentLink->ForwardLink;
1049 }
1050 //
1051 // Set or clear Fast Back to Back bit for the whole bridge
1052 //
1053 if (!IsListEmpty (&PciIoDevice->ChildList)) {
1054
1055 if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
1056
1057 Status = GetFastBackToBackSupport (PciIoDevice, PCI_BRIDGE_STATUS_REGISTER_OFFSET);
1058
1059 if (EFI_ERROR (Status) || (!FastB2BSupport)) {
1060 FastB2BSupport = FALSE;
1061 PciDisableBridgeControlRegister (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK);
1062 } else {
1063 PciEnableBridgeControlRegister (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK);
1064 }
1065 }
1066
1067 CurrentLink = PciIoDevice->ChildList.ForwardLink;
1068 while (CurrentLink && CurrentLink != &PciIoDevice->ChildList) {
1069 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
1070 if (FastB2BSupport) {
1071 PciEnableCommandRegister (Temp, EFI_PCI_COMMAND_FAST_BACK_TO_BACK);
1072 } else {
1073 PciDisableCommandRegister (Temp, EFI_PCI_COMMAND_FAST_BACK_TO_BACK);
1074 }
1075
1076 CurrentLink = CurrentLink->ForwardLink;
1077 }
1078 }
1079 //
1080 // End for IsListEmpty
1081 //
1082 return EFI_SUCCESS;
1083 }
1084
1085 /**
1086 This routine is used to update the bar information for those incompatible PCI device
1087
1088 @param PciIoDevice Pci device instance
1089 @return EFI_UNSUPPORTED failed to update Pci Info
1090 **/
1091 EFI_STATUS
1092 UpdatePciInfo (
1093 IN PCI_IO_DEVICE *PciIoDevice
1094 )
1095 {
1096 EFI_STATUS Status;
1097 UINTN BarIndex;
1098 UINTN BarEndIndex;
1099 BOOLEAN SetFlag;
1100 EFI_PCI_DEVICE_INFO PciDeviceInfo;
1101 VOID *Configuration;
1102 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
1103
1104 Configuration = NULL;
1105 Status = EFI_SUCCESS;
1106
1107 if (gEfiIncompatiblePciDeviceSupport == NULL) {
1108 //
1109 // It can only be supported after the Incompatible PCI Device
1110 // Support Protocol has been installed
1111 //
1112 Status = gBS->LocateProtocol (
1113 &gEfiIncompatiblePciDeviceSupportProtocolGuid,
1114 NULL,
1115 (VOID **) &gEfiIncompatiblePciDeviceSupport
1116 );
1117 }
1118 if (Status == EFI_SUCCESS) {
1119 //
1120 // Check whether the device belongs to incompatible devices from protocol or not
1121 // If it is , then get its special requirement in the ACPI table
1122 //
1123 Status = gEfiIncompatiblePciDeviceSupport->CheckDevice (
1124 gEfiIncompatiblePciDeviceSupport,
1125 PciIoDevice->Pci.Hdr.VendorId,
1126 PciIoDevice->Pci.Hdr.DeviceId,
1127 PciIoDevice->Pci.Hdr.RevisionID,
1128 PciIoDevice->Pci.Device.SubsystemVendorID,
1129 PciIoDevice->Pci.Device.SubsystemID,
1130 &Configuration
1131 );
1132
1133 }
1134
1135 if (EFI_ERROR (Status)) {
1136 //
1137 // Check whether the device belongs to incompatible devices from library or not
1138 // If it is , then get its special requirement in the ACPI table
1139 //
1140 if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT) {
1141 PciDeviceInfo.VendorID = PciIoDevice->Pci.Hdr.VendorId;
1142 PciDeviceInfo.DeviceID = PciIoDevice->Pci.Hdr.DeviceId;
1143 PciDeviceInfo.RevisionID = PciIoDevice->Pci.Hdr.RevisionID;
1144 PciDeviceInfo.SubsystemVendorID = PciIoDevice->Pci.Device.SubsystemVendorID;
1145 PciDeviceInfo.SubsystemID = PciIoDevice->Pci.Device.SubsystemID;
1146
1147 Status = PciResourceUpdateCheck (&PciDeviceInfo, &Configuration);
1148 }
1149 }
1150
1151 if (EFI_ERROR (Status)) {
1152 return EFI_UNSUPPORTED;
1153 }
1154
1155 //
1156 // Update PCI device information from the ACPI table
1157 //
1158 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
1159
1160 while (Ptr->Desc != ACPI_END_TAG_DESCRIPTOR) {
1161
1162 if (Ptr->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR) {
1163 //
1164 // The format is not support
1165 //
1166 break;
1167 }
1168
1169 BarIndex = (UINTN) Ptr->AddrTranslationOffset;
1170 BarEndIndex = BarIndex;
1171
1172 //
1173 // Update all the bars in the device
1174 //
1175 if (BarIndex == PCI_BAR_ALL) {
1176 BarIndex = 0;
1177 BarEndIndex = PCI_MAX_BAR - 1;
1178 }
1179
1180 if (BarIndex >= PCI_MAX_BAR) {
1181 Ptr++;
1182 continue;
1183 }
1184
1185 for (; BarIndex <= BarEndIndex; BarIndex++) {
1186 SetFlag = FALSE;
1187 switch (Ptr->ResType) {
1188 case ACPI_ADDRESS_SPACE_TYPE_MEM:
1189
1190 //
1191 // Make sure the bar is memory type
1192 //
1193 if (CheckBarType (PciIoDevice, (UINT8) BarIndex, PciBarTypeMem)) {
1194 SetFlag = TRUE;
1195 }
1196 break;
1197
1198 case ACPI_ADDRESS_SPACE_TYPE_IO:
1199
1200 //
1201 // Make sure the bar is IO type
1202 //
1203 if (CheckBarType (PciIoDevice, (UINT8) BarIndex, PciBarTypeIo)) {
1204 SetFlag = TRUE;
1205 }
1206 break;
1207 }
1208
1209 if (SetFlag) {
1210
1211 //
1212 // Update the new alignment for the device
1213 //
1214 SetNewAlign (&(PciIoDevice->PciBar[BarIndex].Alignment), Ptr->AddrRangeMax);
1215
1216 //
1217 // Update the new length for the device
1218 //
1219 if (Ptr->AddrLen != PCI_BAR_NOCHANGE) {
1220 PciIoDevice->PciBar[BarIndex].Length = Ptr->AddrLen;
1221 }
1222 }
1223 }
1224
1225 Ptr++;
1226 }
1227
1228 gBS->FreePool (Configuration);
1229 return Status;
1230
1231 }
1232
1233 /**
1234 This routine will update the alignment with the new alignment
1235
1236 @param Alignment old alignment
1237 @param NewAlignment new alignment
1238
1239 **/
1240 VOID
1241 SetNewAlign (
1242 IN UINT64 *Alignment,
1243 IN UINT64 NewAlignment
1244 )
1245 {
1246 UINT64 OldAlignment;
1247 UINTN ShiftBit;
1248
1249 //
1250 // The new alignment is the same as the original,
1251 // so skip it
1252 //
1253 if (NewAlignment == PCI_BAR_OLD_ALIGN) {
1254 return ;
1255 }
1256 //
1257 // Check the validity of the parameter
1258 //
1259 if (NewAlignment != PCI_BAR_EVEN_ALIGN &&
1260 NewAlignment != PCI_BAR_SQUAD_ALIGN &&
1261 NewAlignment != PCI_BAR_DQUAD_ALIGN ) {
1262 *Alignment = NewAlignment;
1263 return ;
1264 }
1265
1266 OldAlignment = (*Alignment) + 1;
1267 ShiftBit = 0;
1268
1269 //
1270 // Get the first non-zero hex value of the length
1271 //
1272 while ((OldAlignment & 0x0F) == 0x00) {
1273 OldAlignment = RShiftU64 (OldAlignment, 4);
1274 ShiftBit += 4;
1275 }
1276
1277 //
1278 // Adjust the alignment to even, quad or double quad boundary
1279 //
1280 if (NewAlignment == PCI_BAR_EVEN_ALIGN) {
1281 if (OldAlignment & 0x01) {
1282 OldAlignment = OldAlignment + 2 - (OldAlignment & 0x01);
1283 }
1284 } else if (NewAlignment == PCI_BAR_SQUAD_ALIGN) {
1285 if (OldAlignment & 0x03) {
1286 OldAlignment = OldAlignment + 4 - (OldAlignment & 0x03);
1287 }
1288 } else if (NewAlignment == PCI_BAR_DQUAD_ALIGN) {
1289 if (OldAlignment & 0x07) {
1290 OldAlignment = OldAlignment + 8 - (OldAlignment & 0x07);
1291 }
1292 }
1293
1294 //
1295 // Update the old value
1296 //
1297 NewAlignment = LShiftU64 (OldAlignment, ShiftBit) - 1;
1298 *Alignment = NewAlignment;
1299
1300 return ;
1301 }
1302
1303 /**
1304 Parse PCI bar bit.
1305
1306 @param PciIoDevice Pci device instance
1307 @param Offset bar offset
1308 @param BarIndex bar index
1309
1310 @return next bar offset.
1311 **/
1312 UINTN
1313 PciParseBar (
1314 IN PCI_IO_DEVICE *PciIoDevice,
1315 IN UINTN Offset,
1316 IN UINTN BarIndex
1317 )
1318 {
1319 UINT32 Value;
1320 UINT32 OriginalValue;
1321 UINT32 Mask;
1322 UINT32 Data;
1323 UINT8 Index;
1324 EFI_STATUS Status;
1325
1326 OriginalValue = 0;
1327 Value = 0;
1328
1329 Status = BarExisted (
1330 PciIoDevice,
1331 Offset,
1332 &Value,
1333 &OriginalValue
1334 );
1335
1336 if (EFI_ERROR (Status)) {
1337 PciIoDevice->PciBar[BarIndex].BaseAddress = 0;
1338 PciIoDevice->PciBar[BarIndex].Length = 0;
1339 PciIoDevice->PciBar[BarIndex].Alignment = 0;
1340
1341 //
1342 // Some devices don't fully comply to PCI spec 2.2. So be to scan all the BARs anyway
1343 //
1344 PciIoDevice->PciBar[BarIndex].Offset = (UINT8) Offset;
1345 return Offset + 4;
1346 }
1347
1348 PciIoDevice->PciBar[BarIndex].Offset = (UINT8) Offset;
1349 if (Value & 0x01) {
1350 //
1351 // Device I/Os
1352 //
1353 Mask = 0xfffffffc;
1354
1355 if (Value & 0xFFFF0000) {
1356 //
1357 // It is a IO32 bar
1358 //
1359 PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeIo32;
1360 PciIoDevice->PciBar[BarIndex].Length = ((~(Value & Mask)) + 1);
1361 PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
1362
1363 } else {
1364 //
1365 // It is a IO16 bar
1366 //
1367 PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeIo16;
1368 PciIoDevice->PciBar[BarIndex].Length = 0x0000FFFF & ((~(Value & Mask)) + 1);
1369 PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
1370
1371 }
1372 //
1373 // Workaround. Some platforms inplement IO bar with 0 length
1374 // Need to treat it as no-bar
1375 //
1376 if (PciIoDevice->PciBar[BarIndex].Length == 0) {
1377 PciIoDevice->PciBar[BarIndex].BarType = (PCI_BAR_TYPE) 0;
1378 }
1379
1380 PciIoDevice->PciBar[BarIndex].Prefetchable = FALSE;
1381 PciIoDevice->PciBar[BarIndex].BaseAddress = OriginalValue & Mask;
1382
1383 } else {
1384
1385 Mask = 0xfffffff0;
1386
1387 PciIoDevice->PciBar[BarIndex].BaseAddress = OriginalValue & Mask;
1388
1389 switch (Value & 0x07) {
1390
1391 //
1392 //memory space; anywhere in 32 bit address space
1393 //
1394 case 0x00:
1395 if (Value & 0x08) {
1396 PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem32;
1397 } else {
1398 PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem32;
1399 }
1400
1401 PciIoDevice->PciBar[BarIndex].Length = (~(Value & Mask)) + 1;
1402 PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
1403
1404 break;
1405
1406 //
1407 // memory space; anywhere in 64 bit address space
1408 //
1409 case 0x04:
1410 if (Value & 0x08) {
1411 PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem64;
1412 } else {
1413 PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem64;
1414 }
1415
1416 //
1417 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1418 // is regarded as an extension for the first bar. As a result
1419 // the sizing will be conducted on combined 64 bit value
1420 // Here just store the masked first 32bit value for future size
1421 // calculation
1422 //
1423 PciIoDevice->PciBar[BarIndex].Length = Value & Mask;
1424 PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
1425
1426 //
1427 // Increment the offset to point to next DWORD
1428 //
1429 Offset += 4;
1430
1431 Status = BarExisted (
1432 PciIoDevice,
1433 Offset,
1434 &Value,
1435 &OriginalValue
1436 );
1437
1438 if (EFI_ERROR (Status)) {
1439 return Offset + 4;
1440 }
1441
1442 //
1443 // Fix the length to support some spefic 64 bit BAR
1444 //
1445 Data = Value;
1446 Index = 0;
1447 for (Data = Value; Data != 0; Data >>= 1) {
1448 Index ++;
1449 }
1450 Value |= ((UINT32)(-1) << Index);
1451
1452 //
1453 // Calculate the size of 64bit bar
1454 //
1455 PciIoDevice->PciBar[BarIndex].BaseAddress |= LShiftU64 ((UINT64) OriginalValue, 32);
1456
1457 PciIoDevice->PciBar[BarIndex].Length = PciIoDevice->PciBar[BarIndex].Length | LShiftU64 ((UINT64) Value, 32);
1458 PciIoDevice->PciBar[BarIndex].Length = (~(PciIoDevice->PciBar[BarIndex].Length)) + 1;
1459 PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
1460
1461 break;
1462
1463 //
1464 // reserved
1465 //
1466 default:
1467 PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeUnknown;
1468 PciIoDevice->PciBar[BarIndex].Length = (~(Value & Mask)) + 1;
1469 PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
1470
1471 break;
1472 }
1473 }
1474
1475 //
1476 // Check the length again so as to keep compatible with some special bars
1477 //
1478 if (PciIoDevice->PciBar[BarIndex].Length == 0) {
1479 PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeUnknown;
1480 PciIoDevice->PciBar[BarIndex].BaseAddress = 0;
1481 PciIoDevice->PciBar[BarIndex].Alignment = 0;
1482 }
1483
1484 //
1485 // Increment number of bar
1486 //
1487 return Offset + 4;
1488 }
1489
1490 /**
1491 This routine is used to initialize the bar of a PCI device
1492 It can be called typically when a device is going to be rejected
1493
1494 @param PciIoDevice Pci device instance
1495 **/
1496 EFI_STATUS
1497 InitializePciDevice (
1498 IN PCI_IO_DEVICE *PciIoDevice
1499 )
1500 {
1501 EFI_PCI_IO_PROTOCOL *PciIo;
1502 UINT8 Offset;
1503
1504 PciIo = &(PciIoDevice->PciIo);
1505
1506 //
1507 // Put all the resource apertures
1508 // Resource base is set to all ones so as to indicate its resource
1509 // has not been alloacted
1510 //
1511 for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {
1512 PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);
1513 }
1514
1515 return EFI_SUCCESS;
1516 }
1517
1518 /**
1519 Init PPB for bridge device
1520
1521 @param PciIoDevice Pci device instance
1522 **/
1523 EFI_STATUS
1524 InitializePpb (
1525 IN PCI_IO_DEVICE *PciIoDevice
1526 )
1527 {
1528 EFI_PCI_IO_PROTOCOL *PciIo;
1529
1530 PciIo = &(PciIoDevice->PciIo);
1531
1532 //
1533 // Put all the resource apertures including IO16
1534 // Io32, pMem32, pMem64 to quiescent state
1535 // Resource base all ones, Resource limit all zeros
1536 //
1537 PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
1538 PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);
1539
1540 PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);
1541 PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);
1542
1543 PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);
1544 PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);
1545
1546 PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);
1547 PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);
1548
1549 //
1550 // don't support use io32 as for now
1551 //
1552 PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);
1553 PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);
1554
1555 //
1556 // Force Interrupt line to zero for cards that come up randomly
1557 //
1558 PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
1559
1560 return EFI_SUCCESS;
1561 }
1562
1563 /**
1564 Init private data for Hotplug bridge device
1565
1566 @param PciIoDevice hotplug bridge device
1567 **/
1568 EFI_STATUS
1569 InitializeP2C (
1570 IN PCI_IO_DEVICE *PciIoDevice
1571 )
1572 {
1573 EFI_PCI_IO_PROTOCOL *PciIo;
1574
1575 PciIo = &(PciIoDevice->PciIo);
1576
1577 //
1578 // Put all the resource apertures including IO16
1579 // Io32, pMem32, pMem64 to quiescent state(
1580 // Resource base all ones, Resource limit all zeros
1581 //
1582 PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);
1583 PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);
1584
1585 PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);
1586 PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);
1587
1588 PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);
1589 PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);
1590
1591 PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);
1592 PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);
1593
1594 //
1595 // Force Interrupt line to zero for cards that come up randomly
1596 //
1597 PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);
1598 return EFI_SUCCESS;
1599 }
1600
1601 /**
1602 Create and initiliaze general PCI I/O device instance for
1603 PCI device/bridge device/hotplug bridge device.
1604
1605 @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1606 @param Pci Pci bar block
1607 @param Bus device Bus NO.
1608 @param Device device device NO.
1609 @param Func device func NO.
1610
1611 @return instance of PCI device
1612 **/
1613 PCI_IO_DEVICE *
1614 CreatePciIoDevice (
1615 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
1616 IN PCI_TYPE00 *Pci,
1617 UINT8 Bus,
1618 UINT8 Device,
1619 UINT8 Func
1620 )
1621 {
1622
1623 EFI_STATUS Status;
1624 PCI_IO_DEVICE *PciIoDevice;
1625
1626 PciIoDevice = NULL;
1627
1628 Status = gBS->AllocatePool (
1629 EfiBootServicesData,
1630 sizeof (PCI_IO_DEVICE),
1631 (VOID **) &PciIoDevice
1632 );
1633
1634 if (EFI_ERROR (Status)) {
1635 return NULL;
1636 }
1637
1638 ZeroMem (PciIoDevice, sizeof (PCI_IO_DEVICE));
1639
1640 PciIoDevice->Signature = PCI_IO_DEVICE_SIGNATURE;
1641 PciIoDevice->Handle = NULL;
1642 PciIoDevice->PciRootBridgeIo = PciRootBridgeIo;
1643 PciIoDevice->DevicePath = NULL;
1644 PciIoDevice->BusNumber = Bus;
1645 PciIoDevice->DeviceNumber = Device;
1646 PciIoDevice->FunctionNumber = Func;
1647 PciIoDevice->Decodes = 0;
1648 if (gFullEnumeration) {
1649 PciIoDevice->Allocated = FALSE;
1650 } else {
1651 PciIoDevice->Allocated = TRUE;
1652 }
1653
1654 PciIoDevice->Registered = FALSE;
1655 PciIoDevice->Attributes = 0;
1656 PciIoDevice->Supports = 0;
1657 PciIoDevice->BusOverride = FALSE;
1658 PciIoDevice->AllOpRomProcessed = FALSE;
1659
1660 PciIoDevice->IsPciExp = FALSE;
1661
1662 CopyMem (&(PciIoDevice->Pci), Pci, sizeof (PCI_TYPE01));
1663
1664 //
1665 // Initialize the PCI I/O instance structure
1666 //
1667
1668 Status = InitializePciIoInstance (PciIoDevice);
1669 Status = InitializePciDriverOverrideInstance (PciIoDevice);
1670
1671 if (EFI_ERROR (Status)) {
1672 gBS->FreePool (PciIoDevice);
1673 return NULL;
1674 }
1675
1676 //
1677 // Initialize the reserved resource list
1678 //
1679 InitializeListHead (&PciIoDevice->ReservedResourceList);
1680
1681 //
1682 // Initialize the driver list
1683 //
1684 InitializeListHead (&PciIoDevice->OptionRomDriverList);
1685
1686 //
1687 // Initialize the child list
1688 //
1689 InitializeListHead (&PciIoDevice->ChildList);
1690
1691 return PciIoDevice;
1692 }
1693
1694 /**
1695 This routine is used to enumerate entire pci bus system
1696 in a given platform
1697 It is only called on the second start on the same Root Bridge.
1698
1699 @param Controller Parent bridge handler
1700
1701 @return status of operation.
1702 **/
1703 EFI_STATUS
1704 PciEnumeratorLight (
1705 IN EFI_HANDLE Controller
1706 )
1707 {
1708
1709 EFI_STATUS Status;
1710 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
1711 PCI_IO_DEVICE *RootBridgeDev;
1712 UINT16 MinBus;
1713 UINT16 MaxBus;
1714 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
1715
1716 MinBus = 0;
1717 MaxBus = PCI_MAX_BUS;
1718 Descriptors = NULL;
1719
1720 //
1721 // If this root bridge has been already enumerated, then return successfully
1722 //
1723 if (GetRootBridgeByHandle (Controller) != NULL) {
1724 return EFI_SUCCESS;
1725 }
1726
1727 //
1728 // Open pci root bridge io protocol
1729 //
1730 Status = gBS->OpenProtocol (
1731 Controller,
1732 &gEfiPciRootBridgeIoProtocolGuid,
1733 (VOID **) &PciRootBridgeIo,
1734 gPciBusDriverBinding.DriverBindingHandle,
1735 Controller,
1736 EFI_OPEN_PROTOCOL_BY_DRIVER
1737 );
1738 if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {
1739 return Status;
1740 }
1741
1742 Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **) &Descriptors);
1743
1744 if (EFI_ERROR (Status)) {
1745 return Status;
1746 }
1747
1748 while (PciGetBusRange (&Descriptors, &MinBus, &MaxBus, NULL) == EFI_SUCCESS) {
1749
1750 //
1751 // Create a device node for root bridge device with a NULL host bridge controller handle
1752 //
1753 RootBridgeDev = CreateRootBridge (Controller);
1754
1755 if (!RootBridgeDev) {
1756 Descriptors++;
1757 continue;
1758 }
1759
1760 //
1761 // Record the root bridge io protocol
1762 //
1763 RootBridgeDev->PciRootBridgeIo = PciRootBridgeIo;
1764
1765 Status = PciPciDeviceInfoCollector (
1766 RootBridgeDev,
1767 (UINT8) MinBus
1768 );
1769
1770 if (!EFI_ERROR (Status)) {
1771
1772 //
1773 // Remove those PCI devices which are rejected when full enumeration
1774 //
1775 RemoveRejectedPciDevices (RootBridgeDev->Handle, RootBridgeDev);
1776
1777 //
1778 // Process option rom light
1779 //
1780 ProcessOptionRomLight (RootBridgeDev);
1781
1782 //
1783 // Determine attributes for all devices under this root bridge
1784 //
1785 DetermineDeviceAttribute (RootBridgeDev);
1786
1787 //
1788 // If successfully, insert the node into device pool
1789 //
1790 InsertRootBridge (RootBridgeDev);
1791 } else {
1792
1793 //
1794 // If unsuccessly, destroy the entire node
1795 //
1796 DestroyRootBridge (RootBridgeDev);
1797 }
1798
1799 Descriptors++;
1800 }
1801
1802 return EFI_SUCCESS;
1803 }
1804
1805 /**
1806 Get bus range.
1807
1808 @param Descriptors A pointer to the address space descriptor.
1809 @param MinBus The min bus.
1810 @param MaxBus The max bus.
1811 @param BusRange The bus range.
1812
1813 @retval EFI_SUCCESS Success operation.
1814 @retval EFI_NOT_FOUND can not find the specific bus.
1815 **/
1816 EFI_STATUS
1817 PciGetBusRange (
1818 IN EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,
1819 OUT UINT16 *MinBus,
1820 OUT UINT16 *MaxBus,
1821 OUT UINT16 *BusRange
1822 )
1823 {
1824
1825 while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {
1826 if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {
1827 if (MinBus != NULL) {
1828 *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;
1829 }
1830
1831 if (MaxBus != NULL) {
1832 *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;
1833 }
1834
1835 if (BusRange != NULL) {
1836 *BusRange = (UINT16) (*Descriptors)->AddrLen;
1837 }
1838
1839 return EFI_SUCCESS;
1840 }
1841
1842 (*Descriptors)++;
1843 }
1844
1845 return EFI_NOT_FOUND;
1846 }
1847
1848 EFI_STATUS
1849 StartManagingRootBridge (
1850 IN PCI_IO_DEVICE *RootBridgeDev
1851 )
1852 {
1853 EFI_HANDLE RootBridgeHandle;
1854 EFI_STATUS Status;
1855 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
1856
1857 //
1858 // Get the root bridge handle
1859 //
1860 RootBridgeHandle = RootBridgeDev->Handle;
1861 PciRootBridgeIo = NULL;
1862
1863 //
1864 // Get the pci root bridge io protocol
1865 //
1866 Status = gBS->OpenProtocol (
1867 RootBridgeHandle,
1868 &gEfiPciRootBridgeIoProtocolGuid,
1869 (VOID **) &PciRootBridgeIo,
1870 gPciBusDriverBinding.DriverBindingHandle,
1871 RootBridgeHandle,
1872 EFI_OPEN_PROTOCOL_BY_DRIVER
1873 );
1874
1875 if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {
1876 return Status;
1877 }
1878
1879 //
1880 // Store the PciRootBridgeIo protocol into root bridge private data
1881 //
1882 RootBridgeDev->PciRootBridgeIo = PciRootBridgeIo;
1883
1884 return EFI_SUCCESS;
1885
1886 }
1887
1888 /**
1889 This routine can be used to check whether a PCI device should be rejected when light enumeration
1890
1891 @param PciIoDevice Pci device instance
1892
1893 @retval TRUE This device should be rejected
1894 @retval FALSE This device shouldn't be rejected
1895
1896 **/
1897 BOOLEAN
1898 IsPciDeviceRejected (
1899 IN PCI_IO_DEVICE *PciIoDevice
1900 )
1901 {
1902 EFI_STATUS Status;
1903 UINT32 TestValue;
1904 UINT32 OldValue;
1905 UINT32 Mask;
1906 UINT8 BarOffset;
1907
1908 //
1909 // PPB should be skip!
1910 //
1911 if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
1912 return FALSE;
1913 }
1914
1915 if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
1916 //
1917 // Only test base registers for P2C
1918 //
1919 for (BarOffset = 0x1C; BarOffset <= 0x38; BarOffset += 2 * sizeof (UINT32)) {
1920
1921 Mask = (BarOffset < 0x2C) ? 0xFFFFF000 : 0xFFFFFFFC;
1922 Status = BarExisted (PciIoDevice, BarOffset, &TestValue, &OldValue);
1923 if (EFI_ERROR (Status)) {
1924 continue;
1925 }
1926
1927 TestValue = TestValue & Mask;
1928 if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {
1929 //
1930 // The bar isn't programed, so it should be rejected
1931 //
1932 return TRUE;
1933 }
1934 }
1935
1936 return FALSE;
1937 }
1938
1939 for (BarOffset = 0x14; BarOffset <= 0x24; BarOffset += sizeof (UINT32)) {
1940 //
1941 // Test PCI devices
1942 //
1943 Status = BarExisted (PciIoDevice, BarOffset, &TestValue, &OldValue);
1944 if (EFI_ERROR (Status)) {
1945 continue;
1946 }
1947
1948 if (TestValue & 0x01) {
1949
1950 //
1951 // IO Bar
1952 //
1953
1954 Mask = 0xFFFFFFFC;
1955 TestValue = TestValue & Mask;
1956 if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {
1957 return TRUE;
1958 }
1959
1960 } else {
1961
1962 //
1963 // Mem Bar
1964 //
1965
1966 Mask = 0xFFFFFFF0;
1967 TestValue = TestValue & Mask;
1968
1969 if ((TestValue & 0x07) == 0x04) {
1970
1971 //
1972 // Mem64 or PMem64
1973 //
1974 BarOffset += sizeof (UINT32);
1975 if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {
1976
1977 //
1978 // Test its high 32-Bit BAR
1979 //
1980
1981 Status = BarExisted (PciIoDevice, BarOffset, &TestValue, &OldValue);
1982 if (TestValue == OldValue) {
1983 return TRUE;
1984 }
1985 }
1986
1987 } else {
1988
1989 //
1990 // Mem32 or PMem32
1991 //
1992 if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {
1993 return TRUE;
1994 }
1995 }
1996 }
1997 }
1998
1999 return FALSE;
2000 }
2001
2002 /**
2003 Reset and all bus number from specific bridge.
2004
2005 @param Bridge Parent specific bridge
2006 @param StartBusNumber start bus number
2007 **/
2008 EFI_STATUS
2009 ResetAllPpbBusNumber (
2010 IN PCI_IO_DEVICE *Bridge,
2011 IN UINT8 StartBusNumber
2012 )
2013 {
2014 EFI_STATUS Status;
2015 PCI_TYPE00 Pci;
2016 UINT8 Device;
2017 UINT32 Register;
2018 UINT8 Func;
2019 UINT64 Address;
2020 UINT8 SecondaryBus;
2021 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
2022
2023 PciRootBridgeIo = Bridge->PciRootBridgeIo;
2024
2025 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
2026 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
2027
2028 //
2029 // Check to see whether a pci device is present
2030 //
2031 Status = PciDevicePresent (
2032 PciRootBridgeIo,
2033 &Pci,
2034 StartBusNumber,
2035 Device,
2036 Func
2037 );
2038
2039 if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci))) {
2040
2041 Register = 0;
2042 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
2043 Status = PciRootBridgeIoRead (
2044 PciRootBridgeIo,
2045 &Pci,
2046 EfiPciWidthUint32,
2047 Address,
2048 1,
2049 &Register
2050 );
2051 SecondaryBus = (UINT8)(Register >> 8);
2052
2053 if (SecondaryBus != 0) {
2054 ResetAllPpbBusNumber (Bridge, SecondaryBus);
2055 }
2056
2057 //
2058 // Reset register 18h, 19h, 1Ah on PCI Bridge
2059 //
2060 Register &= 0xFF000000;
2061 Status = PciRootBridgeIoWrite (
2062 PciRootBridgeIo,
2063 &Pci,
2064 EfiPciWidthUint32,
2065 Address,
2066 1,
2067 &Register
2068 );
2069 }
2070
2071 if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
2072 //
2073 // Skip sub functions, this is not a multi function device
2074 //
2075 Func = PCI_MAX_FUNC;
2076 }
2077 }
2078 }
2079
2080 return EFI_SUCCESS;
2081 }
2082
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