3 PCI Bus Driver Lib file
4 It abstracts some functions that can be different
5 between light PCI bus driver and full PCI bus driver
7 Copyright (c) 2006, Intel Corporation
8 All rights reserved. This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL gPciHotPlugRequest
= {
21 PciHotPlugRequestNotify
26 InstallHotPlugRequestProtocol (
34 Status - A pointer to the status.
44 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport
)) {
49 *Status
= gBS
->InstallProtocolInterface (
51 &gEfiPciHotPlugRequestProtocolGuid
,
58 InstallPciHotplugGuid (
59 IN PCI_IO_DEVICE
*PciIoDevice
67 PciIoDevice - A pointer to the PCI_IO_DEVICE.
77 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport
)) {
81 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Parent
->Pci
)) {
83 Status
= gBS
->InstallProtocolInterface (
85 &gEfiPciHotplugDeviceGuid
,
89 ASSERT_EFI_ERROR (Status
);
94 UninstallPciHotplugGuid (
95 IN PCI_IO_DEVICE
*PciIoDevice
103 PciIoDevice - A pointer to the PCI_IO_DEVICE.
113 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport
)) {
117 Status
= gBS
->OpenProtocol (
119 &gEfiPciHotplugDeviceGuid
,
123 EFI_OPEN_PROTOCOL_TEST_PROTOCOL
126 if (Status
== EFI_SUCCESS
) {
128 // This may triger CardBus driver to stop for
129 // Pccard devices opened the GUID via BY_DRIVER
131 Status
= gBS
->UninstallProtocolInterface (
133 &gEfiPciHotplugDeviceGuid
,
141 IN PCI_IO_DEVICE
*PciIoDevice
150 PciIoDevice - A pointer to the PCI_IO_DEVICE.
160 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport
)) {
165 // Read PciBar information from the bar register
167 if (!gFullEnumeration
) {
171 &(PciIoDevice
->PciIo
),
178 (PciIoDevice
->PciBar
)[P2C_MEM_1
].BaseAddress
= (UINT64
) (Address
);
179 (PciIoDevice
->PciBar
)[P2C_MEM_1
].Length
= 0x2000000;
180 (PciIoDevice
->PciBar
)[P2C_MEM_1
].BarType
= PciBarTypeMem32
;
184 &(PciIoDevice
->PciIo
),
190 (PciIoDevice
->PciBar
)[P2C_MEM_2
].BaseAddress
= (UINT64
) (Address
);
191 (PciIoDevice
->PciBar
)[P2C_MEM_2
].Length
= 0x2000000;
192 (PciIoDevice
->PciBar
)[P2C_MEM_2
].BarType
= PciBarTypePMem32
;
196 &(PciIoDevice
->PciIo
),
202 (PciIoDevice
->PciBar
)[P2C_IO_1
].BaseAddress
= (UINT64
) (Address
);
203 (PciIoDevice
->PciBar
)[P2C_IO_1
].Length
= 0x100;
204 (PciIoDevice
->PciBar
)[P2C_IO_1
].BarType
= PciBarTypeIo16
;
208 &(PciIoDevice
->PciIo
),
214 (PciIoDevice
->PciBar
)[P2C_IO_2
].BaseAddress
= (UINT64
) (Address
);
215 (PciIoDevice
->PciBar
)[P2C_IO_2
].Length
= 0x100;
216 (PciIoDevice
->PciBar
)[P2C_IO_2
].BarType
= PciBarTypeIo16
;
220 if (gPciHotPlugInit
!= NULL
) {
221 GetResourcePaddingForHpb (PciIoDevice
);
226 RemoveRejectedPciDevices (
227 EFI_HANDLE RootBridgeHandle
,
228 IN PCI_IO_DEVICE
*Bridge
237 RootBridgeHandle - An efi handle.
238 Bridge - An pointer to the PCI_IO_DEVICE.
245 // TODO: EFI_SUCCESS - add return value to function comment
248 LIST_ENTRY
*CurrentLink
;
249 LIST_ENTRY
*LastLink
;
251 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport
)) {
255 CurrentLink
= Bridge
->ChildList
.ForwardLink
;
257 while (CurrentLink
&& CurrentLink
!= &Bridge
->ChildList
) {
259 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
261 if (IS_PCI_BRIDGE (&Temp
->Pci
)) {
263 // Remove rejected devices recusively
265 RemoveRejectedPciDevices (RootBridgeHandle
, Temp
);
268 // Skip rejection for all PPBs, while detect rejection for others
270 if (IsPciDeviceRejected (Temp
)) {
273 // For P2C, remove all devices on it
276 if (!IsListEmpty (&Temp
->ChildList
)) {
277 RemoveAllPciDeviceOnBridge (RootBridgeHandle
, Temp
);
281 // Finally remove itself
284 LastLink
= CurrentLink
->BackLink
;
285 RemoveEntryList (CurrentLink
);
286 FreePciDevice (Temp
);
288 CurrentLink
= LastLink
;
292 CurrentLink
= CurrentLink
->ForwardLink
;
299 PciHostBridgeResourceAllocator (
300 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
303 if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport
)) {
304 return PciHostBridgeResourceAllocator_WithHotPlugDeviceSupport (
308 return PciHostBridgeResourceAllocator_WithoutHotPlugDeviceSupport (
316 PciHostBridgeResourceAllocator_WithoutHotPlugDeviceSupport (
317 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
330 // TODO: PciResAlloc - add argument and description to function comment
331 // TODO: EFI_NOT_FOUND - add return value to function comment
332 // TODO: EFI_OUT_OF_RESOURCES - add return value to function comment
333 // TODO: EFI_NOT_FOUND - add return value to function comment
334 // TODO: EFI_SUCCESS - add return value to function comment
336 PCI_IO_DEVICE
*RootBridgeDev
;
337 EFI_HANDLE RootBridgeHandle
;
345 UINT64 MaxOptionRomSize
;
346 PCI_RESOURCE_NODE
*IoBridge
;
347 PCI_RESOURCE_NODE
*Mem32Bridge
;
348 PCI_RESOURCE_NODE
*PMem32Bridge
;
349 PCI_RESOURCE_NODE
*Mem64Bridge
;
350 PCI_RESOURCE_NODE
*PMem64Bridge
;
351 PCI_RESOURCE_NODE IoPool
;
352 PCI_RESOURCE_NODE Mem32Pool
;
353 PCI_RESOURCE_NODE PMem32Pool
;
354 PCI_RESOURCE_NODE Mem64Pool
;
355 PCI_RESOURCE_NODE PMem64Pool
;
356 EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD ExtendedData
;
359 // Initialize resource pool
362 InitializeResourcePool (&IoPool
, PciBarTypeIo16
);
363 InitializeResourcePool (&Mem32Pool
, PciBarTypeMem32
);
364 InitializeResourcePool (&PMem32Pool
, PciBarTypePMem32
);
365 InitializeResourcePool (&Mem64Pool
, PciBarTypeMem64
);
366 InitializeResourcePool (&PMem64Pool
, PciBarTypePMem64
);
368 RootBridgeDev
= NULL
;
369 RootBridgeHandle
= 0;
371 while (PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
) == EFI_SUCCESS
) {
373 // Get RootBridg Device by handle
375 RootBridgeDev
= GetRootBridgeByHandle (RootBridgeHandle
);
377 if (RootBridgeDev
== NULL
) {
378 return EFI_NOT_FOUND
;
382 // Get host bridge handle for status report
384 ExtendedData
.Handle
= RootBridgeDev
->PciRootBridgeIo
->ParentHandle
;
387 // Create the entire system resource map from the information collected by
388 // enumerator. Several resource tree was created
391 IoBridge
= CreateResourceNode (
400 Mem32Bridge
= CreateResourceNode (
409 PMem32Bridge
= CreateResourceNode (
418 Mem64Bridge
= CreateResourceNode (
427 PMem64Bridge
= CreateResourceNode (
437 // Create resourcemap by going through all the devices subject to this root bridge
439 Status
= CreateResourceMap (
449 // Get the max ROM size that the root bridge can process
451 RootBridgeDev
->RomSize
= Mem32Bridge
->Length
;
454 // Get Max Option Rom size for current root bridge
456 MaxOptionRomSize
= GetMaxOptionRomSize (RootBridgeDev
);
459 // Enlarger the mem32 resource to accomdate the option rom
460 // if the mem32 resource is not enough to hold the rom
462 if (MaxOptionRomSize
> Mem32Bridge
->Length
) {
464 Mem32Bridge
->Length
= MaxOptionRomSize
;
465 RootBridgeDev
->RomSize
= MaxOptionRomSize
;
468 // Alignment should be adjusted as well
470 if (Mem32Bridge
->Alignment
< MaxOptionRomSize
- 1) {
471 Mem32Bridge
->Alignment
= MaxOptionRomSize
- 1;
476 // Based on the all the resource tree, contruct ACPI resource node to
477 // submit the resource aperture to pci host bridge protocol
479 Status
= ConstructAcpiResourceRequestor (
490 // Insert these resource nodes into the database
492 InsertResourceNode (&IoPool
, IoBridge
);
493 InsertResourceNode (&Mem32Pool
, Mem32Bridge
);
494 InsertResourceNode (&PMem32Pool
, PMem32Bridge
);
495 InsertResourceNode (&Mem64Pool
, Mem64Bridge
);
496 InsertResourceNode (&PMem64Pool
, PMem64Bridge
);
498 if (Status
== EFI_SUCCESS
) {
500 // Submit the resource requirement
502 Status
= PciResAlloc
->SubmitResources (
504 RootBridgeDev
->Handle
,
509 // Free acpi resource node
511 if (AcpiConfig
!= NULL
) {
512 FreePool (AcpiConfig
);
515 if (EFI_ERROR (Status
)) {
517 // Destroy all the resource tree
519 DestroyResourceTree (&IoPool
);
520 DestroyResourceTree (&Mem32Pool
);
521 DestroyResourceTree (&PMem32Pool
);
522 DestroyResourceTree (&Mem64Pool
);
523 DestroyResourceTree (&PMem64Pool
);
532 // Notify pci bus driver starts to program the resource
534 Status
= NotifyPhase (PciResAlloc
, EfiPciHostBridgeAllocateResources
);
536 if (EFI_ERROR (Status
)) {
538 // Allocation failed, then return
540 return EFI_OUT_OF_RESOURCES
;
543 // Raise the EFI_IOB_PCI_RES_ALLOC status code
545 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
547 EFI_IO_BUS_PCI
| EFI_IOB_PCI_PC_RES_ALLOC
,
548 (VOID
*) &ExtendedData
,
549 sizeof (ExtendedData
)
553 // Notify pci bus driver starts to program the resource
555 NotifyPhase (PciResAlloc
, EfiPciHostBridgeSetResources
);
557 RootBridgeDev
= NULL
;
559 RootBridgeHandle
= 0;
561 while (PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
) == EFI_SUCCESS
) {
563 // Get RootBridg Device by handle
565 RootBridgeDev
= GetRootBridgeByHandle (RootBridgeHandle
);
567 if (RootBridgeDev
== NULL
) {
568 return EFI_NOT_FOUND
;
572 // Get acpi resource node for all the resource types
575 Status
= PciResAlloc
->GetProposedResources (
577 RootBridgeDev
->Handle
,
581 if (EFI_ERROR (Status
)) {
586 // Get the resource base by interpreting acpi resource node
599 // Process option rom for this root bridge
601 Status
= ProcessOptionRom (RootBridgeDev
, Mem32Base
, RootBridgeDev
->RomSize
);
604 // Create the entire system resource map from the information collected by
605 // enumerator. Several resource tree was created
607 Status
= GetResourceMap (
621 if (EFI_ERROR (Status
)) {
626 // Program IO resources
634 // Program Mem32 resources
642 // Program PMem32 resources
650 // Program Mem64 resources
658 // Program PMem64 resources
665 if (AcpiConfig
!= NULL
) {
666 FreePool (AcpiConfig
);
671 // Destroy all the resource tree
673 DestroyResourceTree (&IoPool
);
674 DestroyResourceTree (&Mem32Pool
);
675 DestroyResourceTree (&PMem32Pool
);
676 DestroyResourceTree (&Mem64Pool
);
677 DestroyResourceTree (&PMem64Pool
);
680 // Notify the resource allocation phase is to end
682 NotifyPhase (PciResAlloc
, EfiPciHostBridgeEndResourceAllocation
);
689 PciHostBridgeResourceAllocator_WithHotPlugDeviceSupport (
690 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
696 Host brige resource allocator.
700 PciResAlloc - A pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
707 // TODO: EFI_NOT_FOUND - add return value to function comment
708 // TODO: EFI_NOT_FOUND - add return value to function comment
709 // TODO: EFI_NOT_FOUND - add return value to function comment
710 // TODO: EFI_SUCCESS - add return value to function comment
712 PCI_IO_DEVICE
*RootBridgeDev
;
713 EFI_HANDLE RootBridgeHandle
;
722 UINT64 Mem32ResStatus
;
723 UINT64 PMem32ResStatus
;
724 UINT64 Mem64ResStatus
;
725 UINT64 PMem64ResStatus
;
726 UINT64 MaxOptionRomSize
;
727 PCI_RESOURCE_NODE
*IoBridge
;
728 PCI_RESOURCE_NODE
*Mem32Bridge
;
729 PCI_RESOURCE_NODE
*PMem32Bridge
;
730 PCI_RESOURCE_NODE
*Mem64Bridge
;
731 PCI_RESOURCE_NODE
*PMem64Bridge
;
732 PCI_RESOURCE_NODE IoPool
;
733 PCI_RESOURCE_NODE Mem32Pool
;
734 PCI_RESOURCE_NODE PMem32Pool
;
735 PCI_RESOURCE_NODE Mem64Pool
;
736 PCI_RESOURCE_NODE PMem64Pool
;
738 EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD HandleExtendedData
;
739 EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData
;
747 // It will try several times if the resource allocation fails
752 // Initialize resource pool
754 InitializeResourcePool (&IoPool
, PciBarTypeIo16
);
755 InitializeResourcePool (&Mem32Pool
, PciBarTypeMem32
);
756 InitializeResourcePool (&PMem32Pool
, PciBarTypePMem32
);
757 InitializeResourcePool (&Mem64Pool
, PciBarTypeMem64
);
758 InitializeResourcePool (&PMem64Pool
, PciBarTypePMem64
);
760 RootBridgeDev
= NULL
;
761 RootBridgeHandle
= 0;
763 while (PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
) == EFI_SUCCESS
) {
766 // Get RootBridg Device by handle
768 RootBridgeDev
= GetRootBridgeByHandle (RootBridgeHandle
);
770 if (RootBridgeDev
== NULL
) {
771 return EFI_NOT_FOUND
;
775 // Create the entire system resource map from the information collected by
776 // enumerator. Several resource tree was created
779 IoBridge
= CreateResourceNode (
788 Mem32Bridge
= CreateResourceNode (
797 PMem32Bridge
= CreateResourceNode (
806 Mem64Bridge
= CreateResourceNode (
815 PMem64Bridge
= CreateResourceNode (
825 // Create resourcemap by going through all the devices subject to this root bridge
827 Status
= CreateResourceMap (
837 // Get the max ROM size that the root bridge can process
839 RootBridgeDev
->RomSize
= Mem32Bridge
->Length
;
842 // Skip to enlarge the resource request during realloction
846 // Get Max Option Rom size for current root bridge
848 MaxOptionRomSize
= GetMaxOptionRomSize (RootBridgeDev
);
851 // Enlarger the mem32 resource to accomdate the option rom
852 // if the mem32 resource is not enough to hold the rom
854 if (MaxOptionRomSize
> Mem32Bridge
->Length
) {
856 Mem32Bridge
->Length
= MaxOptionRomSize
;
857 RootBridgeDev
->RomSize
= MaxOptionRomSize
;
860 // Alignment should be adjusted as well
862 if (Mem32Bridge
->Alignment
< MaxOptionRomSize
- 1) {
863 Mem32Bridge
->Alignment
= MaxOptionRomSize
- 1;
869 // Based on the all the resource tree, contruct ACPI resource node to
870 // submit the resource aperture to pci host bridge protocol
872 Status
= ConstructAcpiResourceRequestor (
883 // Insert these resource nodes into the database
885 InsertResourceNode (&IoPool
, IoBridge
);
886 InsertResourceNode (&Mem32Pool
, Mem32Bridge
);
887 InsertResourceNode (&PMem32Pool
, PMem32Bridge
);
888 InsertResourceNode (&Mem64Pool
, Mem64Bridge
);
889 InsertResourceNode (&PMem64Pool
, PMem64Bridge
);
891 if (Status
== EFI_SUCCESS
) {
893 // Submit the resource requirement
895 Status
= PciResAlloc
->SubmitResources (
897 RootBridgeDev
->Handle
,
903 // Free acpi resource node
905 if (AcpiConfig
!= NULL
) {
906 FreePool (AcpiConfig
);
909 if (EFI_ERROR (Status
)) {
911 // Destroy all the resource tree
913 DestroyResourceTree (&IoPool
);
914 DestroyResourceTree (&Mem32Pool
);
915 DestroyResourceTree (&PMem32Pool
);
916 DestroyResourceTree (&Mem64Pool
);
917 DestroyResourceTree (&PMem64Pool
);
923 // Notify pci bus driver starts to program the resource
926 Status
= NotifyPhase (PciResAlloc
, EfiPciHostBridgeAllocateResources
);
928 if (!EFI_ERROR (Status
)) {
930 // Allocation succeed, then continue the following
936 // If the resource allocation is unsuccessful, free resources on bridge
939 RootBridgeDev
= NULL
;
940 RootBridgeHandle
= 0;
942 IoResStatus
= EFI_RESOURCE_SATISFIED
;
943 Mem32ResStatus
= EFI_RESOURCE_SATISFIED
;
944 PMem32ResStatus
= EFI_RESOURCE_SATISFIED
;
945 Mem64ResStatus
= EFI_RESOURCE_SATISFIED
;
946 PMem64ResStatus
= EFI_RESOURCE_SATISFIED
;
948 while (PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
) == EFI_SUCCESS
) {
950 // Get RootBridg Device by handle
952 RootBridgeDev
= GetRootBridgeByHandle (RootBridgeHandle
);
953 if (RootBridgeDev
== NULL
) {
954 return EFI_NOT_FOUND
;
958 // Get host bridge handle for status report
960 HandleExtendedData
.Handle
= RootBridgeDev
->PciRootBridgeIo
->ParentHandle
;
963 // Get acpi resource node for all the resource types
967 Status
= PciResAlloc
->GetProposedResources (
969 RootBridgeDev
->Handle
,
973 if (EFI_ERROR (Status
)) {
977 if (AcpiConfig
!= NULL
) {
979 // Adjust resource allocation policy for each RB
981 GetResourceAllocationStatus (
989 FreePool (AcpiConfig
);
997 // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code
1000 // It is very difficult to follow the spec here
1001 // Device path , Bar index can not be get here
1003 ZeroMem (&AllocFailExtendedData
, sizeof (AllocFailExtendedData
));
1005 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
1007 EFI_IO_BUS_PCI
| EFI_IOB_EC_RESOURCE_CONFLICT
,
1008 (VOID
*) &AllocFailExtendedData
,
1009 sizeof (AllocFailExtendedData
)
1012 Status
= PciHostBridgeAdjustAllocation (
1026 // Destroy all the resource tree
1028 DestroyResourceTree (&IoPool
);
1029 DestroyResourceTree (&Mem32Pool
);
1030 DestroyResourceTree (&PMem32Pool
);
1031 DestroyResourceTree (&Mem64Pool
);
1032 DestroyResourceTree (&PMem64Pool
);
1034 NotifyPhase (PciResAlloc
, EfiPciHostBridgeFreeResources
);
1036 if (EFI_ERROR (Status
)) {
1048 // Raise the EFI_IOB_PCI_RES_ALLOC status code
1050 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
1052 EFI_IO_BUS_PCI
| EFI_IOB_PCI_PC_RES_ALLOC
,
1053 (VOID
*) &HandleExtendedData
,
1054 sizeof (HandleExtendedData
)
1058 // Notify pci bus driver starts to program the resource
1060 NotifyPhase (PciResAlloc
, EfiPciHostBridgeSetResources
);
1062 RootBridgeDev
= NULL
;
1064 RootBridgeHandle
= 0;
1066 while (PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
) == EFI_SUCCESS
) {
1069 // Get RootBridg Device by handle
1071 RootBridgeDev
= GetRootBridgeByHandle (RootBridgeHandle
);
1073 if (RootBridgeDev
== NULL
) {
1074 return EFI_NOT_FOUND
;
1078 // Get acpi resource node for all the resource types
1081 Status
= PciResAlloc
->GetProposedResources (
1083 RootBridgeDev
->Handle
,
1087 if (EFI_ERROR (Status
)) {
1092 // Get the resource base by interpreting acpi resource node
1105 // Process option rom for this root bridge
1107 Status
= ProcessOptionRom (RootBridgeDev
, Mem32Base
, RootBridgeDev
->RomSize
);
1110 // Create the entire system resource map from the information collected by
1111 // enumerator. Several resource tree was created
1113 Status
= GetResourceMap (
1127 if (EFI_ERROR (Status
)) {
1132 // Program IO resources
1140 // Program Mem32 resources
1148 // Program PMem32 resources
1156 // Program Mem64 resources
1164 // Program PMem64 resources
1171 if (AcpiConfig
!= NULL
) {
1172 gBS
->FreePool (AcpiConfig
);
1177 // Destroy all the resource tree
1179 DestroyResourceTree (&IoPool
);
1180 DestroyResourceTree (&Mem32Pool
);
1181 DestroyResourceTree (&PMem32Pool
);
1182 DestroyResourceTree (&Mem64Pool
);
1183 DestroyResourceTree (&PMem64Pool
);
1186 // Notify the resource allocation phase is to end
1188 NotifyPhase (PciResAlloc
, EfiPciHostBridgeEndResourceAllocation
);
1196 IN PCI_IO_DEVICE
*Bridge
,
1197 IN UINT8 StartBusNumber
,
1198 OUT UINT8
*SubBusNumber
,
1199 OUT UINT8
*PaddedBusRange
1202 if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport
)) {
1203 return PciScanBus_WithHotPlugDeviceSupport (
1210 return PciScanBus_WithoutHotPlugDeviceSupport (
1221 PciScanBus_WithoutHotPlugDeviceSupport (
1222 IN PCI_IO_DEVICE
*Bridge
,
1223 IN UINT8 StartBusNumber
,
1224 OUT UINT8
*SubBusNumber
,
1225 OUT UINT8
*PaddedBusRange
1229 Routine Description:
1231 This routine is used to assign bus number to the given PCI bus system
1240 // TODO: Bridge - add argument and description to function comment
1241 // TODO: StartBusNumber - add argument and description to function comment
1242 // TODO: SubBusNumber - add argument and description to function comment
1243 // TODO: PaddedBusRange - add argument and description to function comment
1244 // TODO: EFI_DEVICE_ERROR - add return value to function comment
1245 // TODO: EFI_SUCCESS - add return value to function comment
1254 PCI_IO_DEVICE
*PciDevice
;
1255 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
1257 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
1261 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
1262 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
1265 // Check to see whether a pci device is present
1267 Status
= PciDevicePresent (
1275 if (!EFI_ERROR (Status
) &&
1276 (IS_PCI_BRIDGE (&Pci
) ||
1277 IS_CARDBUS_BRIDGE (&Pci
))) {
1279 DEBUG((EFI_D_ERROR
, "Found DEV(%02d,%02d,%02d)\n", StartBusNumber
, Device
, Func
));
1282 // Get the bridge information
1284 Status
= PciSearchDevice (
1293 if (EFI_ERROR (Status
)) {
1298 // Add feature to support customized secondary bus number
1300 if (*SubBusNumber
== 0) {
1301 *SubBusNumber
= *PaddedBusRange
;
1302 *PaddedBusRange
= 0;
1307 SecondBus
= (*SubBusNumber
);
1309 Register
= (UINT16
) ((SecondBus
<< 8) | (UINT16
) StartBusNumber
);
1311 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x18);
1313 Status
= PciRootBridgeIoWrite (
1323 // Initialize SubBusNumber to SecondBus
1325 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x1A);
1326 Status
= PciRootBridgeIoWrite (
1335 // If it is PPB, resursively search down this bridge
1337 if (IS_PCI_BRIDGE (&Pci
)) {
1339 // Temporarily initialize SubBusNumber to maximum bus number to ensure the
1340 // PCI configuration transaction to go through any PPB
1342 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x1A);
1344 Status
= PciRootBridgeIoWrite (
1353 PreprocessController (
1355 PciDevice
->BusNumber
,
1356 PciDevice
->DeviceNumber
,
1357 PciDevice
->FunctionNumber
,
1358 EfiPciBeforeChildBusEnumeration
1361 DEBUG((EFI_D_ERROR
, "Scan PPB(%02d,%02d,%02d)\n", PciDevice
->BusNumber
, PciDevice
->DeviceNumber
,PciDevice
->FunctionNumber
));
1362 Status
= PciScanBus (
1364 (UINT8
) (SecondBus
),
1369 if (EFI_ERROR (Status
)) {
1370 return EFI_DEVICE_ERROR
;
1375 // Set the current maximum bus number under the PPB
1378 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x1A);
1380 Status
= PciRootBridgeIoWrite (
1391 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
1394 // Skip sub functions, this is not a multi function device
1397 Func
= PCI_MAX_FUNC
;
1406 PciScanBus_WithHotPlugDeviceSupport (
1407 IN PCI_IO_DEVICE
*Bridge
,
1408 IN UINT8 StartBusNumber
,
1409 OUT UINT8
*SubBusNumber
,
1410 OUT UINT8
*PaddedBusRange
1414 Routine Description:
1416 This routine is used to assign bus number to the given PCI bus system
1420 Bridge - A pointer to the PCI_IO_DEVICE structure.
1421 StartBusNumber - The start bus number.
1422 SubBusNumber - A pointer to the sub bus number.
1423 PaddedBusRange - A pointer to the padded bus range.
1430 // TODO: EFI_DEVICE_ERROR - add return value to function comment
1431 // TODO: EFI_SUCCESS - add return value to function comment
1441 PCI_IO_DEVICE
*PciDevice
;
1443 EFI_HPC_STATE State
;
1445 EFI_HPC_PADDING_ATTRIBUTES Attributes
;
1446 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
1448 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
1451 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
1455 Attributes
= (EFI_HPC_PADDING_ATTRIBUTES
) 0;
1458 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
1459 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
1462 // Check to see whether a pci device is present
1464 Status
= PciDevicePresent (
1472 if (EFI_ERROR (Status
)) {
1475 // Skip sub functions, this is not a multi function device
1477 Func
= PCI_MAX_FUNC
;
1483 DEBUG((EFI_D_ERROR
, "Found DEV(%02d,%02d,%02d)\n", StartBusNumber
, Device
, Func
));
1486 // Get the PCI device information
1488 Status
= PciSearchDevice (
1497 ASSERT (!EFI_ERROR (Status
));
1499 PciAddress
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0);
1501 if (!IS_PCI_BRIDGE (&Pci
)) {
1503 // PCI bridges will be called later
1504 // Here just need for PCI device or PCI to cardbus controller
1505 // EfiPciBeforeChildBusEnumeration for PCI Device Node
1507 PreprocessController (
1509 PciDevice
->BusNumber
,
1510 PciDevice
->DeviceNumber
,
1511 PciDevice
->FunctionNumber
,
1512 EfiPciBeforeChildBusEnumeration
1517 // For Pci Hotplug controller devcie only
1519 if (gPciHotPlugInit
!= NULL
) {
1521 // Check if it is a Hotplug PCI controller
1523 if (IsRootPciHotPlugController (PciDevice
->DevicePath
, &HpIndex
)) {
1525 if (!gPciRootHpcData
[HpIndex
].Initialized
) {
1527 Status
= CreateEventForHpc (HpIndex
, &Event
);
1529 ASSERT (!EFI_ERROR (Status
));
1531 Status
= gPciHotPlugInit
->InitializeRootHpc (
1533 gPciRootHpcPool
[HpIndex
].HpcDevicePath
,
1539 PreprocessController (
1541 PciDevice
->BusNumber
,
1542 PciDevice
->DeviceNumber
,
1543 PciDevice
->FunctionNumber
,
1544 EfiPciBeforeChildBusEnumeration
1550 if (IS_PCI_BRIDGE (&Pci
) || IS_CARDBUS_BRIDGE (&Pci
)) {
1553 // Get the bridge information
1556 if (gPciHotPlugInit
!= NULL
) {
1558 if (IsRootPciHotPlugBus (PciDevice
->DevicePath
, &HpIndex
)) {
1561 // If it is initialized, get the padded bus range
1563 Status
= gPciHotPlugInit
->GetResourcePadding (
1565 gPciRootHpcPool
[HpIndex
].HpbDevicePath
,
1568 (VOID
**) &Descriptors
,
1572 if (EFI_ERROR (Status
)) {
1577 Status
= PciGetBusRange (
1584 gBS
->FreePool (Descriptors
);
1586 if (EFI_ERROR (Status
)) {
1595 // Add feature to support customized secondary bus number
1597 if (*SubBusNumber
== 0) {
1598 *SubBusNumber
= *PaddedBusRange
;
1599 *PaddedBusRange
= 0;
1603 SecondBus
= *SubBusNumber
;
1605 Register
= (UINT16
) ((SecondBus
<< 8) | (UINT16
) StartBusNumber
);
1606 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x18);
1608 Status
= PciRootBridgeIoWrite (
1619 // If it is PPB, resursively search down this bridge
1621 if (IS_PCI_BRIDGE (&Pci
)) {
1624 // Initialize SubBusNumber to Maximum bus number
1627 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x1A);
1628 Status
= PciRootBridgeIoWrite (
1638 // Nofify EfiPciBeforeChildBusEnumeration for PCI Brige
1640 PreprocessController (
1642 PciDevice
->BusNumber
,
1643 PciDevice
->DeviceNumber
,
1644 PciDevice
->FunctionNumber
,
1645 EfiPciBeforeChildBusEnumeration
1648 DEBUG((EFI_D_ERROR
, "Scan PPB(%02d,%02d,%02d)\n", PciDevice
->BusNumber
, PciDevice
->DeviceNumber
,PciDevice
->FunctionNumber
));
1649 Status
= PciScanBus (
1651 (UINT8
) (SecondBus
),
1656 if (EFI_ERROR (Status
)) {
1657 return EFI_DEVICE_ERROR
;
1663 // Ensure the device is enabled and initialized
1665 if ((Attributes
== EfiPaddingPciRootBridge
) &&
1666 (State
& EFI_HPC_STATE_ENABLED
) &&
1667 (State
& EFI_HPC_STATE_INITIALIZED
) ) {
1668 *PaddedBusRange
= (UINT8
) ((UINT8
) (BusRange
) +*PaddedBusRange
);
1670 *SubBusNumber
= (UINT8
) ((UINT8
) (BusRange
) +*SubBusNumber
);
1675 // Set the current maximum bus number under the PPB
1677 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x1A);
1679 Status
= PciRootBridgeIoWrite (
1689 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
1692 // Skip sub functions, this is not a multi function device
1694 Func
= PCI_MAX_FUNC
;
1704 PciRootBridgeP2CProcess (
1705 IN PCI_IO_DEVICE
*Bridge
1709 Routine Description:
1711 Process Option Rom on this host bridge
1720 // TODO: Bridge - add argument and description to function comment
1721 // TODO: EFI_SUCCESS - add return value to function comment
1723 LIST_ENTRY
*CurrentLink
;
1724 PCI_IO_DEVICE
*Temp
;
1725 EFI_HPC_STATE State
;
1729 CurrentLink
= Bridge
->ChildList
.ForwardLink
;
1731 while (CurrentLink
&& CurrentLink
!= &Bridge
->ChildList
) {
1733 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1735 if (IS_CARDBUS_BRIDGE (&Temp
->Pci
)) {
1737 if (gPciHotPlugInit
&& Temp
->Allocated
) {
1740 // Raise the EFI_IOB_PCI_HPC_INIT status code
1742 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1744 EFI_IO_BUS_PCI
| EFI_IOB_PCI_PC_HPC_INIT
,
1748 PciAddress
= EFI_PCI_ADDRESS (Temp
->BusNumber
, Temp
->DeviceNumber
, Temp
->FunctionNumber
, 0);
1749 Status
= gPciHotPlugInit
->InitializeRootHpc (
1757 if (!EFI_ERROR (Status
)) {
1758 Status
= PciBridgeEnumerator (Temp
);
1760 if (EFI_ERROR (Status
)) {
1765 CurrentLink
= CurrentLink
->ForwardLink
;
1771 if (!IsListEmpty (&Temp
->ChildList
)) {
1772 Status
= PciRootBridgeP2CProcess (Temp
);
1775 CurrentLink
= CurrentLink
->ForwardLink
;
1782 PciHostBridgeP2CProcess (
1783 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
1787 Routine Description:
1796 // TODO: PciResAlloc - add argument and description to function comment
1797 // TODO: EFI_NOT_FOUND - add return value to function comment
1798 // TODO: EFI_SUCCESS - add return value to function comment
1800 EFI_HANDLE RootBridgeHandle
;
1801 PCI_IO_DEVICE
*RootBridgeDev
;
1804 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport
)) {
1808 RootBridgeHandle
= NULL
;
1810 while (PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
) == EFI_SUCCESS
) {
1813 // Get RootBridg Device by handle
1815 RootBridgeDev
= GetRootBridgeByHandle (RootBridgeHandle
);
1817 if (RootBridgeDev
== NULL
) {
1818 return EFI_NOT_FOUND
;
1821 Status
= PciRootBridgeP2CProcess (RootBridgeDev
);
1823 if (EFI_ERROR (Status
)) {
1833 PciHostBridgeEnumerator (
1834 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
*PciResAlloc
1838 Routine Description:
1840 This function is used to enumerate the entire host bridge
1845 PciResAlloc - A pointer to the resource allocate protocol.
1852 // TODO: EFI_OUT_OF_RESOURCES - add return value to function comment
1853 // TODO: EFI_OUT_OF_RESOURCES - add return value to function comment
1854 // TODO: EFI_OUT_OF_RESOURCES - add return value to function comment
1855 // TODO: EFI_SUCCESS - add return value to function comment
1857 EFI_HANDLE RootBridgeHandle
;
1858 PCI_IO_DEVICE
*RootBridgeDev
;
1860 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
1862 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
1864 InitializeHotPlugSupport ();
1867 // Notify the bus allocation phase is about to start
1869 NotifyPhase (PciResAlloc
, EfiPciHostBridgeBeginBusAllocation
);
1871 DEBUG((EFI_D_ERROR
, "PCI Bus First Scanning\n"));
1872 RootBridgeHandle
= NULL
;
1873 while (PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
) == EFI_SUCCESS
) {
1876 // if a root bridge instance is found, create root bridge device for it
1879 RootBridgeDev
= CreateRootBridge (RootBridgeHandle
);
1881 if (RootBridgeDev
== NULL
) {
1882 return EFI_OUT_OF_RESOURCES
;
1886 // Enumerate all the buses under this root bridge
1889 Status
= PciRootBridgeEnumerator (
1894 DestroyRootBridge (RootBridgeDev
);
1895 if (EFI_ERROR (Status
)) {
1901 // Notify the bus allocation phase is finished for the first time
1903 NotifyPhase (PciResAlloc
, EfiPciHostBridgeEndBusAllocation
);
1905 if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport
)) {
1907 if (gPciHotPlugInit
!= NULL
) {
1909 // Wait for all HPC initialized
1911 Status
= AllRootHPCInitialized (STALL_1_SECOND
* 15);
1913 if (EFI_ERROR (Status
)) {
1918 // Notify the bus allocation phase is about to start for the 2nd time
1920 NotifyPhase (PciResAlloc
, EfiPciHostBridgeBeginBusAllocation
);
1922 DEBUG((EFI_D_ERROR
, "PCI Bus Second Scanning\n"));
1923 RootBridgeHandle
= NULL
;
1924 while (PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
) == EFI_SUCCESS
) {
1927 // if a root bridge instance is found, create root bridge device for it
1930 RootBridgeDev
= CreateRootBridge (RootBridgeHandle
);
1932 if (RootBridgeDev
== NULL
) {
1933 return EFI_OUT_OF_RESOURCES
;
1937 // Enumerate all the buses under this root bridge
1940 Status
= PciRootBridgeEnumerator (
1945 DestroyRootBridge (RootBridgeDev
);
1946 if (EFI_ERROR (Status
)) {
1952 // Notify the bus allocation phase is to end for the 2nd time
1954 NotifyPhase (PciResAlloc
, EfiPciHostBridgeEndBusAllocation
);
1959 // Notify the resource allocation phase is to start
1961 NotifyPhase (PciResAlloc
, EfiPciHostBridgeBeginResourceAllocation
);
1963 RootBridgeHandle
= NULL
;
1964 while (PciResAlloc
->GetNextRootBridge (PciResAlloc
, &RootBridgeHandle
) == EFI_SUCCESS
) {
1967 // if a root bridge instance is found, create root bridge device for it
1970 RootBridgeDev
= CreateRootBridge (RootBridgeHandle
);
1972 if (RootBridgeDev
== NULL
) {
1973 return EFI_OUT_OF_RESOURCES
;
1976 Status
= StartManagingRootBridge (RootBridgeDev
);
1978 if (EFI_ERROR (Status
)) {
1982 PciRootBridgeIo
= RootBridgeDev
->PciRootBridgeIo
;
1983 Status
= PciRootBridgeIo
->Configuration (PciRootBridgeIo
, (VOID
**) &Descriptors
);
1985 if (EFI_ERROR (Status
)) {
1989 Status
= PciGetBusRange (&Descriptors
, &MinBus
, NULL
, NULL
);
1991 if (EFI_ERROR (Status
)) {
1996 // Determine root bridge attribute by calling interface of Pcihostbridge
1999 DetermineRootBridgeAttributes (
2005 // Collect all the resource information under this root bridge
2006 // A database that records all the information about pci device subject to this
2007 // root bridge will then be created
2009 Status
= PciPciDeviceInfoCollector (
2014 if (EFI_ERROR (Status
)) {
2018 InsertRootBridge (RootBridgeDev
);
2021 // Record the hostbridge handle
2023 AddHostBridgeEnumerator (RootBridgeDev
->PciRootBridgeIo
->ParentHandle
);
2030 Read PCI device configuration register by specified address.
2032 This function check the incompatiblilites on PCI device. Return the register
2035 @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
2036 @param PciIo A pointer to EFI_PCI_PROTOCOL.
2037 @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
2038 @param Width Signifies the width of the memory operations.
2039 @Param Address The address within the PCI configuration space for the PCI controller.
2040 @param Buffer For read operations, the destination buffer to store the results. For
2041 write operations, the source buffer to write data from.
2043 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
2044 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
2045 @retval EFI_INVALID_PARAMETER Buffer is NULL.
2046 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
2052 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
, OPTIONAL
2053 IN EFI_PCI_IO_PROTOCOL
*PciIo
, OPTIONAL
2054 IN EFI_PCI_DEVICE_INFO
*PciDeviceInfo
,
2062 EFI_PCI_REGISTER_ACCESS_DATA
*PciRegisterAccessData
;
2063 UINT64 AccessAddress
;
2068 ASSERT ((PciRootBridgeIo
== NULL
) ^ (PciIo
== NULL
));
2070 if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask
) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT
) {
2072 // check access compatibility at first time
2074 Status
= PciRegisterAccessCheck (PciDeviceInfo
, PCI_REGISTER_READ
, Address
& 0xff, Width
, &PciRegisterAccessData
);
2076 if (Status
== EFI_SUCCESS
) {
2078 // there exist incompatibility on this operation
2080 AccessWidth
= Width
;
2082 if (PciRegisterAccessData
->Width
!= VALUE_NOCARE
) {
2083 AccessWidth
= PciRegisterAccessData
->Width
;
2086 AccessAddress
= Address
& ~((1 << AccessWidth
) - 1);
2090 Pointer
= (UINT8
*) &TempBuffer
;
2094 if (PciRootBridgeIo
!= NULL
) {
2095 Status
= PciRootBridgeIo
->Pci
.Read (
2097 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) AccessWidth
,
2102 } else if (PciIo
!= NULL
) {
2103 Status
= PciIo
->Pci
.Read (
2105 (EFI_PCI_IO_PROTOCOL_WIDTH
) AccessWidth
,
2106 (UINT32
) AccessAddress
,
2112 if (Status
!= EFI_SUCCESS
) {
2116 Stride
= (UINTN
)1 << AccessWidth
;
2117 AccessAddress
+= Stride
;
2118 if (AccessAddress
>= (Address
+ LShiftU64 (1ULL, (UINTN
)Width
))) {
2120 // if all datas have been read, exist
2127 if ((AccessAddress
& 0xff) < PciRegisterAccessData
->EndOffset
) {
2129 // if current offset doesn't reach the end
2134 FreePool (PciRegisterAccessData
);
2137 // continue checking access incompatibility
2139 Status
= PciRegisterAccessCheck (PciDeviceInfo
, PCI_REGISTER_READ
, AccessAddress
& 0xff, AccessWidth
, &PciRegisterAccessData
);
2140 if (Status
== EFI_SUCCESS
) {
2141 if (PciRegisterAccessData
->Width
!= VALUE_NOCARE
) {
2142 AccessWidth
= PciRegisterAccessData
->Width
;
2147 FreePool (PciRegisterAccessData
);
2150 case EfiPciWidthUint8
:
2151 * (UINT8
*) Buffer
= (UINT8
) TempBuffer
;
2153 case EfiPciWidthUint16
:
2154 * (UINT16
*) Buffer
= (UINT16
) TempBuffer
;
2156 case EfiPciWidthUint32
:
2157 * (UINT32
*) Buffer
= (UINT32
) TempBuffer
;
2160 return EFI_UNSUPPORTED
;
2167 // AccessWidth incompatible check not supportted
2168 // or, there doesn't exist incompatibility on this operation
2170 if (PciRootBridgeIo
!= NULL
) {
2171 Status
= PciRootBridgeIo
->Pci
.Read (
2173 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) Width
,
2180 Status
= PciIo
->Pci
.Read (
2182 (EFI_PCI_IO_PROTOCOL_WIDTH
) Width
,
2193 Update register value by checking PCI device incompatibility.
2195 This function check register value incompatibilites on PCI device. Return the register
2198 @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
2199 @param AccessType Access type, READ or WRITE.
2200 @Param Address The address within the PCI configuration space.
2201 @param Buffer Store the register data.
2203 @retval EFI_SUCCESS The data has been updated.
2209 IN EFI_PCI_DEVICE_INFO
*PciDeviceInfo
,
2210 IN UINT64 AccessType
,
2217 EFI_PCI_REGISTER_VALUE_DATA
*PciRegisterData
;
2223 // check register value incompatibility
2225 Status
= PciRegisterUpdateCheck (PciDeviceInfo
, AccessType
, Address
& 0xff, &PciRegisterData
);
2227 if (Status
== EFI_SUCCESS
) {
2229 AndValue
= ((UINT32
) PciRegisterData
->AndValue
) >> (((UINT8
) Address
& 0x3) * 8);
2230 OrValue
= ((UINT32
) PciRegisterData
->OrValue
) >> (((UINT8
) Address
& 0x3) * 8);
2232 TempValue
= * (UINT32
*) Buffer
;
2233 if (PciRegisterData
->AndValue
!= VALUE_NOCARE
) {
2234 TempValue
&= AndValue
;
2236 if (PciRegisterData
->OrValue
!= VALUE_NOCARE
) {
2237 TempValue
|= OrValue
;
2241 case EfiPciWidthUint8
:
2242 *(UINT8
*)Buffer
= (UINT8
) TempValue
;
2245 case EfiPciWidthUint16
:
2246 *(UINT16
*)Buffer
= (UINT16
) TempValue
;
2248 case EfiPciWidthUint32
:
2249 *(UINT32
*)Buffer
= TempValue
;
2253 return EFI_UNSUPPORTED
;
2256 FreePool (PciRegisterData
);
2263 Write PCI device configuration register by specified address.
2265 This function check the incompatiblilites on PCI device, and write date
2268 @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
2269 @param PciIo A pointer to EFI_PCI_PROTOCOL.
2270 @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
2271 @param Width Signifies the width of the memory operations.
2272 @Param Address The address within the PCI configuration space for the PCI controller.
2273 @param Buffer For read operations, the destination buffer to store the results. For
2274 write operations, the source buffer to write data from.
2276 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
2277 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
2278 @retval EFI_INVALID_PARAMETER Buffer is NULL.
2279 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
2285 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
, OPTIONAL
2286 IN EFI_PCI_IO_PROTOCOL
*PciIo
, OPTIONAL
2287 IN EFI_PCI_DEVICE_INFO
*PciDeviceInfo
,
2295 EFI_PCI_REGISTER_ACCESS_DATA
*PciRegisterAccessData
;
2296 UINT64 AccessAddress
;
2302 ASSERT ((PciRootBridgeIo
== NULL
) ^ (PciIo
== NULL
));
2304 if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask
) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT
) {
2306 // check access compatibility at first time
2308 Status
= PciRegisterAccessCheck (PciDeviceInfo
, PCI_REGISTER_WRITE
, Address
& 0xff, Width
, &PciRegisterAccessData
);
2310 if (Status
== EFI_SUCCESS
) {
2312 // there exist incompatibility on this operation
2314 AccessWidth
= Width
;
2316 if (PciRegisterAccessData
->Width
!= VALUE_NOCARE
) {
2317 AccessWidth
= PciRegisterAccessData
->Width
;
2320 AccessAddress
= Address
& ~((1 << AccessWidth
) - 1);
2323 Pointer
= (UINT8
*) &Buffer
;
2324 Data
= * (UINT64
*) Buffer
;
2328 if (AccessWidth
> Width
) {
2330 // if actual access width is larger than orignal one, additional data need to be read back firstly
2332 Status
= ReadConfigData (PciRootBridgeIo
, PciIo
, PciDeviceInfo
, AccessWidth
, AccessAddress
, &Data
);
2333 if (Status
!= EFI_SUCCESS
) {
2338 // check data read incompatibility
2340 UpdateConfigData (PciDeviceInfo
, PCI_REGISTER_READ
, AccessWidth
, AccessAddress
& 0xff, &Data
);
2342 Shift
= (UINTN
)(Address
- AccessAddress
) * 8;
2344 case EfiPciWidthUint8
:
2345 Data
= (* (UINT8
*) Buffer
) << Shift
| (Data
& ~(0xff << Shift
));
2348 case EfiPciWidthUint16
:
2349 Data
= (* (UINT16
*) Buffer
) << Shift
| (Data
& ~(0xffff << Shift
));
2354 // check data write incompatibility
2356 UpdateConfigData (PciDeviceInfo
, PCI_REGISTER_WRITE
, AccessWidth
, MultU64x32 (AccessAddress
, 0xff), &Data
);
2359 if (PciRootBridgeIo
!= NULL
) {
2360 Status
= PciRootBridgeIo
->Pci
.Write (
2362 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) AccessWidth
,
2368 Status
= PciIo
->Pci
.Write (
2370 (EFI_PCI_IO_PROTOCOL_WIDTH
) AccessWidth
,
2371 (UINT32
) AccessAddress
,
2377 if (Status
!= EFI_SUCCESS
) {
2381 Data
= RShiftU64 (Data
, ((1 << AccessWidth
) * 8));
2383 Stride
= (UINTN
)1 << AccessWidth
;
2384 AccessAddress
+= Stride
;
2385 if (AccessAddress
>= (Address
+ LShiftU64 (1ULL, (UINTN
)Width
))) {
2387 // if all datas have been written, exist
2394 if ((AccessAddress
& 0xff) < PciRegisterAccessData
->EndOffset
) {
2396 // if current offset doesn't reach the end
2401 FreePool (PciRegisterAccessData
);
2404 // continue checking access incompatibility
2406 Status
= PciRegisterAccessCheck (PciDeviceInfo
, PCI_REGISTER_WRITE
, AccessAddress
& 0xff, AccessWidth
, &PciRegisterAccessData
);
2407 if (Status
== EFI_SUCCESS
) {
2408 if (PciRegisterAccessData
->Width
!= VALUE_NOCARE
) {
2409 AccessWidth
= PciRegisterAccessData
->Width
;
2414 FreePool (PciRegisterAccessData
);
2421 // AccessWidth incompatible check not supportted
2422 // or, there doesn't exist incompatibility on this operation
2424 if (PciRootBridgeIo
!= NULL
) {
2425 Status
= PciRootBridgeIo
->Pci
.Write (
2427 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) Width
,
2433 Status
= PciIo
->Pci
.Write (
2435 (EFI_PCI_IO_PROTOCOL_WIDTH
) Width
,
2446 Abstract PCI device device information.
2448 @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
2449 @param PciIo A pointer to EFI_PCI_PROTOCOL.
2450 @param Pci A pointer to PCI_TYPE00.
2451 @Param Address The address within the PCI configuration space for the PCI controller.
2452 @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.
2454 @retval EFI_SUCCESS Pci device device information has been abstracted.
2459 GetPciDeviceDeviceInfo (
2460 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
, OPTIONAL
2461 IN EFI_PCI_IO_PROTOCOL
*PciIo
, OPTIONAL
2462 IN PCI_TYPE00
*Pci
, OPTIONAL
2463 IN UINT64 Address
, OPTIONAL
2464 OUT EFI_PCI_DEVICE_INFO
*PciDeviceInfo
2469 UINT32 PciConfigData
;
2470 PCI_IO_DEVICE
*PciIoDevice
;
2472 ASSERT ((PciRootBridgeIo
== NULL
) ^ (PciIo
== NULL
));
2474 if (PciIo
!= NULL
) {
2475 PciIoDevice
= PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo
);
2478 // get pointer to PCI_TYPE00 from PciIoDevice
2480 Pci
= &PciIoDevice
->Pci
;
2485 // while PCI_TYPE00 hasn't been gotten, read PCI device device information directly
2487 PciAddress
= Address
& 0xffffffffffffff00ULL
;
2488 Status
= PciRootBridgeIo
->Pci
.Read (
2496 if (EFI_ERROR (Status
)) {
2500 if ((PciConfigData
& 0xffff) == 0xffff) {
2501 return EFI_NOT_FOUND
;
2504 PciDeviceInfo
->VendorID
= PciConfigData
& 0xffff;
2505 PciDeviceInfo
->DeviceID
= PciConfigData
>> 16;
2507 Status
= PciRootBridgeIo
->Pci
.Read (
2514 if (EFI_ERROR (Status
)) {
2518 PciDeviceInfo
->RevisionID
= PciConfigData
& 0xf;
2520 Status
= PciRootBridgeIo
->Pci
.Read (
2528 if (EFI_ERROR (Status
)) {
2532 PciDeviceInfo
->SubsystemVendorID
= PciConfigData
& 0xffff;
2533 PciDeviceInfo
->SubsystemID
= PciConfigData
>> 16;
2536 PciDeviceInfo
->VendorID
= Pci
->Hdr
.VendorId
;
2537 PciDeviceInfo
->DeviceID
= Pci
->Hdr
.DeviceId
;
2538 PciDeviceInfo
->RevisionID
= Pci
->Hdr
.RevisionID
;
2539 PciDeviceInfo
->SubsystemVendorID
= Pci
->Device
.SubsystemVendorID
;
2540 PciDeviceInfo
->SubsystemID
= Pci
->Device
.SubsystemID
;
2547 Read PCI configuration space with incompatibility check.
2549 @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
2550 @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL.
2551 @param Pci A pointer to PCI_TYPE00.
2552 @param Width Signifies the width of the memory operations.
2553 @Param Address The address within the PCI configuration space for the PCI controller.
2554 @param Buffer For read operations, the destination buffer to store the results. For
2555 write operations, the source buffer to write data from.
2557 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
2558 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
2559 @retval EFI_INVALID_PARAMETER Buffer is NULL.
2560 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
2565 PciIncompatibilityCheckRead (
2566 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
, OPTIONAL
2567 IN EFI_PCI_IO_PROTOCOL
*PciIo
, OPTIONAL
2568 IN PCI_TYPE00
*Pci
, OPTIONAL
2576 EFI_PCI_DEVICE_INFO PciDeviceInfo
;
2579 ASSERT ((PciRootBridgeIo
== NULL
) ^ (PciIo
== NULL
));
2582 // get PCI device device information
2584 Status
= GetPciDeviceDeviceInfo (PciRootBridgeIo
, PciIo
, Pci
, Address
, &PciDeviceInfo
);
2585 if (Status
!= EFI_SUCCESS
) {
2589 Stride
= 1 << Width
;
2591 for (; Count
> 0; Count
--, Address
+= Stride
, Buffer
= (UINT8
*)Buffer
+ Stride
) {
2594 // read configuration register
2596 Status
= ReadConfigData (PciRootBridgeIo
, PciIo
, &PciDeviceInfo
, (UINT64
) Width
, Address
, Buffer
);
2598 if (Status
!= EFI_SUCCESS
) {
2603 // update the data read from configuration register
2605 if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask
) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT
) {
2606 UpdateConfigData (&PciDeviceInfo
, PCI_REGISTER_READ
, Width
, Address
& 0xff, Buffer
);
2614 Write PCI configuration space with incompatibility check.
2616 @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
2617 @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL.
2618 @param Pci A pointer to PCI_TYPE00.
2619 @param Width Signifies the width of the memory operations.
2620 @Param Address The address within the PCI configuration space for the PCI controller.
2621 @param Buffer For read operations, the destination buffer to store the results. For
2622 write operations, the source buffer to write data from.
2624 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
2625 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
2626 @retval EFI_INVALID_PARAMETER Buffer is NULL.
2627 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
2632 PciIncompatibilityCheckWrite (
2633 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
, OPTIONAL
2634 IN EFI_PCI_IO_PROTOCOL
*PciIo
, OPTIONAL
2635 IN PCI_TYPE00
*Pci
, OPTIONAL
2643 EFI_PCI_DEVICE_INFO PciDeviceInfo
;
2647 ASSERT ((PciRootBridgeIo
== NULL
) ^ (PciIo
== NULL
));
2650 // get PCI device device information
2652 Status
= GetPciDeviceDeviceInfo (PciRootBridgeIo
, PciIo
, Pci
, Address
, &PciDeviceInfo
);
2653 if (Status
!= EFI_SUCCESS
) {
2657 Stride
= 1 << Width
;
2659 for (; Count
> 0; Count
--, Address
+= Stride
, Buffer
= (UINT8
*) Buffer
+ Stride
) {
2664 case EfiPciWidthUint8
:
2665 Data
= * (UINT8
*) Buffer
;
2667 case EfiPciWidthUint16
:
2668 Data
= * (UINT16
*) Buffer
;
2671 case EfiPciWidthUint32
:
2672 Data
= * (UINT32
*) Buffer
;
2676 return EFI_UNSUPPORTED
;
2680 // update the data writen into configuration register
2682 if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask
) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT
) {
2683 UpdateConfigData (&PciDeviceInfo
, PCI_REGISTER_WRITE
, Width
, Address
& 0xff, &Data
);
2687 // write configuration register
2689 Status
= WriteConfigData (PciRootBridgeIo
, PciIo
, &PciDeviceInfo
, Width
, Address
, &Data
);
2691 if (Status
!= EFI_SUCCESS
) {
2700 Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
2702 @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
2703 @param Pci A pointer to PCI_TYPE00.
2704 @param Width Signifies the width of the memory operations.
2705 @Param Address The address within the PCI configuration space for the PCI controller.
2706 @param Buffer For read operations, the destination buffer to store the results. For
2707 write operations, the source buffer to write data from.
2709 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
2710 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
2711 @retval EFI_INVALID_PARAMETER Buffer is NULL.
2712 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
2716 PciRootBridgeIoRead (
2717 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
,
2718 IN PCI_TYPE00
*Pci
, OPTIONAL
2719 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
2725 if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask
) & PCI_INCOMPATIBLE_READ_SUPPORT
) {
2727 // if PCI incompatibility check enabled
2729 return PciIncompatibilityCheckRead (
2739 return PciRootBridgeIo
->Pci
.Read (
2750 Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
2752 @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
2753 @param Pci A pointer to PCI_TYPE00.
2754 @param Width Signifies the width of the memory operations.
2755 @Param Address The address within the PCI configuration space for the PCI controller.
2756 @param Buffer For read operations, the destination buffer to store the results. For
2757 write operations, the source buffer to write data from.
2759 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
2760 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
2761 @retval EFI_INVALID_PARAMETER Buffer is NULL.
2762 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
2766 PciRootBridgeIoWrite (
2767 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
,
2769 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
2775 if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask
) & PCI_INCOMPATIBLE_WRITE_SUPPORT
) {
2777 // if PCI incompatibility check enabled
2779 return PciIncompatibilityCheckWrite (
2790 return PciRootBridgeIo
->Pci
.Write (
2801 Read PCI configuration space through EFI_PCI_IO_PROTOCOL.
2803 @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.
2804 @param Width Signifies the width of the memory operations.
2805 @Param Address The address within the PCI configuration space for the PCI controller.
2806 @param Buffer For read operations, the destination buffer to store the results. For
2807 write operations, the source buffer to write data from.
2809 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
2810 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
2811 @retval EFI_INVALID_PARAMETER Buffer is NULL.
2812 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
2817 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
2818 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
2824 if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask
) & PCI_INCOMPATIBLE_READ_SUPPORT
) {
2826 // if PCI incompatibility check enabled
2828 return PciIncompatibilityCheckRead (
2838 return PciIo
->Pci
.Read (
2849 Write PCI configuration space through EFI_PCI_IO_PROTOCOL.
2851 @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.
2852 @param Width Signifies the width of the memory operations.
2853 @Param Address The address within the PCI configuration space for the PCI controller.
2854 @param Buffer For read operations, the destination buffer to store the results. For
2855 write operations, the source buffer to write data from.
2857 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
2858 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
2859 @retval EFI_INVALID_PARAMETER Buffer is NULL.
2860 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
2865 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
2866 IN EFI_PCI_IO_PROTOCOL_WIDTH Width
,
2872 if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask
) & PCI_INCOMPATIBLE_WRITE_SUPPORT
) {
2875 // if PCI incompatibility check enabled
2877 return PciIncompatibilityCheckWrite (
2888 return PciIo
->Pci
.Write (