1 ;------------------------------------------------------------------------------
3 ; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
4 ; SPDX-License-Identifier: BSD-2-Clause-Patent
8 ;------------------------------------------------------------------------------
13 ; Float control word initial value:
14 ; all exceptions masked, double-precision, round-to-nearest
16 ASM_PFX(mFpuControlWord):
19 ; Multimedia-extensions control word:
20 ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
22 ASM_PFX(mMmxControlWord):
28 ; Initializes floating point units for requirement of UEFI specification.
30 ; This function initializes floating-point control word to 0x027F (all exceptions
31 ; masked,double-precision, round-to-nearest) and multimedia-extensions control word
32 ; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
33 ; for masked underflow).
36 global ASM_PFX(InitializeFloatingPointUnits)
37 ASM_PFX(InitializeFloatingPointUnits):
43 ; Initialize floating point units
46 fldcw [ASM_PFX(mFpuControlWord)]
49 ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
50 ; whether the processor supports SSE instruction.
58 ; Set OSFXSR bit 9 in CR4
65 ; The processor should support SSE instruction and we can use
68 ldmxcsr [ASM_PFX(mMmxControlWord)]