IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc

   1 ;------------------------------------------------------------------------------
   2 ;
   3 ; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>
   4 ; SPDX-License-Identifier: BSD-2-Clause-Patent
   5 ;
   6 ; Abstract:
   7 ;
   8 ;   Provide macro for register save/restore using SSE registers
   9 ;
  10 ;------------------------------------------------------------------------------
  11
  12 ;
  13 ; Define SSE instruction set
  14 ;
  15 %ifdef USE_SSE41_FLAG
  16 ;
  17 ; Define SSE macros using SSE 4.1 instructions
  18 ; args 1:XMM, 2:IDX, 3:REG
  19 %macro SXMMN    3
  20              pinsrd  %1, %3, (%2 & 3)
  21              %endmacro
  22
  23 ;
  24 ;args 1:XMM, 2:REG, 3:IDX
  25 ;
  26 %macro LXMMN    3
  27              pextrd  %2, %1, (%3 & 3)
  28              %endmacro
  29 %else
  30 ;
  31 ; Define SSE macros using SSE 2 instructions
  32 ; args 1:XMM, 2:IDX, 3:REG
  33 %macro SXMMN    3
  34              pinsrw  %1, %3, (%2 & 3) * 2
  35              ror     %3, 16
  36              pinsrw  %1, %3, (%2 & 3) * 2 + 1
  37              rol     %3, 16
  38              %endmacro
  39
  40 ;
  41 ;args 1:XMM, 2:REG, 3:IDX
  42 ;
  43 %macro LXMMN    3
  44              pshufd  %1, %1, ((0E4E4E4h >> (%3 * 2))  & 0FFh)
  45              movd    %2, %1
  46              pshufd  %1, %1, ((0E4E4E4h >> (%3 * 2 + (%3 & 1) * 4)) & 0FFh)
  47              %endmacro
  48 %endif
  49
  50 ;
  51 ; XMM7 to save/restore EBP - slot 0, EBX - slot 1, ESI - slot 2, EDI - slot 3
  52 ;
  53 %macro SAVE_REGS    0
  54   SXMMN      xmm7, 0, ebp
  55   SXMMN      xmm7, 1, ebx
  56   SXMMN      xmm7, 2, esi
  57   SXMMN      xmm7, 3, edi
  58   SAVE_ESP
  59              %endmacro
  60
  61 %macro LOAD_REGS    0
  62   LXMMN      xmm7, ebp, 0
  63   LXMMN      xmm7, ebx, 1
  64   LXMMN      xmm7, esi, 2
  65   LXMMN      xmm7, edi, 3
  66   LOAD_ESP
  67              %endmacro
  68
  69 ;
  70 ; XMM6 to save/restore ESP - slot 0, EAX - slot 1, EDX - slot 2, ECX - slot 3
  71 ;
  72 %macro LOAD_ESP    0
  73   movd       esp,  xmm6
  74              %endmacro
  75
  76 %macro SAVE_ESP    0
  77   SXMMN      xmm6, 0, esp
  78              %endmacro
  79
  80 %macro LOAD_EAX    0
  81   LXMMN      xmm6, eax, 1
  82              %endmacro
  83
  84 %macro SAVE_EAX    0
  85   SXMMN      xmm6, 1, eax
  86              %endmacro
  87
  88 %macro LOAD_EDX    0
  89   LXMMN      xmm6, edx, 2
  90              %endmacro
  91
  92 %macro SAVE_EDX    0
  93   SXMMN      xmm6, 2, edx
  94              %endmacro
  95
  96 %macro LOAD_ECX    0
  97   LXMMN      xmm6, ecx, 3
  98              %endmacro
  99
 100 %macro SAVE_ECX    0
 101   SXMMN      xmm6, 3, ecx
 102              %endmacro
 103
 104 ;
 105 ; XMM5 slot 0 for calling stack
 106 ; arg 1:Entry
 107 %macro CALL_XMM       1
 108              mov     esi, %%ReturnAddress
 109              SXMMN   xmm5, 0, esi
 110              mov     esi,  %1
 111              jmp     esi
 112 %%ReturnAddress:
 113              %endmacro
 114
 115 %macro RET_XMM       0
 116              LXMMN   xmm5, esi, 0
 117              jmp     esi
 118              %endmacro
 119
 120 ;
 121 ; XMM5 slot 1 for uCode status
 122 ;
 123 %macro LOAD_UCODE_STATUS    0
 124   LXMMN      xmm5, eax, 1
 125              %endmacro
 126
 127 %macro SAVE_UCODE_STATUS    0
 128   SXMMN      xmm5, 1, eax
 129              %endmacro
 130
 131 %macro ENABLE_SSE   0
 132             ;
 133             ; Initialize floating point units
 134             ;
 135             jmp     NextAddress
 136 align 4
 137             ;
 138             ; Float control word initial value:
 139             ; all exceptions masked, double-precision, round-to-nearest
 140             ;
 141 FpuControlWord       DW      027Fh
 142             ;
 143             ; Multimedia-extensions control word:
 144             ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
 145             ;
 146 MmxControlWord       DD      01F80h
 147 SseError:
 148             ;
 149             ; Processor has to support SSE
 150             ;
 151             jmp     SseError
 152 NextAddress:
 153             finit
 154             fldcw   [FpuControlWord]
 155
 156             ;
 157             ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
 158             ; whether the processor supports SSE instruction.
 159             ;
 160             mov     eax, 1
 161             cpuid
 162             bt      edx, 25
 163             jnc     SseError
 164
 165 %ifdef USE_SSE41_FLAG
 166             ;
 167             ; SSE 4.1 support
 168             ;
 169             bt      ecx, 19
 170             jnc     SseError
 171 %endif
 172
 173             ;
 174             ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
 175             ;
 176             mov     eax, cr4
 177             or      eax, 00000600h
 178             mov     cr4, eax
 179
 180             ;
 181             ; The processor should support SSE instruction and we can use
 182             ; ldmxcsr instruction
 183             ;
 184             ldmxcsr [MmxControlWord]
 185             %endmacro