1 ;------------------------------------------------------------------------------
3 ; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>
4 ; SPDX-License-Identifier: BSD-2-Clause-Patent
8 ; Provide macro for register save/restore using SSE registers
10 ;------------------------------------------------------------------------------
13 ; Define SSE instruction set
17 ; Define SSE macros using SSE 4.1 instructions
18 ; args 1:XMM, 2:IDX, 3:REG
20 pinsrd %1, %3, (%2 & 3)
24 ;args 1:XMM, 2:REG, 3:IDX
27 pextrd %2, %1, (%3 & 3)
31 ; Define SSE macros using SSE 2 instructions
32 ; args 1:XMM, 2:IDX, 3:REG
34 pinsrw %1, %3, (%2 & 3) * 2
36 pinsrw %1, %3, (%2 & 3) * 2 + 1
41 ;args 1:XMM, 2:REG, 3:IDX
44 pshufd %1, %1, ((0E4E4E4h >> (%3 * 2)) & 0FFh)
46 pshufd %1, %1, ((0E4E4E4h >> (%3 * 2 + (%3 & 1) * 4)) & 0FFh)
51 ; XMM7 to save/restore EBP - slot 0, EBX - slot 1, ESI - slot 2, EDI - slot 3
70 ; XMM6 to save/restore ESP - slot 0, EAX - slot 1, EDX - slot 2, ECX - slot 3
105 ; XMM5 slot 0 for calling stack
108 mov esi, %%ReturnAddress
121 ; XMM5 slot 1 for uCode status
123 %macro LOAD_UCODE_STATUS 0
127 %macro SAVE_UCODE_STATUS 0
133 ; Initialize floating point units
138 ; Float control word initial value:
139 ; all exceptions masked, double-precision, round-to-nearest
141 FpuControlWord DW 027Fh
143 ; Multimedia-extensions control word:
144 ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
146 MmxControlWord DD 01F80h
149 ; Processor has to support SSE
154 fldcw [FpuControlWord]
157 ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
158 ; whether the processor supports SSE instruction.
165 %ifdef USE_SSE41_FLAG
174 ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
181 ; The processor should support SSE instruction and we can use
182 ; ldmxcsr instruction
184 ldmxcsr [MmxControlWord]