3 Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>
4 SPDX-License-Identifier: BSD-2-Clause-Patent
8 #ifndef _FSP_GLOBAL_DATA_H_
9 #define _FSP_GLOBAL_DATA_H_
13 #define FSP_IN_API_MODE 0
14 #define FSP_IN_DISPATCH_MODE 1
15 #define FSP_GLOBAL_DATA_VERSION 0x3
23 FspMemoryInitApiIndex
,
25 FspSiliconInitApiIndex
,
26 FspMultiPhaseSiInitApiIndex
,
28 FspMultiPhaseMemInitApiIndex
,
34 UINTN MicrocodeRegionBase
;
35 UINTN MicrocodeRegionSize
;
41 #define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')
42 #define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F')
43 #define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF
55 /// IA32: Offset 0x10; X64: Offset 0x18
60 /// 0: FSP in API mode; 1: FSP in DISPATCH mode
63 UINT8 OnSeparateStack
;
65 UINT32 NumberOfPhases
;
66 UINT32 PhasesExecuted
;
69 /// IA32: Offset 0x40; X64: Offset 0x48
70 /// Start of UINTN and pointer section
71 /// All UINTN and pointer members are put in this section
72 /// for maintaining natural alignment for both IA32 and X64 builds.
74 FSP_PLAT_DATA PlatformData
;
75 VOID
*TempRamInitUpdPtr
;
76 VOID
*MemoryInitUpdPtr
;
77 VOID
*SiliconInitUpdPtr
;
79 /// IA32: Offset 0x64; X64: Offset 0x90
80 /// To store function parameters pointer
81 /// so it can be retrieved after stack switched.
83 VOID
*FunctionParameterPtr
;
84 FSP_INFO_HEADER
*FspInfoHeader
;
87 VOID
*VariableRequestParameterPtr
;
89 /// End of UINTN and pointer section
90 /// At this point, next field offset must be either *0h or *8h to
91 /// meet natural alignment requirement.