2 # Provides drivers and definitions to support fsp in EDKII bios.
4 # Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
5 # SPDX-License-Identifier: BSD-2-Clause-Patent
10 DEC_SPECIFICATION = 0x00010005
11 PACKAGE_NAME = IntelFsp2WrapperPkg
12 PACKAGE_GUID = FAFE06D4-7245-42D7-9FD2-E5D5E36AB0A0
19 ## @libraryclass Provide FSP API related function.
20 FspWrapperApiLib|Include/Library/FspWrapperApiLib.h
21 FspWrapperApiTestLib|Include/Library/FspWrapperApiTestLib.h
23 ## @libraryclass Provide FSP hob process related function.
24 FspWrapperHobProcessLib|Include/Library/FspWrapperHobProcessLib.h
26 ## @libraryclass Provide FSP platform related function.
27 FspWrapperPlatformLib|Include/Library/FspWrapperPlatformLib.h
31 # GUID defined in package
33 gIntelFsp2WrapperTokenSpaceGuid = { 0xa34cf082, 0xf50, 0x4f0d, { 0x89, 0x8a, 0x3d, 0x39, 0x30, 0x2b, 0xc5, 0x1e } }
34 gFspApiPerformanceGuid = { 0xc9122295, 0x56ed, 0x4d4e, { 0x06, 0xa6, 0x50, 0x8d, 0x89, 0x4d, 0x3e, 0x40 } }
35 gFspHobGuid = { 0x6d86fb36, 0xba90, 0x472c, { 0xb5, 0x83, 0x3f, 0xbe, 0xd3, 0xfb, 0x20, 0x9a } }
38 gFspSiliconInitDonePpiGuid = { 0x4eb6e09c, 0xd256, 0x4e1e, { 0xb5, 0x0a, 0x87, 0x4b, 0xd2, 0x84, 0xb3, 0xde } }
39 gTopOfTemporaryRamPpiGuid = { 0x2f3962b2, 0x57c5, 0x44ec, { 0x9e, 0xfc, 0xa6, 0x9f, 0xd3, 0x02, 0x03, 0x2b } }
42 gAddPerfRecordProtocolGuid = { 0xc4a58d6d, 0x3677, 0x49cb, { 0xa0, 0x0a, 0x94, 0x70, 0x76, 0x5f, 0xb5, 0x5e } }
44 ################################################################################
46 # PCD Declarations section - list of all PCDs Declared by this Package
47 # Only this package should be providing the
48 # declaration, other packages should not.
50 ################################################################################
51 [PcdsFixedAtBuild, PcdsPatchableInModule]
52 ## Provides the memory mapped base address of the BIOS CodeCache Flash Device.
53 gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFFE00000|UINT32|0x10000001
54 ## Provides the size of the BIOS Flash Device.
55 gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002
57 ## Indicates the base address of the first Microcode Patch in the Microcode Region
58 gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005
59 gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x10000006
60 ## Indicates the offset of the Cpu Microcode.
61 gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset|0x90|UINT32|0x10000007
63 ## Indicate the PEI memory size platform want to report
64 gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x1800000|UINT32|0x40000004
65 ## Indicate the PEI memory size platform want to report
66 gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x3000000|UINT32|0x40000005
68 ## This is the base address of FSP-T
69 gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0x00000000|UINT32|0x00000300
71 ## This PCD indicates if FSP APIs are skipped from FSP wrapper.<BR><BR>
72 # If a bit is set, that means this FSP API is skipped.<BR>
73 # If a bit is clear, that means this FSP API is NOT skipped.<BR>
74 # NOTE: Only NotifyPhase Post PCI enumeration (BIT16) is implemented.<BR>
75 # BIT[15:0] is for function:<BR>
76 # BIT0 - Skip TempRamInit<BR>
77 # BIT1 - Skip MemoryInit<BR>
78 # BIT2 - Skip TempRamExit<BR>
79 # BIT3 - Skip SiliconInit<BR>
80 # BIT4 - Skip NotifyPhase<BR>
81 # BIT[32:16] is for sub-function:<BR>
82 # BIT16 - Skip NotifyPhase (AfterPciEnumeration)<BR>
83 # BIT17 - Skip NotifyPhase (ReadyToBoot)<BR>
84 # BIT18 - Skip NotifyPhase (EndOfFirmware)<BR>
85 # Any undefined BITs are reserved for future use.<BR>
86 # @Prompt Skip FSP API from FSP wrapper.
87 gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi|0x00000000|UINT32|0x40000009
89 ## This PCD decides how Wrapper code utilizes FSP
90 # 0: DISPATCH mode (FSP Wrapper will load PeiCore from FSP without calling FSP API)
91 # 1: API mode (FSP Wrapper will call FSP API)
93 gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0x00000001|UINT8|0x4000000A
95 [PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx]
97 ## These are the base address of FSP-M/S
99 gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32|0x00001000
100 gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT32|0x00001001
102 # To provide flexibility for platform to pre-allocate FSP UPD buffer
104 # The PCDs define the pre-allocated FSPM and FSPS UPD Data Buffer Address.
105 # 0x00000000 - Platform will not pre-allocate UPD buffer before FspWrapper module
106 # non-zero - Platform will pre-allocate UPD buffer and patch this value to
107 # buffer address before FspWrapper module executing.
109 gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000|UINT32|0x50000000
110 gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x00000000|UINT32|0x50000001