IntelFspPkg/FspSecCore/Ia32/InitializeFpu.asm

   1 ;------------------------------------------------------------------------------
   2 ;
   3 ; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
   4 ; SPDX-License-Identifier: BSD-2-Clause-Patent
   5 ;
   6 ; Abstract:
   7 ;
   8 ;------------------------------------------------------------------------------
   9
  10     .686
  11     .model  flat,C
  12     .const
  13 ;
  14 ; Float control word initial value:
  15 ; all exceptions masked, double-precision, round-to-nearest
  16 ;
  17 mFpuControlWord       DW      027Fh
  18 ;
  19 ; Multimedia-extensions control word:
  20 ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
  21 ;
  22 mMmxControlWord       DD      01F80h
  23
  24     .xmm
  25     .code
  26
  27 ;
  28 ; Initializes floating point units for requirement of UEFI specification.
  29 ;
  30 ; This function initializes floating-point control word to 0x027F (all exceptions
  31 ; masked,double-precision, round-to-nearest) and multimedia-extensions control word
  32 ; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
  33 ; for masked underflow).
  34 ;
  35 InitializeFloatingPointUnits PROC PUBLIC
  36
  37     push    ebx
  38
  39     ;
  40     ; Initialize floating point units
  41     ;
  42     finit
  43     fldcw   mFpuControlWord
  44
  45     ;
  46     ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
  47     ; whether the processor supports SSE instruction.
  48     ;
  49     mov     eax, 1
  50     cpuid
  51     bt      edx, 25
  52     jnc     Done
  53
  54     ;
  55     ; Set OSFXSR bit 9 in CR4
  56     ;
  57     mov     eax, cr4
  58     or      eax, BIT9
  59     mov     cr4, eax
  60
  61     ;
  62     ; The processor should support SSE instruction and we can use
  63     ; ldmxcsr instruction
  64     ;
  65     ldmxcsr mMmxControlWord
  66 Done:
  67     pop     ebx
  68
  69     ret
  70
  71 InitializeFloatingPointUnits ENDP
  72
  73 END