2 The definition for VTD register.
3 It is defined in "Intel VT for Direct IO Architecture Specification".
5 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 // Translation Structure Formats
24 #define VTD_ROOT_ENTRY_NUMBER 256
25 #define VTD_CONTEXT_ENTRY_NUMBER 256
31 UINT32 ContextTablePointerLo
:20;
32 UINT32 ContextTablePointerHi
:32;
44 UINT32 LowerPresent
:1;
46 UINT32 LowerContextTablePointerLo
:20;
47 UINT32 LowerContextTablePointerHi
:32;
49 UINT32 UpperPresent
:1;
50 UINT32 Reserved_65
:11;
51 UINT32 UpperContextTablePointerLo
:20;
52 UINT32 UpperContextTablePointerHi
:32;
63 UINT32 FaultProcessingDisable
:1;
64 UINT32 TranslationType
:2;
66 UINT32 SecondLevelPageTranslationPointerLo
:20;
67 UINT32 SecondLevelPageTranslationPointerHi
:32;
69 UINT32 AddressWidth
:3;
72 UINT32 DomainIdentifier
:16;
74 UINT32 Reserved_96
:32;
85 UINT32 FaultProcessingDisable
:1;
86 UINT32 TranslationType
:3;
87 UINT32 ExtendedMemoryType
:3;
88 UINT32 DeferredInvalidateEnable
:1;
89 UINT32 PageRequestEnable
:1;
90 UINT32 NestedTranslationEnable
:1;
92 UINT32 SecondLevelPageTranslationPointerLo
:20;
93 UINT32 SecondLevelPageTranslationPointerHi
:32;
95 UINT32 AddressWidth
:3;
96 UINT32 PageGlobalEnable
:1;
97 UINT32 NoExecuteEnable
:1;
98 UINT32 WriteProtectEnable
:1;
99 UINT32 CacheDisable
:1;
100 UINT32 ExtendedMemoryTypeEnable
:1;
101 UINT32 DomainIdentifier
:16;
102 UINT32 SupervisorModeExecuteProtection
:1;
103 UINT32 ExtendedAccessedFlagEnable
:1;
104 UINT32 ExecuteRequestsEnable
:1;
105 UINT32 SecondLevelExecuteEnable
:1;
106 UINT32 Reserved_92
:4;
107 UINT32 PageAttributeTable0
:3;
108 UINT32 Reserved_Pat0
:1;
109 UINT32 PageAttributeTable1
:3;
110 UINT32 Reserved_Pat1
:1;
111 UINT32 PageAttributeTable2
:3;
112 UINT32 Reserved_Pat2
:1;
113 UINT32 PageAttributeTable3
:3;
114 UINT32 Reserved_Pat3
:1;
115 UINT32 PageAttributeTable4
:3;
116 UINT32 Reserved_Pat4
:1;
117 UINT32 PageAttributeTable5
:3;
118 UINT32 Reserved_Pat5
:1;
119 UINT32 PageAttributeTable6
:3;
120 UINT32 Reserved_Pat6
:1;
121 UINT32 PageAttributeTable7
:3;
122 UINT32 Reserved_Pat7
:1;
124 UINT32 PASIDTableSize
:4;
125 UINT32 Reserved_132
:8;
126 UINT32 PASIDTablePointerLo
:20;
127 UINT32 PASIDTablePointerHi
:32;
129 UINT32 Reserved_192
:12;
130 UINT32 PASIDStateTablePointerLo
:20;
131 UINT32 PASIDStateTablePointerHi
:32;
139 } VTD_EXT_CONTEXT_ENTRY
;
145 UINT32 PageLevelCacheDisable
:1;
146 UINT32 PageLevelWriteThrough
:1;
148 UINT32 SupervisorRequestsEnable
:1;
149 UINT32 FirstLevelPageTranslationPointerLo
:20;
150 UINT32 FirstLevelPageTranslationPointerHi
:32;
157 UINT32 Reserved_0
:32;
158 UINT32 ActiveReferenceCount
:16;
159 UINT32 Reserved_48
:15;
160 UINT32 DeferredInvalidate
:1;
163 } VTD_PASID_STATE_ENTRY
;
169 UINT32 UserSupervisor
:1;
170 UINT32 PageLevelWriteThrough
:1;
171 UINT32 PageLevelCacheDisable
:1;
174 UINT32 PageSize
:1; // It is PageAttribute:1 for 4K page entry
177 UINT32 ExtendedAccessed
:1;
179 // NOTE: There is PageAttribute:1 as bit12 for 1G page entry and 2M page entry
182 UINT32 Ignored_52
:11;
183 UINT32 ExecuteDisable
:1;
186 } VTD_FIRST_LEVEL_PAGING_ENTRY
;
193 UINT32 ExtendedMemoryType
:3;
200 UINT32 Ignored_52
:10;
201 UINT32 TransientMapping
:1;
205 } VTD_SECOND_LEVEL_PAGING_ENTRY
;
208 // Register Descriptions
210 #define R_VER_REG 0x00
211 #define R_CAP_REG 0x08
212 #define B_CAP_REG_RWBF BIT4
213 #define R_ECAP_REG 0x10
214 #define R_GCMD_REG 0x18
215 #define B_GMCD_REG_WBF BIT27
216 #define B_GMCD_REG_SRTP BIT30
217 #define B_GMCD_REG_TE BIT31
218 #define R_GSTS_REG 0x1C
219 #define B_GSTS_REG_WBF BIT27
220 #define B_GSTS_REG_RTPS BIT30
221 #define B_GSTS_REG_TE BIT31
222 #define R_RTADDR_REG 0x20
223 #define R_CCMD_REG 0x28
224 #define B_CCMD_REG_CIRG_MASK (BIT62|BIT61)
225 #define V_CCMD_REG_CIRG_GLOBAL BIT61
226 #define V_CCMD_REG_CIRG_DOMAIN BIT62
227 #define V_CCMD_REG_CIRG_DEVICE (BIT62|BIT61)
228 #define B_CCMD_REG_ICC BIT63
229 #define R_FSTS_REG 0x34
230 #define R_FECTL_REG 0x38
231 #define R_FEDATA_REG 0x3C
232 #define R_FEADDR_REG 0x40
233 #define R_FEUADDR_REG 0x44
234 #define R_AFLOG_REG 0x58
236 #define R_IVA_REG 0x00 // + IRO
237 #define B_IVA_REG_AM_MASK (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5)
238 #define B_IVA_REG_AM_4K 0 // 1 page
239 #define B_IVA_REG_AM_2M 9 // 2M page
240 #define B_IVA_REG_IH BIT6
241 #define R_IOTLB_REG 0x08 // + IRO
242 #define B_IOTLB_REG_IIRG_MASK (BIT61|BIT60)
243 #define V_IOTLB_REG_IIRG_GLOBAL BIT60
244 #define V_IOTLB_REG_IIRG_DOMAIN BIT61
245 #define V_IOTLB_REG_IIRG_PAGE (BIT61|BIT60)
246 #define B_IOTLB_REG_IVT BIT63
248 #define R_FRCD_REG 0x00 // + FRO
250 #define R_PMEN_ENABLE_REG 0x64
251 #define R_PMEN_LOW_BASE_REG 0x68
252 #define R_PMEN_LOW_LIMITE_REG 0x6C
253 #define R_PMEN_HIGH_BASE_REG 0x70
254 #define R_PMEN_HIGH_LIMITE_REG 0x78
258 UINT8 ND
:3; // Number of domains supported
259 UINT8 AFL
:1; // Advanced Fault Logging
260 UINT8 RWBF
:1; // Required Write-Buffer Flushing
261 UINT8 PLMR
:1; // Protected Low-Memory Region
262 UINT8 PHMR
:1; // Protected High-Memory Region
263 UINT8 CM
:1; // Caching Mode
265 UINT8 SAGAW
:5; // Supported Adjusted Guest Address Widths
268 UINT8 MGAW
:6; // Maximum Guest Address Width
269 UINT8 ZLR
:1; // Zero Length Read
272 UINT16 FRO
:10; // Fault-recording Register offset
273 UINT16 SLLPS
:4; // Second Level Large Page Support
275 UINT16 PSI
:1; // Page Selective Invalidation
277 UINT8 NFR
:8; // Number of Fault-recording Registers
279 UINT8 MAMV
:6; // Maximum Address Mask Value
280 UINT8 DWD
:1; // Write Draining
281 UINT8 DRD
:1; // Read Draining
283 UINT8 FL1GP
:1; // First Level 1-GByte Page Support
285 UINT8 PI
:1; // Posted Interrupts Support
293 UINT8 C
:1; // Page-walk Coherency
294 UINT8 QI
:1; // Queued Invalidation support
295 UINT8 DT
:1; // Device-TLB support
296 UINT8 IR
:1; // Interrupt Remapping support
297 UINT8 EIM
:1; // Extended Interrupt Mode
299 UINT8 PT
:1; // Pass Through
300 UINT8 SC
:1; // Snoop Control
302 UINT16 IRO
:10; // IOTLB Register Offset
304 UINT16 MHMV
:4; // Maximum Handle Mask Value
306 UINT8 ECS
:1; // Extended Context Support
307 UINT8 MTS
:1; // Memory Type Support
308 UINT8 NEST
:1; // Nested Translation Support
309 UINT8 DIS
:1; // Deferred Invalidate Support
310 UINT8 PASID
:1; // Process Address Space ID Support
311 UINT8 PRS
:1; // Page Request Support
312 UINT8 ERS
:1; // Execute Request Support
313 UINT8 SRS
:1; // Supervisor Request Support
316 UINT32 NWFS
:1; // No Write Flag Support
317 UINT32 EAFS
:1; // Extended Accessed Flag Support
318 UINT32 PSS
:5; // PASID Size Supported
327 UINT32 FILo
:20; // FaultInfo
328 UINT32 FIHi
:32; // FaultInfo
330 UINT32 SID
:16; // Source Identifier
332 UINT32 PRIV
:1; // Privilege Mode Requested
333 UINT32 EXE
:1; // Execute Permission Requested
334 UINT32 PP
:1; // PASID Present
336 UINT32 FR
:8; // Fault Reason
337 UINT32 PV
:20; // PASID Value
338 UINT32 AT
:2; // Address Type
339 UINT32 T
:1; // Type (0: Write, 1: Read)