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[mirror_edk2.git] / MdeModulePkg / Bus / Ata / AtaAtapiPassThru / AhciMode.c
1 /** @file
2 The file for AHCI mode of ATA host controller.
3
4 Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10 #include "AtaAtapiPassThru.h"
11
12 /**
13 Read AHCI Operation register.
14
15 @param PciIo The PCI IO protocol instance.
16 @param Offset The operation register offset.
17
18 @return The register content read.
19
20 **/
21 UINT32
22 EFIAPI
23 AhciReadReg (
24 IN EFI_PCI_IO_PROTOCOL *PciIo,
25 IN UINT32 Offset
26 )
27 {
28 UINT32 Data;
29
30 ASSERT (PciIo != NULL);
31
32 Data = 0;
33
34 PciIo->Mem.Read (
35 PciIo,
36 EfiPciIoWidthUint32,
37 EFI_AHCI_BAR_INDEX,
38 (UINT64) Offset,
39 1,
40 &Data
41 );
42
43 return Data;
44 }
45
46 /**
47 Write AHCI Operation register.
48
49 @param PciIo The PCI IO protocol instance.
50 @param Offset The operation register offset.
51 @param Data The data used to write down.
52
53 **/
54 VOID
55 EFIAPI
56 AhciWriteReg (
57 IN EFI_PCI_IO_PROTOCOL *PciIo,
58 IN UINT32 Offset,
59 IN UINT32 Data
60 )
61 {
62 ASSERT (PciIo != NULL);
63
64 PciIo->Mem.Write (
65 PciIo,
66 EfiPciIoWidthUint32,
67 EFI_AHCI_BAR_INDEX,
68 (UINT64) Offset,
69 1,
70 &Data
71 );
72
73 return ;
74 }
75
76 /**
77 Do AND operation with the value of AHCI Operation register.
78
79 @param PciIo The PCI IO protocol instance.
80 @param Offset The operation register offset.
81 @param AndData The data used to do AND operation.
82
83 **/
84 VOID
85 EFIAPI
86 AhciAndReg (
87 IN EFI_PCI_IO_PROTOCOL *PciIo,
88 IN UINT32 Offset,
89 IN UINT32 AndData
90 )
91 {
92 UINT32 Data;
93
94 ASSERT (PciIo != NULL);
95
96 Data = AhciReadReg (PciIo, Offset);
97
98 Data &= AndData;
99
100 AhciWriteReg (PciIo, Offset, Data);
101 }
102
103 /**
104 Do OR operation with the value of AHCI Operation register.
105
106 @param PciIo The PCI IO protocol instance.
107 @param Offset The operation register offset.
108 @param OrData The data used to do OR operation.
109
110 **/
111 VOID
112 EFIAPI
113 AhciOrReg (
114 IN EFI_PCI_IO_PROTOCOL *PciIo,
115 IN UINT32 Offset,
116 IN UINT32 OrData
117 )
118 {
119 UINT32 Data;
120
121 ASSERT (PciIo != NULL);
122
123 Data = AhciReadReg (PciIo, Offset);
124
125 Data |= OrData;
126
127 AhciWriteReg (PciIo, Offset, Data);
128 }
129
130 /**
131 Wait for the value of the specified MMIO register set to the test value.
132
133 @param PciIo The PCI IO protocol instance.
134 @param Offset The MMIO address to test.
135 @param MaskValue The mask value of memory.
136 @param TestValue The test value of memory.
137 @param Timeout The time out value for wait memory set, uses 100ns as a unit.
138
139 @retval EFI_TIMEOUT The MMIO setting is time out.
140 @retval EFI_SUCCESS The MMIO is correct set.
141
142 **/
143 EFI_STATUS
144 EFIAPI
145 AhciWaitMmioSet (
146 IN EFI_PCI_IO_PROTOCOL *PciIo,
147 IN UINTN Offset,
148 IN UINT32 MaskValue,
149 IN UINT32 TestValue,
150 IN UINT64 Timeout
151 )
152 {
153 UINT32 Value;
154 UINT64 Delay;
155 BOOLEAN InfiniteWait;
156
157 if (Timeout == 0) {
158 InfiniteWait = TRUE;
159 } else {
160 InfiniteWait = FALSE;
161 }
162
163 Delay = DivU64x32 (Timeout, 1000) + 1;
164
165 do {
166 //
167 // Access PCI MMIO space to see if the value is the tested one.
168 //
169 Value = AhciReadReg (PciIo, (UINT32) Offset) & MaskValue;
170
171 if (Value == TestValue) {
172 return EFI_SUCCESS;
173 }
174
175 //
176 // Stall for 100 microseconds.
177 //
178 MicroSecondDelay (100);
179
180 Delay--;
181
182 } while (InfiniteWait || (Delay > 0));
183
184 return EFI_TIMEOUT;
185 }
186
187 /**
188 Wait for the value of the specified system memory set to the test value.
189
190 @param Address The system memory address to test.
191 @param MaskValue The mask value of memory.
192 @param TestValue The test value of memory.
193 @param Timeout The time out value for wait memory set, uses 100ns as a unit.
194
195 @retval EFI_TIMEOUT The system memory setting is time out.
196 @retval EFI_SUCCESS The system memory is correct set.
197
198 **/
199 EFI_STATUS
200 EFIAPI
201 AhciWaitMemSet (
202 IN EFI_PHYSICAL_ADDRESS Address,
203 IN UINT32 MaskValue,
204 IN UINT32 TestValue,
205 IN UINT64 Timeout
206 )
207 {
208 UINT32 Value;
209 UINT64 Delay;
210 BOOLEAN InfiniteWait;
211
212 if (Timeout == 0) {
213 InfiniteWait = TRUE;
214 } else {
215 InfiniteWait = FALSE;
216 }
217
218 Delay = DivU64x32 (Timeout, 1000) + 1;
219
220 do {
221 //
222 // Access system memory to see if the value is the tested one.
223 //
224 // The system memory pointed by Address will be updated by the
225 // SATA Host Controller, "volatile" is introduced to prevent
226 // compiler from optimizing the access to the memory address
227 // to only read once.
228 //
229 Value = *(volatile UINT32 *) (UINTN) Address;
230 Value &= MaskValue;
231
232 if (Value == TestValue) {
233 return EFI_SUCCESS;
234 }
235
236 //
237 // Stall for 100 microseconds.
238 //
239 MicroSecondDelay (100);
240
241 Delay--;
242
243 } while (InfiniteWait || (Delay > 0));
244
245 return EFI_TIMEOUT;
246 }
247
248 /**
249 Check the memory status to the test value.
250
251 @param[in] Address The memory address to test.
252 @param[in] MaskValue The mask value of memory.
253 @param[in] TestValue The test value of memory.
254
255 @retval EFI_NOT_READY The memory is not set.
256 @retval EFI_SUCCESS The memory is correct set.
257 **/
258 EFI_STATUS
259 EFIAPI
260 AhciCheckMemSet (
261 IN UINTN Address,
262 IN UINT32 MaskValue,
263 IN UINT32 TestValue
264 )
265 {
266 UINT32 Value;
267
268 Value = *(volatile UINT32 *) Address;
269 Value &= MaskValue;
270
271 if (Value == TestValue) {
272 return EFI_SUCCESS;
273 }
274
275 return EFI_NOT_READY;
276 }
277
278
279 /**
280
281 Clear the port interrupt and error status. It will also clear
282 HBA interrupt status.
283
284 @param PciIo The PCI IO protocol instance.
285 @param Port The number of port.
286
287 **/
288 VOID
289 EFIAPI
290 AhciClearPortStatus (
291 IN EFI_PCI_IO_PROTOCOL *PciIo,
292 IN UINT8 Port
293 )
294 {
295 UINT32 Offset;
296
297 //
298 // Clear any error status
299 //
300 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
301 AhciWriteReg (PciIo, Offset, AhciReadReg (PciIo, Offset));
302
303 //
304 // Clear any port interrupt status
305 //
306 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
307 AhciWriteReg (PciIo, Offset, AhciReadReg (PciIo, Offset));
308
309 //
310 // Clear any HBA interrupt status
311 //
312 AhciWriteReg (PciIo, EFI_AHCI_IS_OFFSET, AhciReadReg (PciIo, EFI_AHCI_IS_OFFSET));
313 }
314
315 /**
316 This function is used to dump the Status Registers and if there is ERR bit set
317 in the Status Register, the Error Register's value is also be dumped.
318
319 @param PciIo The PCI IO protocol instance.
320 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
321 @param Port The number of port.
322 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
323
324 **/
325 VOID
326 EFIAPI
327 AhciDumpPortStatus (
328 IN EFI_PCI_IO_PROTOCOL *PciIo,
329 IN EFI_AHCI_REGISTERS *AhciRegisters,
330 IN UINT8 Port,
331 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
332 )
333 {
334 UINTN Offset;
335 UINT32 Data;
336 UINTN FisBaseAddr;
337 EFI_STATUS Status;
338
339 ASSERT (PciIo != NULL);
340
341 if (AtaStatusBlock != NULL) {
342 ZeroMem (AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
343
344 FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
345 Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
346
347 Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H);
348 if (!EFI_ERROR (Status)) {
349 //
350 // If D2H FIS is received, update StatusBlock with its content.
351 //
352 CopyMem (AtaStatusBlock, (UINT8 *)Offset, sizeof (EFI_ATA_STATUS_BLOCK));
353 } else {
354 //
355 // If D2H FIS is not received, only update Status & Error field through PxTFD
356 // as there is no other way to get the content of the Shadow Register Block.
357 //
358 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
359 Data = AhciReadReg (PciIo, (UINT32)Offset);
360
361 AtaStatusBlock->AtaStatus = (UINT8)Data;
362 if ((AtaStatusBlock->AtaStatus & BIT0) != 0) {
363 AtaStatusBlock->AtaError = (UINT8)(Data >> 8);
364 }
365 }
366 }
367 }
368
369
370 /**
371 Enable the FIS running for giving port.
372
373 @param PciIo The PCI IO protocol instance.
374 @param Port The number of port.
375 @param Timeout The timeout value of enabling FIS, uses 100ns as a unit.
376
377 @retval EFI_DEVICE_ERROR The FIS enable setting fails.
378 @retval EFI_TIMEOUT The FIS enable setting is time out.
379 @retval EFI_SUCCESS The FIS enable successfully.
380
381 **/
382 EFI_STATUS
383 EFIAPI
384 AhciEnableFisReceive (
385 IN EFI_PCI_IO_PROTOCOL *PciIo,
386 IN UINT8 Port,
387 IN UINT64 Timeout
388 )
389 {
390 UINT32 Offset;
391
392 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
393 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);
394
395 return EFI_SUCCESS;
396 }
397
398 /**
399 Disable the FIS running for giving port.
400
401 @param PciIo The PCI IO protocol instance.
402 @param Port The number of port.
403 @param Timeout The timeout value of disabling FIS, uses 100ns as a unit.
404
405 @retval EFI_DEVICE_ERROR The FIS disable setting fails.
406 @retval EFI_TIMEOUT The FIS disable setting is time out.
407 @retval EFI_UNSUPPORTED The port is in running state.
408 @retval EFI_SUCCESS The FIS disable successfully.
409
410 **/
411 EFI_STATUS
412 EFIAPI
413 AhciDisableFisReceive (
414 IN EFI_PCI_IO_PROTOCOL *PciIo,
415 IN UINT8 Port,
416 IN UINT64 Timeout
417 )
418 {
419 UINT32 Offset;
420 UINT32 Data;
421
422 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
423 Data = AhciReadReg (PciIo, Offset);
424
425 //
426 // Before disabling Fis receive, the DMA engine of the port should NOT be in running status.
427 //
428 if ((Data & (EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_CR)) != 0) {
429 return EFI_UNSUPPORTED;
430 }
431
432 //
433 // Check if the Fis receive DMA engine for the port is running.
434 //
435 if ((Data & EFI_AHCI_PORT_CMD_FR) != EFI_AHCI_PORT_CMD_FR) {
436 return EFI_SUCCESS;
437 }
438
439 AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_FRE));
440
441 return AhciWaitMmioSet (
442 PciIo,
443 Offset,
444 EFI_AHCI_PORT_CMD_FR,
445 0,
446 Timeout
447 );
448 }
449
450
451
452 /**
453 Build the command list, command table and prepare the fis receiver.
454
455 @param PciIo The PCI IO protocol instance.
456 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
457 @param Port The number of port.
458 @param PortMultiplier The timeout value of stop.
459 @param CommandFis The control fis will be used for the transfer.
460 @param CommandList The command list will be used for the transfer.
461 @param AtapiCommand The atapi command will be used for the transfer.
462 @param AtapiCommandLength The length of the atapi command.
463 @param CommandSlotNumber The command slot will be used for the transfer.
464 @param DataPhysicalAddr The pointer to the data buffer pci bus master address.
465 @param DataLength The data count to be transferred.
466
467 **/
468 VOID
469 EFIAPI
470 AhciBuildCommand (
471 IN EFI_PCI_IO_PROTOCOL *PciIo,
472 IN EFI_AHCI_REGISTERS *AhciRegisters,
473 IN UINT8 Port,
474 IN UINT8 PortMultiplier,
475 IN EFI_AHCI_COMMAND_FIS *CommandFis,
476 IN EFI_AHCI_COMMAND_LIST *CommandList,
477 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
478 IN UINT8 AtapiCommandLength,
479 IN UINT8 CommandSlotNumber,
480 IN OUT VOID *DataPhysicalAddr,
481 IN UINT32 DataLength
482 )
483 {
484 UINT64 BaseAddr;
485 UINT32 PrdtNumber;
486 UINT32 PrdtIndex;
487 UINTN RemainedData;
488 UINTN MemAddr;
489 DATA_64 Data64;
490 UINT32 Offset;
491
492 //
493 // Filling the PRDT
494 //
495 PrdtNumber = (UINT32)DivU64x32 (((UINT64)DataLength + EFI_AHCI_MAX_DATA_PER_PRDT - 1), EFI_AHCI_MAX_DATA_PER_PRDT);
496
497 //
498 // According to AHCI 1.3 spec, a PRDT entry can point to a maximum 4MB data block.
499 // It also limits that the maximum amount of the PRDT entry in the command table
500 // is 65535.
501 //
502 ASSERT (PrdtNumber <= 65535);
503
504 Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFis) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
505
506 BaseAddr = Data64.Uint64;
507
508 ZeroMem ((VOID *)((UINTN) BaseAddr), sizeof (EFI_AHCI_RECEIVED_FIS));
509
510 ZeroMem (AhciRegisters->AhciCommandTable, sizeof (EFI_AHCI_COMMAND_TABLE));
511
512 CommandFis->AhciCFisPmNum = PortMultiplier;
513
514 CopyMem (&AhciRegisters->AhciCommandTable->CommandFis, CommandFis, sizeof (EFI_AHCI_COMMAND_FIS));
515
516 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
517 if (AtapiCommand != NULL) {
518 CopyMem (
519 &AhciRegisters->AhciCommandTable->AtapiCmd,
520 AtapiCommand,
521 AtapiCommandLength
522 );
523
524 CommandList->AhciCmdA = 1;
525 CommandList->AhciCmdP = 1;
526
527 AhciOrReg (PciIo, Offset, (EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
528 } else {
529 AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
530 }
531
532 RemainedData = (UINTN) DataLength;
533 MemAddr = (UINTN) DataPhysicalAddr;
534 CommandList->AhciCmdPrdtl = PrdtNumber;
535
536 for (PrdtIndex = 0; PrdtIndex < PrdtNumber; PrdtIndex++) {
537 if (RemainedData < EFI_AHCI_MAX_DATA_PER_PRDT) {
538 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = (UINT32)RemainedData - 1;
539 } else {
540 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = EFI_AHCI_MAX_DATA_PER_PRDT - 1;
541 }
542
543 Data64.Uint64 = (UINT64)MemAddr;
544 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDba = Data64.Uint32.Lower32;
545 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbau = Data64.Uint32.Upper32;
546 RemainedData -= EFI_AHCI_MAX_DATA_PER_PRDT;
547 MemAddr += EFI_AHCI_MAX_DATA_PER_PRDT;
548 }
549
550 //
551 // Set the last PRDT to Interrupt On Complete
552 //
553 if (PrdtNumber > 0) {
554 AhciRegisters->AhciCommandTable->PrdtTable[PrdtNumber - 1].AhciPrdtIoc = 1;
555 }
556
557 CopyMem (
558 (VOID *) ((UINTN) AhciRegisters->AhciCmdList + (UINTN) CommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST)),
559 CommandList,
560 sizeof (EFI_AHCI_COMMAND_LIST)
561 );
562
563 Data64.Uint64 = (UINT64)(UINTN) AhciRegisters->AhciCommandTablePciAddr;
564 AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtba = Data64.Uint32.Lower32;
565 AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtbau = Data64.Uint32.Upper32;
566 AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdPmp = PortMultiplier;
567
568 }
569
570 /**
571 Build a command FIS.
572
573 @param CmdFis A pointer to the EFI_AHCI_COMMAND_FIS data structure.
574 @param AtaCommandBlock A pointer to the AhciBuildCommandFis data structure.
575
576 **/
577 VOID
578 EFIAPI
579 AhciBuildCommandFis (
580 IN OUT EFI_AHCI_COMMAND_FIS *CmdFis,
581 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock
582 )
583 {
584 ZeroMem (CmdFis, sizeof (EFI_AHCI_COMMAND_FIS));
585
586 CmdFis->AhciCFisType = EFI_AHCI_FIS_REGISTER_H2D;
587 //
588 // Indicator it's a command
589 //
590 CmdFis->AhciCFisCmdInd = 0x1;
591 CmdFis->AhciCFisCmd = AtaCommandBlock->AtaCommand;
592
593 CmdFis->AhciCFisFeature = AtaCommandBlock->AtaFeatures;
594 CmdFis->AhciCFisFeatureExp = AtaCommandBlock->AtaFeaturesExp;
595
596 CmdFis->AhciCFisSecNum = AtaCommandBlock->AtaSectorNumber;
597 CmdFis->AhciCFisSecNumExp = AtaCommandBlock->AtaSectorNumberExp;
598
599 CmdFis->AhciCFisClyLow = AtaCommandBlock->AtaCylinderLow;
600 CmdFis->AhciCFisClyLowExp = AtaCommandBlock->AtaCylinderLowExp;
601
602 CmdFis->AhciCFisClyHigh = AtaCommandBlock->AtaCylinderHigh;
603 CmdFis->AhciCFisClyHighExp = AtaCommandBlock->AtaCylinderHighExp;
604
605 CmdFis->AhciCFisSecCount = AtaCommandBlock->AtaSectorCount;
606 CmdFis->AhciCFisSecCountExp = AtaCommandBlock->AtaSectorCountExp;
607
608 CmdFis->AhciCFisDevHead = (UINT8) (AtaCommandBlock->AtaDeviceHead | 0xE0);
609 }
610
611 /**
612 Wait until SATA device reports it is ready for operation.
613
614 @param[in] PciIo Pointer to AHCI controller PciIo.
615 @param[in] Port SATA port index on which to reset.
616
617 @retval EFI_SUCCESS Device ready for operation.
618 @retval EFI_TIMEOUT Device failed to get ready within required period.
619 **/
620 EFI_STATUS
621 AhciWaitDeviceReady (
622 IN EFI_PCI_IO_PROTOCOL *PciIo,
623 IN UINT8 Port
624 )
625 {
626 UINT32 PhyDetectDelay;
627 UINT32 Data;
628 UINT32 Offset;
629
630 //
631 // According to SATA1.0a spec section 5.2, we need to wait for PxTFD.BSY and PxTFD.DRQ
632 // and PxTFD.ERR to be zero. The maximum wait time is 16s which is defined at ATA spec.
633 //
634 PhyDetectDelay = 16 * 1000;
635 do {
636 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
637 if (AhciReadReg(PciIo, Offset) != 0) {
638 AhciWriteReg (PciIo, Offset, AhciReadReg(PciIo, Offset));
639 }
640 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
641
642 Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_TFD_MASK;
643 if (Data == 0) {
644 break;
645 }
646
647 MicroSecondDelay (1000);
648 PhyDetectDelay--;
649 } while (PhyDetectDelay > 0);
650
651 if (PhyDetectDelay == 0) {
652 DEBUG ((DEBUG_ERROR, "Port %d Device not ready (TFD=0x%X)\n", Port, Data));
653 return EFI_TIMEOUT;
654 } else {
655 return EFI_SUCCESS;
656 }
657 }
658
659
660 /**
661 Reset the SATA port. Algorithm follows AHCI spec 1.3.1 section 10.4.2
662
663 @param[in] PciIo Pointer to AHCI controller PciIo.
664 @param[in] Port SATA port index on which to reset.
665
666 @retval EFI_SUCCESS Port reset.
667 @retval Others Failed to reset the port.
668 **/
669 EFI_STATUS
670 AhciResetPort (
671 IN EFI_PCI_IO_PROTOCOL *PciIo,
672 IN UINT8 Port
673 )
674 {
675 UINT32 Offset;
676 EFI_STATUS Status;
677
678 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;
679 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_SCTL_DET_INIT);
680 //
681 // SW is required to keep DET set to 0x1 at least for 1 milisecond to ensure that
682 // at least one COMRESET signal is sent.
683 //
684 MicroSecondDelay(1000);
685 AhciAndReg (PciIo, Offset, ~(UINT32)EFI_AHCI_PORT_SSTS_DET_MASK);
686
687 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
688 Status = AhciWaitMmioSet (PciIo, Offset, EFI_AHCI_PORT_SSTS_DET_MASK, EFI_AHCI_PORT_SSTS_DET_PCE, ATA_ATAPI_TIMEOUT);
689 if (EFI_ERROR (Status)) {
690 return Status;
691 }
692
693 return AhciWaitDeviceReady (PciIo, Port);
694 }
695
696 /**
697 Recovers the SATA port from error condition.
698 This function implements algorithm described in
699 AHCI spec 1.3.1 section 6.2.2
700
701 @param[in] PciIo Pointer to AHCI controller PciIo.
702 @param[in] Port SATA port index on which to check.
703
704 @retval EFI_SUCCESS Port recovered.
705 @retval Others Failed to recover port.
706 **/
707 EFI_STATUS
708 AhciRecoverPortError (
709 IN EFI_PCI_IO_PROTOCOL *PciIo,
710 IN UINT8 Port
711 )
712 {
713 UINT32 Offset;
714 UINT32 PortInterrupt;
715 UINT32 PortTfd;
716 EFI_STATUS Status;
717
718 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
719 PortInterrupt = AhciReadReg (PciIo, Offset);
720 if ((PortInterrupt & EFI_AHCI_PORT_IS_FATAL_ERROR_MASK) == 0) {
721 //
722 // No fatal error detected. Exit with success as port should still be operational.
723 // No need to clear IS as it will be cleared when the next command starts.
724 //
725 return EFI_SUCCESS;
726 }
727
728 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
729 AhciAndReg (PciIo, Offset, ~(UINT32)EFI_AHCI_PORT_CMD_ST);
730
731 Status = AhciWaitMmioSet (PciIo, Offset, EFI_AHCI_PORT_CMD_CR, 0, ATA_ATAPI_TIMEOUT);
732 if (EFI_ERROR (Status)) {
733 DEBUG ((DEBUG_ERROR, "Ahci port %d is in hung state, aborting recovery\n", Port));
734 return Status;
735 }
736
737 //
738 // If TFD.BSY or TFD.DRQ is still set it means that drive is hung and software has
739 // to reset it before sending any additional commands.
740 //
741 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
742 PortTfd = AhciReadReg (PciIo, Offset);
743 if ((PortTfd & (EFI_AHCI_PORT_TFD_BSY | EFI_AHCI_PORT_TFD_DRQ)) != 0) {
744 Status = AhciResetPort (PciIo, Port);
745 if (EFI_ERROR (Status)) {
746 DEBUG ((DEBUG_ERROR, "Failed to reset the port %d\n", Port));
747 }
748 }
749
750 return EFI_SUCCESS;
751 }
752
753 /**
754 Checks if specified FIS has been received.
755
756 @param[in] PciIo Pointer to AHCI controller PciIo.
757 @param[in] Port SATA port index on which to check.
758 @param[in] FisType FIS type for which to check.
759
760 @retval EFI_SUCCESS FIS received.
761 @retval EFI_NOT_READY FIS not received yet.
762 @retval EFI_DEVICE_ERROR AHCI controller reported an error on port.
763 **/
764 EFI_STATUS
765 AhciCheckFisReceived (
766 IN EFI_PCI_IO_PROTOCOL *PciIo,
767 IN UINT8 Port,
768 IN SATA_FIS_TYPE FisType
769 )
770 {
771 UINT32 Offset;
772 UINT32 PortInterrupt;
773 UINT32 PortTfd;
774
775 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
776 PortInterrupt = AhciReadReg (PciIo, Offset);
777 if ((PortInterrupt & EFI_AHCI_PORT_IS_ERROR_MASK) != 0) {
778 DEBUG ((DEBUG_ERROR, "AHCI: Error interrupt reported PxIS: %X\n", PortInterrupt));
779 return EFI_DEVICE_ERROR;
780 }
781 //
782 // For PIO setup FIS - According to SATA 2.6 spec section 11.7, D2h FIS means an error encountered.
783 // But Qemu and Marvel 9230 sata controller may just receive a D2h FIS from device
784 // after the transaction is finished successfully.
785 // To get better device compatibilities, we further check if the PxTFD's ERR bit is set.
786 // By this way, we can know if there is a real error happened.
787 //
788 if (((FisType == SataFisD2H) && ((PortInterrupt & EFI_AHCI_PORT_IS_DHRS) != 0)) ||
789 ((FisType == SataFisPioSetup) && (PortInterrupt & (EFI_AHCI_PORT_IS_PSS | EFI_AHCI_PORT_IS_DHRS)) != 0) ||
790 ((FisType == SataFisDmaSetup) && (PortInterrupt & (EFI_AHCI_PORT_IS_DSS | EFI_AHCI_PORT_IS_DHRS)) != 0)) {
791 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
792 PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
793 if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
794 return EFI_DEVICE_ERROR;
795 } else {
796 return EFI_SUCCESS;
797 }
798 }
799
800 return EFI_NOT_READY;
801 }
802
803 /**
804 Waits until specified FIS has been received.
805
806 @param[in] PciIo Pointer to AHCI controller PciIo.
807 @param[in] Port SATA port index on which to check.
808 @param[in] Timeout Time after which function should stop polling.
809 @param[in] FisType FIS type for which to check.
810
811 @retval EFI_SUCCESS FIS received.
812 @retval EFI_TIMEOUT FIS failed to arrive within a specified time period.
813 @retval EFI_DEVICE_ERROR AHCI controller reported an error on port.
814 **/
815 EFI_STATUS
816 AhciWaitUntilFisReceived (
817 IN EFI_PCI_IO_PROTOCOL *PciIo,
818 IN UINT8 Port,
819 IN UINT64 Timeout,
820 IN SATA_FIS_TYPE FisType
821 )
822 {
823 EFI_STATUS Status;
824 BOOLEAN InfiniteWait;
825 UINT64 Delay;
826
827 Delay = DivU64x32 (Timeout, 1000) + 1;
828 if (Timeout == 0) {
829 InfiniteWait = TRUE;
830 } else {
831 InfiniteWait = FALSE;
832 }
833
834 do {
835 Status = AhciCheckFisReceived (PciIo, Port, FisType);
836 if (Status != EFI_NOT_READY) {
837 return Status;
838 }
839 //
840 // Stall for 100 microseconds.
841 //
842 MicroSecondDelay (100);
843 Delay--;
844 } while (InfiniteWait || (Delay > 0));
845
846 return EFI_TIMEOUT;
847 }
848
849 /**
850 Prints contents of the ATA command block into the debug port.
851
852 @param[in] AtaCommandBlock AtaCommandBlock to print.
853 @param[in] DebugLevel Debug level on which to print.
854 **/
855 VOID
856 AhciPrintCommandBlock (
857 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
858 IN UINT32 DebugLevel
859 )
860 {
861 DEBUG ((DebugLevel, "ATA COMMAND BLOCK:\n"));
862 DEBUG ((DebugLevel, "AtaCommand: %d\n", AtaCommandBlock->AtaCommand));
863 DEBUG ((DebugLevel, "AtaFeatures: %X\n", AtaCommandBlock->AtaFeatures));
864 DEBUG ((DebugLevel, "AtaSectorNumber: %d\n", AtaCommandBlock->AtaSectorNumber));
865 DEBUG ((DebugLevel, "AtaCylinderLow: %X\n", AtaCommandBlock->AtaCylinderHigh));
866 DEBUG ((DebugLevel, "AtaCylinderHigh: %X\n", AtaCommandBlock->AtaCylinderHigh));
867 DEBUG ((DebugLevel, "AtaDeviceHead: %d\n", AtaCommandBlock->AtaDeviceHead));
868 DEBUG ((DebugLevel, "AtaSectorNumberExp: %d\n", AtaCommandBlock->AtaSectorNumberExp));
869 DEBUG ((DebugLevel, "AtaCylinderLowExp: %X\n", AtaCommandBlock->AtaCylinderLowExp));
870 DEBUG ((DebugLevel, "AtaCylinderHighExp: %X\n", AtaCommandBlock->AtaCylinderHighExp));
871 DEBUG ((DebugLevel, "AtaFeaturesExp: %X\n", AtaCommandBlock->AtaFeaturesExp));
872 DEBUG ((DebugLevel, "AtaSectorCount: %d\n", AtaCommandBlock->AtaSectorCount));
873 DEBUG ((DebugLevel, "AtaSectorCountExp: %d\n", AtaCommandBlock->AtaSectorCountExp));
874 }
875
876 /**
877 Prints contents of the ATA status block into the debug port.
878
879 @param[in] AtaStatusBlock AtaStatusBlock to print.
880 @param[in] DebugLevel Debug level on which to print.
881 **/
882 VOID
883 AhciPrintStatusBlock (
884 IN EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
885 IN UINT32 DebugLevel
886 )
887 {
888 //
889 // Skip NULL pointer
890 //
891 if (AtaStatusBlock == NULL) {
892 return;
893 }
894
895 //
896 // Only print status and error since we have all of the rest printed as
897 // a part of command block print.
898 //
899 DEBUG ((DebugLevel, "ATA STATUS BLOCK:\n"));
900 DEBUG ((DebugLevel, "AtaStatus: %d\n", AtaStatusBlock->AtaStatus));
901 DEBUG ((DebugLevel, "AtaError: %d\n", AtaStatusBlock->AtaError));
902 }
903
904 /**
905 Start a PIO data transfer on specific port.
906
907 @param[in] PciIo The PCI IO protocol instance.
908 @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
909 @param[in] Port The number of port.
910 @param[in] PortMultiplier The timeout value of stop.
911 @param[in] AtapiCommand The atapi command will be used for the
912 transfer.
913 @param[in] AtapiCommandLength The length of the atapi command.
914 @param[in] Read The transfer direction.
915 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
916 @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
917 @param[in, out] MemoryAddr The pointer to the data buffer.
918 @param[in] DataCount The data count to be transferred.
919 @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
920 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
921 used by non-blocking mode.
922
923 @retval EFI_DEVICE_ERROR The PIO data transfer abort with error occurs.
924 @retval EFI_TIMEOUT The operation is time out.
925 @retval EFI_UNSUPPORTED The device is not ready for transfer.
926 @retval EFI_SUCCESS The PIO data transfer executes successfully.
927
928 **/
929 EFI_STATUS
930 EFIAPI
931 AhciPioTransfer (
932 IN EFI_PCI_IO_PROTOCOL *PciIo,
933 IN EFI_AHCI_REGISTERS *AhciRegisters,
934 IN UINT8 Port,
935 IN UINT8 PortMultiplier,
936 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
937 IN UINT8 AtapiCommandLength,
938 IN BOOLEAN Read,
939 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
940 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
941 IN OUT VOID *MemoryAddr,
942 IN UINT32 DataCount,
943 IN UINT64 Timeout,
944 IN ATA_NONBLOCK_TASK *Task
945 )
946 {
947 EFI_STATUS Status;
948 EFI_PHYSICAL_ADDRESS PhyAddr;
949 VOID *Map;
950 UINTN MapLength;
951 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
952 EFI_AHCI_COMMAND_FIS CFis;
953 EFI_AHCI_COMMAND_LIST CmdList;
954 UINT32 PrdCount;
955 UINT32 Retry;
956
957 if (Read) {
958 Flag = EfiPciIoOperationBusMasterWrite;
959 } else {
960 Flag = EfiPciIoOperationBusMasterRead;
961 }
962
963 //
964 // construct command list and command table with pci bus address
965 //
966 MapLength = DataCount;
967 Status = PciIo->Map (
968 PciIo,
969 Flag,
970 MemoryAddr,
971 &MapLength,
972 &PhyAddr,
973 &Map
974 );
975
976 if (EFI_ERROR (Status) || (DataCount != MapLength)) {
977 return EFI_BAD_BUFFER_SIZE;
978 }
979
980 //
981 // Package read needed
982 //
983 AhciBuildCommandFis (&CFis, AtaCommandBlock);
984
985 ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
986
987 CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
988 CmdList.AhciCmdW = Read ? 0 : 1;
989
990 for (Retry = 0; Retry < AHCI_COMMAND_RETRIES; Retry++) {
991 AhciBuildCommand (
992 PciIo,
993 AhciRegisters,
994 Port,
995 PortMultiplier,
996 &CFis,
997 &CmdList,
998 AtapiCommand,
999 AtapiCommandLength,
1000 0,
1001 (VOID *)(UINTN)PhyAddr,
1002 DataCount
1003 );
1004
1005 DEBUG ((DEBUG_VERBOSE, "Starting command for PIO transfer:\n"));
1006 AhciPrintCommandBlock (AtaCommandBlock, DEBUG_VERBOSE);
1007 Status = AhciStartCommand (
1008 PciIo,
1009 Port,
1010 0,
1011 Timeout
1012 );
1013 if (EFI_ERROR (Status)) {
1014 break;
1015 }
1016
1017 if (Read && (AtapiCommand == 0)) {
1018 Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisPioSetup);
1019 if (Status == EFI_SUCCESS) {
1020 PrdCount = *(volatile UINT32 *) (&(AhciRegisters->AhciCmdList[0].AhciCmdPrdbc));
1021 if (PrdCount == DataCount) {
1022 Status = EFI_SUCCESS;
1023 } else {
1024 Status = EFI_DEVICE_ERROR;
1025 }
1026 }
1027 } else {
1028 Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisD2H);
1029 }
1030
1031 if (Status == EFI_DEVICE_ERROR) {
1032 DEBUG ((DEBUG_ERROR, "PIO command failed at retry %d\n", Retry));
1033 Status = AhciRecoverPortError (PciIo, Port);
1034 if (EFI_ERROR (Status)) {
1035 break;
1036 }
1037 } else {
1038 break;
1039 }
1040 }
1041
1042 AhciStopCommand (
1043 PciIo,
1044 Port,
1045 Timeout
1046 );
1047
1048 AhciDisableFisReceive (
1049 PciIo,
1050 Port,
1051 Timeout
1052 );
1053
1054 PciIo->Unmap (
1055 PciIo,
1056 Map
1057 );
1058
1059 AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);
1060
1061 if (Status == EFI_DEVICE_ERROR) {
1062 DEBUG ((DEBUG_ERROR, "Failed to execute command for PIO transfer:\n"));
1063 //
1064 // Repeat command block here to make sure it is printed on
1065 // device error debug level.
1066 //
1067 AhciPrintCommandBlock (AtaCommandBlock, DEBUG_ERROR);
1068 AhciPrintStatusBlock (AtaStatusBlock, DEBUG_ERROR);
1069 } else {
1070 AhciPrintStatusBlock (AtaStatusBlock, DEBUG_VERBOSE);
1071 }
1072
1073 return Status;
1074 }
1075
1076 /**
1077 Start a DMA data transfer on specific port
1078
1079 @param[in] Instance The ATA_ATAPI_PASS_THRU_INSTANCE protocol instance.
1080 @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1081 @param[in] Port The number of port.
1082 @param[in] PortMultiplier The timeout value of stop.
1083 @param[in] AtapiCommand The atapi command will be used for the
1084 transfer.
1085 @param[in] AtapiCommandLength The length of the atapi command.
1086 @param[in] Read The transfer direction.
1087 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
1088 @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
1089 @param[in, out] MemoryAddr The pointer to the data buffer.
1090 @param[in] DataCount The data count to be transferred.
1091 @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
1092 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1093 used by non-blocking mode.
1094
1095 @retval EFI_DEVICE_ERROR The DMA data transfer abort with error occurs.
1096 @retval EFI_TIMEOUT The operation is time out.
1097 @retval EFI_UNSUPPORTED The device is not ready for transfer.
1098 @retval EFI_SUCCESS The DMA data transfer executes successfully.
1099
1100 **/
1101 EFI_STATUS
1102 EFIAPI
1103 AhciDmaTransfer (
1104 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
1105 IN EFI_AHCI_REGISTERS *AhciRegisters,
1106 IN UINT8 Port,
1107 IN UINT8 PortMultiplier,
1108 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
1109 IN UINT8 AtapiCommandLength,
1110 IN BOOLEAN Read,
1111 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1112 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
1113 IN OUT VOID *MemoryAddr,
1114 IN UINT32 DataCount,
1115 IN UINT64 Timeout,
1116 IN ATA_NONBLOCK_TASK *Task
1117 )
1118 {
1119 EFI_STATUS Status;
1120 EFI_PHYSICAL_ADDRESS PhyAddr;
1121 VOID *Map;
1122 UINTN MapLength;
1123 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1124 EFI_AHCI_COMMAND_FIS CFis;
1125 EFI_AHCI_COMMAND_LIST CmdList;
1126 EFI_PCI_IO_PROTOCOL *PciIo;
1127 EFI_TPL OldTpl;
1128 UINT32 Retry;
1129
1130 Map = NULL;
1131 PciIo = Instance->PciIo;
1132
1133 if (PciIo == NULL) {
1134 return EFI_INVALID_PARAMETER;
1135 }
1136
1137 //
1138 // Set Status to suppress incorrect compiler/analyzer warnings
1139 //
1140 Status = EFI_SUCCESS;
1141
1142 //
1143 // DMA buffer allocation. Needs to be done only once for both sync and async
1144 // DMA transfers irrespective of number of retries.
1145 //
1146 if ((Task == NULL) || ((Task != NULL) && (Task->Map == NULL))) {
1147 if (Read) {
1148 Flag = EfiPciIoOperationBusMasterWrite;
1149 } else {
1150 Flag = EfiPciIoOperationBusMasterRead;
1151 }
1152
1153 MapLength = DataCount;
1154 Status = PciIo->Map (
1155 PciIo,
1156 Flag,
1157 MemoryAddr,
1158 &MapLength,
1159 &PhyAddr,
1160 &Map
1161 );
1162
1163 if (EFI_ERROR (Status) || (DataCount != MapLength)) {
1164 return EFI_BAD_BUFFER_SIZE;
1165 }
1166 if (Task != NULL) {
1167 Task->Map = Map;
1168 }
1169 }
1170
1171 if (Task == NULL || (Task != NULL && !Task->IsStart)) {
1172 AhciBuildCommandFis (&CFis, AtaCommandBlock);
1173
1174 ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
1175
1176 CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
1177 CmdList.AhciCmdW = Read ? 0 : 1;
1178 }
1179
1180 if (Task == NULL) {
1181 //
1182 // Before starting the Blocking BlockIO operation, push to finish all non-blocking
1183 // BlockIO tasks.
1184 // Delay 100us to simulate the blocking time out checking.
1185 //
1186 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1187 while (!IsListEmpty (&Instance->NonBlockingTaskList)) {
1188 AsyncNonBlockingTransferRoutine (NULL, Instance);
1189 //
1190 // Stall for 100us.
1191 //
1192 MicroSecondDelay (100);
1193 }
1194 gBS->RestoreTPL (OldTpl);
1195 for (Retry = 0; Retry < AHCI_COMMAND_RETRIES; Retry++) {
1196 AhciBuildCommand (
1197 PciIo,
1198 AhciRegisters,
1199 Port,
1200 PortMultiplier,
1201 &CFis,
1202 &CmdList,
1203 AtapiCommand,
1204 AtapiCommandLength,
1205 0,
1206 (VOID *)(UINTN)PhyAddr,
1207 DataCount
1208 );
1209
1210 DEBUG ((DEBUG_VERBOSE, "Starting command for sync DMA transfer:\n"));
1211 AhciPrintCommandBlock (AtaCommandBlock, DEBUG_VERBOSE);
1212 Status = AhciStartCommand (
1213 PciIo,
1214 Port,
1215 0,
1216 Timeout
1217 );
1218 if (EFI_ERROR (Status)) {
1219 break;
1220 }
1221 Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisD2H);
1222 if (Status == EFI_DEVICE_ERROR) {
1223 DEBUG ((DEBUG_ERROR, "DMA command failed at retry: %d\n", Retry));
1224 Status = AhciRecoverPortError (PciIo, Port);
1225 if (EFI_ERROR (Status)) {
1226 break;
1227 }
1228 } else {
1229 break;
1230 }
1231 }
1232 } else {
1233 if (!Task->IsStart) {
1234 AhciBuildCommand (
1235 PciIo,
1236 AhciRegisters,
1237 Port,
1238 PortMultiplier,
1239 &CFis,
1240 &CmdList,
1241 AtapiCommand,
1242 AtapiCommandLength,
1243 0,
1244 (VOID *)(UINTN)PhyAddr,
1245 DataCount
1246 );
1247
1248 DEBUG ((DEBUG_VERBOSE, "Starting command for async DMA transfer:\n"));
1249 AhciPrintCommandBlock (AtaCommandBlock, DEBUG_VERBOSE);
1250 Status = AhciStartCommand (
1251 PciIo,
1252 Port,
1253 0,
1254 Timeout
1255 );
1256 if (!EFI_ERROR (Status)) {
1257 Task->IsStart = TRUE;
1258 }
1259 }
1260 if (Task->IsStart) {
1261 Status = AhciCheckFisReceived (PciIo, Port, SataFisD2H);
1262 if (Status == EFI_DEVICE_ERROR) {
1263 DEBUG ((DEBUG_ERROR, "DMA command failed at retry: %d\n", Task->RetryTimes));
1264 Status = AhciRecoverPortError (PciIo, Port);
1265 //
1266 // If recovery passed mark the Task as not started and change the status
1267 // to EFI_NOT_READY. This will make the higher level call this function again
1268 // and on next call the command will be re-issued due to IsStart being FALSE.
1269 // This also makes the next condition decrement the RetryTimes.
1270 //
1271 if (Status == EFI_SUCCESS) {
1272 Task->IsStart = FALSE;
1273 Status = EFI_NOT_READY;
1274 }
1275 }
1276
1277 if (Status == EFI_NOT_READY) {
1278 if (!Task->InfiniteWait && Task->RetryTimes == 0) {
1279 Status = EFI_TIMEOUT;
1280 } else {
1281 Task->RetryTimes--;
1282 }
1283 }
1284 }
1285 }
1286
1287 //
1288 // For Blocking mode, the command should be stopped, the Fis should be disabled
1289 // and the PciIo should be unmapped.
1290 // For non-blocking mode, only when a error is happened (if the return status is
1291 // EFI_NOT_READY that means the command doesn't finished, try again.), first do the
1292 // context cleanup, then set the packet's Asb status.
1293 //
1294 if (Task == NULL ||
1295 ((Task != NULL) && (Status != EFI_NOT_READY))
1296 ) {
1297 AhciStopCommand (
1298 PciIo,
1299 Port,
1300 Timeout
1301 );
1302
1303 AhciDisableFisReceive (
1304 PciIo,
1305 Port,
1306 Timeout
1307 );
1308
1309 PciIo->Unmap (
1310 PciIo,
1311 (Task != NULL) ? Task->Map : Map
1312 );
1313
1314 if (Task != NULL) {
1315 Task->Packet->Asb->AtaStatus = 0x01;
1316 }
1317 }
1318
1319 AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);
1320
1321 if (Status == EFI_DEVICE_ERROR) {
1322 DEBUG ((DEBUG_ERROR, "Failed to execute command for DMA transfer:\n"));
1323 //
1324 // Repeat command block here to make sure it is printed on
1325 // device error debug level.
1326 //
1327 AhciPrintCommandBlock (AtaCommandBlock, DEBUG_ERROR);
1328 AhciPrintStatusBlock (AtaStatusBlock, DEBUG_ERROR);
1329 } else {
1330 AhciPrintStatusBlock (AtaStatusBlock, DEBUG_VERBOSE);
1331 }
1332
1333 return Status;
1334 }
1335
1336 /**
1337 Start a non data transfer on specific port.
1338
1339 @param[in] PciIo The PCI IO protocol instance.
1340 @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1341 @param[in] Port The number of port.
1342 @param[in] PortMultiplier The timeout value of stop.
1343 @param[in] AtapiCommand The atapi command will be used for the
1344 transfer.
1345 @param[in] AtapiCommandLength The length of the atapi command.
1346 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
1347 @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
1348 @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
1349 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1350 used by non-blocking mode.
1351
1352 @retval EFI_DEVICE_ERROR The non data transfer abort with error occurs.
1353 @retval EFI_TIMEOUT The operation is time out.
1354 @retval EFI_UNSUPPORTED The device is not ready for transfer.
1355 @retval EFI_SUCCESS The non data transfer executes successfully.
1356
1357 **/
1358 EFI_STATUS
1359 EFIAPI
1360 AhciNonDataTransfer (
1361 IN EFI_PCI_IO_PROTOCOL *PciIo,
1362 IN EFI_AHCI_REGISTERS *AhciRegisters,
1363 IN UINT8 Port,
1364 IN UINT8 PortMultiplier,
1365 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
1366 IN UINT8 AtapiCommandLength,
1367 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1368 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
1369 IN UINT64 Timeout,
1370 IN ATA_NONBLOCK_TASK *Task
1371 )
1372 {
1373 EFI_STATUS Status;
1374 EFI_AHCI_COMMAND_FIS CFis;
1375 EFI_AHCI_COMMAND_LIST CmdList;
1376 UINT32 Retry;
1377
1378 //
1379 // Package read needed
1380 //
1381 AhciBuildCommandFis (&CFis, AtaCommandBlock);
1382
1383 ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
1384
1385 CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
1386
1387 for (Retry = 0; Retry < AHCI_COMMAND_RETRIES; Retry++) {
1388 AhciBuildCommand (
1389 PciIo,
1390 AhciRegisters,
1391 Port,
1392 PortMultiplier,
1393 &CFis,
1394 &CmdList,
1395 AtapiCommand,
1396 AtapiCommandLength,
1397 0,
1398 NULL,
1399 0
1400 );
1401
1402 DEBUG ((DEBUG_VERBOSE, "Starting command for non data transfer:\n"));
1403 AhciPrintCommandBlock (AtaCommandBlock, DEBUG_VERBOSE);
1404 Status = AhciStartCommand (
1405 PciIo,
1406 Port,
1407 0,
1408 Timeout
1409 );
1410 if (EFI_ERROR (Status)) {
1411 break;
1412 }
1413
1414 Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisD2H);
1415 if (Status == EFI_DEVICE_ERROR) {
1416 DEBUG ((DEBUG_ERROR, "Non data transfer failed at retry %d\n", Retry));
1417 Status = AhciRecoverPortError (PciIo, Port);
1418 if (EFI_ERROR (Status)) {
1419 break;
1420 }
1421 } else {
1422 break;
1423 }
1424 }
1425
1426 AhciStopCommand (
1427 PciIo,
1428 Port,
1429 Timeout
1430 );
1431
1432 AhciDisableFisReceive (
1433 PciIo,
1434 Port,
1435 Timeout
1436 );
1437
1438 AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);
1439
1440 if (Status == EFI_DEVICE_ERROR) {
1441 DEBUG ((DEBUG_ERROR, "Failed to execute command for non data transfer:\n"));
1442 //
1443 // Repeat command block here to make sure it is printed on
1444 // device error debug level.
1445 //
1446 AhciPrintCommandBlock (AtaCommandBlock, DEBUG_ERROR);
1447 AhciPrintStatusBlock (AtaStatusBlock, DEBUG_ERROR);
1448 } else {
1449 AhciPrintStatusBlock (AtaStatusBlock, DEBUG_VERBOSE);
1450 }
1451
1452 return Status;
1453 }
1454
1455 /**
1456 Stop command running for giving port
1457
1458 @param PciIo The PCI IO protocol instance.
1459 @param Port The number of port.
1460 @param Timeout The timeout value of stop, uses 100ns as a unit.
1461
1462 @retval EFI_DEVICE_ERROR The command stop unsuccessfully.
1463 @retval EFI_TIMEOUT The operation is time out.
1464 @retval EFI_SUCCESS The command stop successfully.
1465
1466 **/
1467 EFI_STATUS
1468 EFIAPI
1469 AhciStopCommand (
1470 IN EFI_PCI_IO_PROTOCOL *PciIo,
1471 IN UINT8 Port,
1472 IN UINT64 Timeout
1473 )
1474 {
1475 UINT32 Offset;
1476 UINT32 Data;
1477
1478 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1479 Data = AhciReadReg (PciIo, Offset);
1480
1481 if ((Data & (EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_CR)) == 0) {
1482 return EFI_SUCCESS;
1483 }
1484
1485 if ((Data & EFI_AHCI_PORT_CMD_ST) != 0) {
1486 AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_ST));
1487 }
1488
1489 return AhciWaitMmioSet (
1490 PciIo,
1491 Offset,
1492 EFI_AHCI_PORT_CMD_CR,
1493 0,
1494 Timeout
1495 );
1496 }
1497
1498 /**
1499 Start command for give slot on specific port.
1500
1501 @param PciIo The PCI IO protocol instance.
1502 @param Port The number of port.
1503 @param CommandSlot The number of Command Slot.
1504 @param Timeout The timeout value of start, uses 100ns as a unit.
1505
1506 @retval EFI_DEVICE_ERROR The command start unsuccessfully.
1507 @retval EFI_TIMEOUT The operation is time out.
1508 @retval EFI_SUCCESS The command start successfully.
1509
1510 **/
1511 EFI_STATUS
1512 EFIAPI
1513 AhciStartCommand (
1514 IN EFI_PCI_IO_PROTOCOL *PciIo,
1515 IN UINT8 Port,
1516 IN UINT8 CommandSlot,
1517 IN UINT64 Timeout
1518 )
1519 {
1520 UINT32 CmdSlotBit;
1521 EFI_STATUS Status;
1522 UINT32 PortStatus;
1523 UINT32 StartCmd;
1524 UINT32 PortTfd;
1525 UINT32 Offset;
1526 UINT32 Capability;
1527
1528 //
1529 // Collect AHCI controller information
1530 //
1531 Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
1532
1533 CmdSlotBit = (UINT32) (1 << CommandSlot);
1534
1535 AhciClearPortStatus (
1536 PciIo,
1537 Port
1538 );
1539
1540 Status = AhciEnableFisReceive (
1541 PciIo,
1542 Port,
1543 Timeout
1544 );
1545
1546 if (EFI_ERROR (Status)) {
1547 return Status;
1548 }
1549
1550 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1551 PortStatus = AhciReadReg (PciIo, Offset);
1552
1553 StartCmd = 0;
1554 if ((PortStatus & EFI_AHCI_PORT_CMD_ALPE) != 0) {
1555 StartCmd = AhciReadReg (PciIo, Offset);
1556 StartCmd &= ~EFI_AHCI_PORT_CMD_ICC_MASK;
1557 StartCmd |= EFI_AHCI_PORT_CMD_ACTIVE;
1558 }
1559
1560 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
1561 PortTfd = AhciReadReg (PciIo, Offset);
1562
1563 if ((PortTfd & (EFI_AHCI_PORT_TFD_BSY | EFI_AHCI_PORT_TFD_DRQ)) != 0) {
1564 if ((Capability & BIT24) != 0) {
1565 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1566 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_CLO);
1567
1568 AhciWaitMmioSet (
1569 PciIo,
1570 Offset,
1571 EFI_AHCI_PORT_CMD_CLO,
1572 0,
1573 Timeout
1574 );
1575 }
1576 }
1577
1578 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1579 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_ST | StartCmd);
1580
1581 //
1582 // Setting the command
1583 //
1584 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;
1585 AhciAndReg (PciIo, Offset, 0);
1586 AhciOrReg (PciIo, Offset, CmdSlotBit);
1587
1588 return EFI_SUCCESS;
1589 }
1590
1591
1592 /**
1593 Do AHCI HBA reset.
1594
1595 @param PciIo The PCI IO protocol instance.
1596 @param Timeout The timeout value of reset, uses 100ns as a unit.
1597
1598 @retval EFI_DEVICE_ERROR AHCI controller is failed to complete hardware reset.
1599 @retval EFI_TIMEOUT The reset operation is time out.
1600 @retval EFI_SUCCESS AHCI controller is reset successfully.
1601
1602 **/
1603 EFI_STATUS
1604 EFIAPI
1605 AhciReset (
1606 IN EFI_PCI_IO_PROTOCOL *PciIo,
1607 IN UINT64 Timeout
1608 )
1609 {
1610 UINT64 Delay;
1611 UINT32 Value;
1612
1613 //
1614 // Make sure that GHC.AE bit is set before accessing any AHCI registers.
1615 //
1616 Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
1617
1618 if ((Value & EFI_AHCI_GHC_ENABLE) == 0) {
1619 AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
1620 }
1621
1622 AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);
1623
1624 Delay = DivU64x32(Timeout, 1000) + 1;
1625
1626 do {
1627 Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
1628
1629 if ((Value & EFI_AHCI_GHC_RESET) == 0) {
1630 break;
1631 }
1632
1633 //
1634 // Stall for 100 microseconds.
1635 //
1636 MicroSecondDelay(100);
1637
1638 Delay--;
1639 } while (Delay > 0);
1640
1641 if (Delay == 0) {
1642 return EFI_TIMEOUT;
1643 }
1644
1645 return EFI_SUCCESS;
1646 }
1647
1648 /**
1649 Send SMART Return Status command to check if the execution of SMART cmd is successful or not.
1650
1651 @param PciIo The PCI IO protocol instance.
1652 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1653 @param Port The number of port.
1654 @param PortMultiplier The port multiplier port number.
1655 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1656
1657 @retval EFI_SUCCESS Successfully get the return status of S.M.A.R.T command execution.
1658 @retval Others Fail to get return status data.
1659
1660 **/
1661 EFI_STATUS
1662 EFIAPI
1663 AhciAtaSmartReturnStatusCheck (
1664 IN EFI_PCI_IO_PROTOCOL *PciIo,
1665 IN EFI_AHCI_REGISTERS *AhciRegisters,
1666 IN UINT8 Port,
1667 IN UINT8 PortMultiplier,
1668 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
1669 )
1670 {
1671 EFI_STATUS Status;
1672 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1673 UINT8 LBAMid;
1674 UINT8 LBAHigh;
1675 UINTN FisBaseAddr;
1676 UINT32 Value;
1677
1678 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1679
1680 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
1681 AtaCommandBlock.AtaFeatures = ATA_SMART_RETURN_STATUS;
1682 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
1683 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
1684
1685 //
1686 // Send S.M.A.R.T Read Return Status command to device
1687 //
1688 Status = AhciNonDataTransfer (
1689 PciIo,
1690 AhciRegisters,
1691 (UINT8)Port,
1692 (UINT8)PortMultiplier,
1693 NULL,
1694 0,
1695 &AtaCommandBlock,
1696 AtaStatusBlock,
1697 ATA_ATAPI_TIMEOUT,
1698 NULL
1699 );
1700
1701 if (EFI_ERROR (Status)) {
1702 REPORT_STATUS_CODE (
1703 EFI_ERROR_CODE | EFI_ERROR_MINOR,
1704 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLED)
1705 );
1706 return EFI_DEVICE_ERROR;
1707 }
1708
1709 REPORT_STATUS_CODE (
1710 EFI_PROGRESS_CODE,
1711 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_ENABLE)
1712 );
1713
1714 FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
1715
1716 Value = *(UINT32 *) (FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET);
1717
1718 if ((Value & EFI_AHCI_FIS_TYPE_MASK) == EFI_AHCI_FIS_REGISTER_D2H) {
1719 LBAMid = ((UINT8 *)(UINTN)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET))[5];
1720 LBAHigh = ((UINT8 *)(UINTN)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET))[6];
1721
1722 if ((LBAMid == 0x4f) && (LBAHigh == 0xc2)) {
1723 //
1724 // The threshold exceeded condition is not detected by the device
1725 //
1726 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is not detected\n"));
1727 REPORT_STATUS_CODE (
1728 EFI_PROGRESS_CODE,
1729 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD)
1730 );
1731 } else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {
1732 //
1733 // The threshold exceeded condition is detected by the device
1734 //
1735 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is detected\n"));
1736 REPORT_STATUS_CODE (
1737 EFI_PROGRESS_CODE,
1738 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD)
1739 );
1740 }
1741 }
1742
1743 return EFI_SUCCESS;
1744 }
1745
1746 /**
1747 Enable SMART command of the disk if supported.
1748
1749 @param PciIo The PCI IO protocol instance.
1750 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1751 @param Port The number of port.
1752 @param PortMultiplier The port multiplier port number.
1753 @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
1754 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1755
1756 **/
1757 VOID
1758 EFIAPI
1759 AhciAtaSmartSupport (
1760 IN EFI_PCI_IO_PROTOCOL *PciIo,
1761 IN EFI_AHCI_REGISTERS *AhciRegisters,
1762 IN UINT8 Port,
1763 IN UINT8 PortMultiplier,
1764 IN EFI_IDENTIFY_DATA *IdentifyData,
1765 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
1766 )
1767 {
1768 EFI_STATUS Status;
1769 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1770
1771 //
1772 // Detect if the device supports S.M.A.R.T.
1773 //
1774 if ((IdentifyData->AtaData.command_set_supported_82 & 0x0001) != 0x0001) {
1775 //
1776 // S.M.A.R.T is not supported by the device
1777 //
1778 DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at port [%d] PortMultiplier [%d]!\n",
1779 Port, PortMultiplier));
1780 REPORT_STATUS_CODE (
1781 EFI_ERROR_CODE | EFI_ERROR_MINOR,
1782 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED)
1783 );
1784 } else {
1785 //
1786 // Check if the feature is enabled. If not, then enable S.M.A.R.T.
1787 //
1788 if ((IdentifyData->AtaData.command_set_feature_enb_85 & 0x0001) != 0x0001) {
1789
1790 REPORT_STATUS_CODE (
1791 EFI_PROGRESS_CODE,
1792 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLE)
1793 );
1794
1795 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1796
1797 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
1798 AtaCommandBlock.AtaFeatures = ATA_SMART_ENABLE_OPERATION;
1799 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
1800 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
1801
1802 //
1803 // Send S.M.A.R.T Enable command to device
1804 //
1805 Status = AhciNonDataTransfer (
1806 PciIo,
1807 AhciRegisters,
1808 (UINT8)Port,
1809 (UINT8)PortMultiplier,
1810 NULL,
1811 0,
1812 &AtaCommandBlock,
1813 AtaStatusBlock,
1814 ATA_ATAPI_TIMEOUT,
1815 NULL
1816 );
1817
1818
1819 if (!EFI_ERROR (Status)) {
1820 //
1821 // Send S.M.A.R.T AutoSave command to device
1822 //
1823 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1824
1825 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
1826 AtaCommandBlock.AtaFeatures = 0xD2;
1827 AtaCommandBlock.AtaSectorCount = 0xF1;
1828 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
1829 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
1830
1831 Status = AhciNonDataTransfer (
1832 PciIo,
1833 AhciRegisters,
1834 (UINT8)Port,
1835 (UINT8)PortMultiplier,
1836 NULL,
1837 0,
1838 &AtaCommandBlock,
1839 AtaStatusBlock,
1840 ATA_ATAPI_TIMEOUT,
1841 NULL
1842 );
1843 }
1844 }
1845
1846 AhciAtaSmartReturnStatusCheck (
1847 PciIo,
1848 AhciRegisters,
1849 (UINT8)Port,
1850 (UINT8)PortMultiplier,
1851 AtaStatusBlock
1852 );
1853
1854 DEBUG ((EFI_D_INFO, "Enabled S.M.A.R.T feature at port [%d] PortMultiplier [%d]!\n",
1855 Port, PortMultiplier));
1856 }
1857
1858 return ;
1859 }
1860
1861 /**
1862 Send Buffer cmd to specific device.
1863
1864 @param PciIo The PCI IO protocol instance.
1865 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1866 @param Port The number of port.
1867 @param PortMultiplier The port multiplier port number.
1868 @param Buffer The data buffer to store IDENTIFY PACKET data.
1869
1870 @retval EFI_DEVICE_ERROR The cmd abort with error occurs.
1871 @retval EFI_TIMEOUT The operation is time out.
1872 @retval EFI_UNSUPPORTED The device is not ready for executing.
1873 @retval EFI_SUCCESS The cmd executes successfully.
1874
1875 **/
1876 EFI_STATUS
1877 EFIAPI
1878 AhciIdentify (
1879 IN EFI_PCI_IO_PROTOCOL *PciIo,
1880 IN EFI_AHCI_REGISTERS *AhciRegisters,
1881 IN UINT8 Port,
1882 IN UINT8 PortMultiplier,
1883 IN OUT EFI_IDENTIFY_DATA *Buffer
1884 )
1885 {
1886 EFI_STATUS Status;
1887 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1888 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
1889
1890 if (PciIo == NULL || AhciRegisters == NULL || Buffer == NULL) {
1891 return EFI_INVALID_PARAMETER;
1892 }
1893
1894 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1895 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1896
1897 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DRIVE;
1898 AtaCommandBlock.AtaSectorCount = 1;
1899
1900 Status = AhciPioTransfer (
1901 PciIo,
1902 AhciRegisters,
1903 Port,
1904 PortMultiplier,
1905 NULL,
1906 0,
1907 TRUE,
1908 &AtaCommandBlock,
1909 &AtaStatusBlock,
1910 Buffer,
1911 sizeof (EFI_IDENTIFY_DATA),
1912 ATA_ATAPI_TIMEOUT,
1913 NULL
1914 );
1915
1916 return Status;
1917 }
1918
1919 /**
1920 Send Buffer cmd to specific device.
1921
1922 @param PciIo The PCI IO protocol instance.
1923 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1924 @param Port The number of port.
1925 @param PortMultiplier The port multiplier port number.
1926 @param Buffer The data buffer to store IDENTIFY PACKET data.
1927
1928 @retval EFI_DEVICE_ERROR The cmd abort with error occurs.
1929 @retval EFI_TIMEOUT The operation is time out.
1930 @retval EFI_UNSUPPORTED The device is not ready for executing.
1931 @retval EFI_SUCCESS The cmd executes successfully.
1932
1933 **/
1934 EFI_STATUS
1935 EFIAPI
1936 AhciIdentifyPacket (
1937 IN EFI_PCI_IO_PROTOCOL *PciIo,
1938 IN EFI_AHCI_REGISTERS *AhciRegisters,
1939 IN UINT8 Port,
1940 IN UINT8 PortMultiplier,
1941 IN OUT EFI_IDENTIFY_DATA *Buffer
1942 )
1943 {
1944 EFI_STATUS Status;
1945 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1946 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
1947
1948 if (PciIo == NULL || AhciRegisters == NULL) {
1949 return EFI_INVALID_PARAMETER;
1950 }
1951
1952 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1953 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1954
1955 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DEVICE;
1956 AtaCommandBlock.AtaSectorCount = 1;
1957
1958 Status = AhciPioTransfer (
1959 PciIo,
1960 AhciRegisters,
1961 Port,
1962 PortMultiplier,
1963 NULL,
1964 0,
1965 TRUE,
1966 &AtaCommandBlock,
1967 &AtaStatusBlock,
1968 Buffer,
1969 sizeof (EFI_IDENTIFY_DATA),
1970 ATA_ATAPI_TIMEOUT,
1971 NULL
1972 );
1973
1974 return Status;
1975 }
1976
1977 /**
1978 Send SET FEATURE cmd on specific device.
1979
1980 @param PciIo The PCI IO protocol instance.
1981 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1982 @param Port The number of port.
1983 @param PortMultiplier The port multiplier port number.
1984 @param Feature The data to send Feature register.
1985 @param FeatureSpecificData The specific data for SET FEATURE cmd.
1986 @param Timeout The timeout value of SET FEATURE cmd, uses 100ns as a unit.
1987
1988 @retval EFI_DEVICE_ERROR The cmd abort with error occurs.
1989 @retval EFI_TIMEOUT The operation is time out.
1990 @retval EFI_UNSUPPORTED The device is not ready for executing.
1991 @retval EFI_SUCCESS The cmd executes successfully.
1992
1993 **/
1994 EFI_STATUS
1995 EFIAPI
1996 AhciDeviceSetFeature (
1997 IN EFI_PCI_IO_PROTOCOL *PciIo,
1998 IN EFI_AHCI_REGISTERS *AhciRegisters,
1999 IN UINT8 Port,
2000 IN UINT8 PortMultiplier,
2001 IN UINT16 Feature,
2002 IN UINT32 FeatureSpecificData,
2003 IN UINT64 Timeout
2004 )
2005 {
2006 EFI_STATUS Status;
2007 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2008 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
2009
2010 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2011 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
2012
2013 AtaCommandBlock.AtaCommand = ATA_CMD_SET_FEATURES;
2014 AtaCommandBlock.AtaFeatures = (UINT8) Feature;
2015 AtaCommandBlock.AtaFeaturesExp = (UINT8) (Feature >> 8);
2016 AtaCommandBlock.AtaSectorCount = (UINT8) FeatureSpecificData;
2017 AtaCommandBlock.AtaSectorNumber = (UINT8) (FeatureSpecificData >> 8);
2018 AtaCommandBlock.AtaCylinderLow = (UINT8) (FeatureSpecificData >> 16);
2019 AtaCommandBlock.AtaCylinderHigh = (UINT8) (FeatureSpecificData >> 24);
2020
2021 Status = AhciNonDataTransfer (
2022 PciIo,
2023 AhciRegisters,
2024 (UINT8)Port,
2025 (UINT8)PortMultiplier,
2026 NULL,
2027 0,
2028 &AtaCommandBlock,
2029 &AtaStatusBlock,
2030 Timeout,
2031 NULL
2032 );
2033
2034 return Status;
2035 }
2036
2037 /**
2038 This function is used to send out ATAPI commands conforms to the Packet Command
2039 with PIO Protocol.
2040
2041 @param PciIo The PCI IO protocol instance.
2042 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2043 @param Port The number of port.
2044 @param PortMultiplier The number of port multiplier.
2045 @param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
2046
2047 @retval EFI_SUCCESS send out the ATAPI packet command successfully
2048 and device sends data successfully.
2049 @retval EFI_DEVICE_ERROR the device failed to send data.
2050
2051 **/
2052 EFI_STATUS
2053 EFIAPI
2054 AhciPacketCommandExecute (
2055 IN EFI_PCI_IO_PROTOCOL *PciIo,
2056 IN EFI_AHCI_REGISTERS *AhciRegisters,
2057 IN UINT8 Port,
2058 IN UINT8 PortMultiplier,
2059 IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet
2060 )
2061 {
2062 EFI_STATUS Status;
2063 VOID *Buffer;
2064 UINT32 Length;
2065 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2066 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
2067 BOOLEAN Read;
2068
2069 if (Packet == NULL || Packet->Cdb == NULL) {
2070 return EFI_INVALID_PARAMETER;
2071 }
2072
2073 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2074 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
2075 AtaCommandBlock.AtaCommand = ATA_CMD_PACKET;
2076 //
2077 // No OVL; No DMA
2078 //
2079 AtaCommandBlock.AtaFeatures = 0x00;
2080 //
2081 // set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device
2082 // determine how many data should be transferred.
2083 //
2084 AtaCommandBlock.AtaCylinderLow = (UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff);
2085 AtaCommandBlock.AtaCylinderHigh = (UINT8) (ATAPI_MAX_BYTE_COUNT >> 8);
2086
2087 if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) {
2088 Buffer = Packet->InDataBuffer;
2089 Length = Packet->InTransferLength;
2090 Read = TRUE;
2091 } else {
2092 Buffer = Packet->OutDataBuffer;
2093 Length = Packet->OutTransferLength;
2094 Read = FALSE;
2095 }
2096
2097 if (Length == 0) {
2098 Status = AhciNonDataTransfer (
2099 PciIo,
2100 AhciRegisters,
2101 Port,
2102 PortMultiplier,
2103 Packet->Cdb,
2104 Packet->CdbLength,
2105 &AtaCommandBlock,
2106 &AtaStatusBlock,
2107 Packet->Timeout,
2108 NULL
2109 );
2110 } else {
2111 Status = AhciPioTransfer (
2112 PciIo,
2113 AhciRegisters,
2114 Port,
2115 PortMultiplier,
2116 Packet->Cdb,
2117 Packet->CdbLength,
2118 Read,
2119 &AtaCommandBlock,
2120 &AtaStatusBlock,
2121 Buffer,
2122 Length,
2123 Packet->Timeout,
2124 NULL
2125 );
2126 }
2127 return Status;
2128 }
2129
2130 /**
2131 Allocate transfer-related data struct which is used at AHCI mode.
2132
2133 @param PciIo The PCI IO protocol instance.
2134 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2135
2136 **/
2137 EFI_STATUS
2138 EFIAPI
2139 AhciCreateTransferDescriptor (
2140 IN EFI_PCI_IO_PROTOCOL *PciIo,
2141 IN OUT EFI_AHCI_REGISTERS *AhciRegisters
2142 )
2143 {
2144 EFI_STATUS Status;
2145 UINTN Bytes;
2146 VOID *Buffer;
2147
2148 UINT32 Capability;
2149 UINT32 PortImplementBitMap;
2150 UINT8 MaxPortNumber;
2151 UINT8 MaxCommandSlotNumber;
2152 BOOLEAN Support64Bit;
2153 UINT64 MaxReceiveFisSize;
2154 UINT64 MaxCommandListSize;
2155 UINT64 MaxCommandTableSize;
2156 EFI_PHYSICAL_ADDRESS AhciRFisPciAddr;
2157 EFI_PHYSICAL_ADDRESS AhciCmdListPciAddr;
2158 EFI_PHYSICAL_ADDRESS AhciCommandTablePciAddr;
2159
2160 Buffer = NULL;
2161 //
2162 // Collect AHCI controller information
2163 //
2164 Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
2165 //
2166 // Get the number of command slots per port supported by this HBA.
2167 //
2168 MaxCommandSlotNumber = (UINT8) (((Capability & 0x1F00) >> 8) + 1);
2169 Support64Bit = (BOOLEAN) (((Capability & BIT31) != 0) ? TRUE : FALSE);
2170
2171 PortImplementBitMap = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);
2172 //
2173 // Get the highest bit of implemented ports which decides how many bytes are allocated for received FIS.
2174 //
2175 MaxPortNumber = (UINT8)(UINTN)(HighBitSet32(PortImplementBitMap) + 1);
2176 if (MaxPortNumber == 0) {
2177 return EFI_DEVICE_ERROR;
2178 }
2179
2180 MaxReceiveFisSize = MaxPortNumber * sizeof (EFI_AHCI_RECEIVED_FIS);
2181 Status = PciIo->AllocateBuffer (
2182 PciIo,
2183 AllocateAnyPages,
2184 EfiBootServicesData,
2185 EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),
2186 &Buffer,
2187 0
2188 );
2189
2190 if (EFI_ERROR (Status)) {
2191 return EFI_OUT_OF_RESOURCES;
2192 }
2193
2194 ZeroMem (Buffer, (UINTN)MaxReceiveFisSize);
2195
2196 AhciRegisters->AhciRFis = Buffer;
2197 AhciRegisters->MaxReceiveFisSize = MaxReceiveFisSize;
2198 Bytes = (UINTN)MaxReceiveFisSize;
2199
2200 Status = PciIo->Map (
2201 PciIo,
2202 EfiPciIoOperationBusMasterCommonBuffer,
2203 Buffer,
2204 &Bytes,
2205 &AhciRFisPciAddr,
2206 &AhciRegisters->MapRFis
2207 );
2208
2209 if (EFI_ERROR (Status) || (Bytes != MaxReceiveFisSize)) {
2210 //
2211 // Map error or unable to map the whole RFis buffer into a contiguous region.
2212 //
2213 Status = EFI_OUT_OF_RESOURCES;
2214 goto Error6;
2215 }
2216
2217 if ((!Support64Bit) && (AhciRFisPciAddr > 0x100000000ULL)) {
2218 //
2219 // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2220 //
2221 Status = EFI_DEVICE_ERROR;
2222 goto Error5;
2223 }
2224 AhciRegisters->AhciRFisPciAddr = (EFI_AHCI_RECEIVED_FIS *)(UINTN)AhciRFisPciAddr;
2225
2226 //
2227 // Allocate memory for command list
2228 // Note that the implementation is a single task model which only use a command list for all ports.
2229 //
2230 Buffer = NULL;
2231 MaxCommandListSize = MaxCommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST);
2232 Status = PciIo->AllocateBuffer (
2233 PciIo,
2234 AllocateAnyPages,
2235 EfiBootServicesData,
2236 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),
2237 &Buffer,
2238 0
2239 );
2240
2241 if (EFI_ERROR (Status)) {
2242 //
2243 // Free mapped resource.
2244 //
2245 Status = EFI_OUT_OF_RESOURCES;
2246 goto Error5;
2247 }
2248
2249 ZeroMem (Buffer, (UINTN)MaxCommandListSize);
2250
2251 AhciRegisters->AhciCmdList = Buffer;
2252 AhciRegisters->MaxCommandListSize = MaxCommandListSize;
2253 Bytes = (UINTN)MaxCommandListSize;
2254
2255 Status = PciIo->Map (
2256 PciIo,
2257 EfiPciIoOperationBusMasterCommonBuffer,
2258 Buffer,
2259 &Bytes,
2260 &AhciCmdListPciAddr,
2261 &AhciRegisters->MapCmdList
2262 );
2263
2264 if (EFI_ERROR (Status) || (Bytes != MaxCommandListSize)) {
2265 //
2266 // Map error or unable to map the whole cmd list buffer into a contiguous region.
2267 //
2268 Status = EFI_OUT_OF_RESOURCES;
2269 goto Error4;
2270 }
2271
2272 if ((!Support64Bit) && (AhciCmdListPciAddr > 0x100000000ULL)) {
2273 //
2274 // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2275 //
2276 Status = EFI_DEVICE_ERROR;
2277 goto Error3;
2278 }
2279 AhciRegisters->AhciCmdListPciAddr = (EFI_AHCI_COMMAND_LIST *)(UINTN)AhciCmdListPciAddr;
2280
2281 //
2282 // Allocate memory for command table
2283 // According to AHCI 1.3 spec, a PRD table can contain maximum 65535 entries.
2284 //
2285 Buffer = NULL;
2286 MaxCommandTableSize = sizeof (EFI_AHCI_COMMAND_TABLE);
2287
2288 Status = PciIo->AllocateBuffer (
2289 PciIo,
2290 AllocateAnyPages,
2291 EfiBootServicesData,
2292 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),
2293 &Buffer,
2294 0
2295 );
2296
2297 if (EFI_ERROR (Status)) {
2298 //
2299 // Free mapped resource.
2300 //
2301 Status = EFI_OUT_OF_RESOURCES;
2302 goto Error3;
2303 }
2304
2305 ZeroMem (Buffer, (UINTN)MaxCommandTableSize);
2306
2307 AhciRegisters->AhciCommandTable = Buffer;
2308 AhciRegisters->MaxCommandTableSize = MaxCommandTableSize;
2309 Bytes = (UINTN)MaxCommandTableSize;
2310
2311 Status = PciIo->Map (
2312 PciIo,
2313 EfiPciIoOperationBusMasterCommonBuffer,
2314 Buffer,
2315 &Bytes,
2316 &AhciCommandTablePciAddr,
2317 &AhciRegisters->MapCommandTable
2318 );
2319
2320 if (EFI_ERROR (Status) || (Bytes != MaxCommandTableSize)) {
2321 //
2322 // Map error or unable to map the whole cmd list buffer into a contiguous region.
2323 //
2324 Status = EFI_OUT_OF_RESOURCES;
2325 goto Error2;
2326 }
2327
2328 if ((!Support64Bit) && (AhciCommandTablePciAddr > 0x100000000ULL)) {
2329 //
2330 // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2331 //
2332 Status = EFI_DEVICE_ERROR;
2333 goto Error1;
2334 }
2335 AhciRegisters->AhciCommandTablePciAddr = (EFI_AHCI_COMMAND_TABLE *)(UINTN)AhciCommandTablePciAddr;
2336
2337 return EFI_SUCCESS;
2338 //
2339 // Map error or unable to map the whole CmdList buffer into a contiguous region.
2340 //
2341 Error1:
2342 PciIo->Unmap (
2343 PciIo,
2344 AhciRegisters->MapCommandTable
2345 );
2346 Error2:
2347 PciIo->FreeBuffer (
2348 PciIo,
2349 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),
2350 AhciRegisters->AhciCommandTable
2351 );
2352 Error3:
2353 PciIo->Unmap (
2354 PciIo,
2355 AhciRegisters->MapCmdList
2356 );
2357 Error4:
2358 PciIo->FreeBuffer (
2359 PciIo,
2360 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),
2361 AhciRegisters->AhciCmdList
2362 );
2363 Error5:
2364 PciIo->Unmap (
2365 PciIo,
2366 AhciRegisters->MapRFis
2367 );
2368 Error6:
2369 PciIo->FreeBuffer (
2370 PciIo,
2371 EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),
2372 AhciRegisters->AhciRFis
2373 );
2374
2375 return Status;
2376 }
2377
2378 /**
2379 Read logs from SATA device.
2380
2381 @param PciIo The PCI IO protocol instance.
2382 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2383 @param Port The number of port.
2384 @param PortMultiplier The multiplier of port.
2385 @param Buffer The data buffer to store SATA logs.
2386 @param LogNumber The address of the log.
2387 @param PageNumber The page number of the log.
2388
2389 @retval EFI_INVALID_PARAMETER PciIo, AhciRegisters or Buffer is NULL.
2390 @retval others Return status of AhciPioTransfer().
2391 **/
2392 EFI_STATUS
2393 AhciReadLogExt (
2394 IN EFI_PCI_IO_PROTOCOL *PciIo,
2395 IN EFI_AHCI_REGISTERS *AhciRegisters,
2396 IN UINT8 Port,
2397 IN UINT8 PortMultiplier,
2398 IN OUT UINT8 *Buffer,
2399 IN UINT8 LogNumber,
2400 IN UINT8 PageNumber
2401 )
2402 {
2403 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2404 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
2405
2406 if (PciIo == NULL || AhciRegisters == NULL || Buffer == NULL) {
2407 return EFI_INVALID_PARAMETER;
2408 }
2409
2410 ///
2411 /// Read log from device
2412 ///
2413 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2414 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
2415 ZeroMem (Buffer, 512);
2416
2417 AtaCommandBlock.AtaCommand = ATA_CMD_READ_LOG_EXT;
2418 AtaCommandBlock.AtaSectorCount = 1;
2419 AtaCommandBlock.AtaSectorNumber = LogNumber;
2420 AtaCommandBlock.AtaCylinderLow = PageNumber;
2421
2422 return AhciPioTransfer (
2423 PciIo,
2424 AhciRegisters,
2425 Port,
2426 PortMultiplier,
2427 NULL,
2428 0,
2429 TRUE,
2430 &AtaCommandBlock,
2431 &AtaStatusBlock,
2432 Buffer,
2433 512,
2434 ATA_ATAPI_TIMEOUT,
2435 NULL
2436 );
2437 }
2438
2439 /**
2440 Enable DEVSLP of the disk if supported.
2441
2442 @param PciIo The PCI IO protocol instance.
2443 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2444 @param Port The number of port.
2445 @param PortMultiplier The multiplier of port.
2446 @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
2447
2448 @retval EFI_SUCCESS The DEVSLP is enabled per policy successfully.
2449 @retval EFI_UNSUPPORTED The DEVSLP isn't supported by the controller/device and policy requires to enable it.
2450 **/
2451 EFI_STATUS
2452 AhciEnableDevSlp (
2453 IN EFI_PCI_IO_PROTOCOL *PciIo,
2454 IN EFI_AHCI_REGISTERS *AhciRegisters,
2455 IN UINT8 Port,
2456 IN UINT8 PortMultiplier,
2457 IN EFI_IDENTIFY_DATA *IdentifyData
2458 )
2459 {
2460 EFI_STATUS Status;
2461 UINT32 Offset;
2462 UINT32 Capability2;
2463 UINT8 LogData[512];
2464 DEVSLP_TIMING_VARIABLES DevSlpTiming;
2465 UINT32 PortCmd;
2466 UINT32 PortDevSlp;
2467
2468 if (mAtaAtapiPolicy->DeviceSleepEnable != 1) {
2469 return EFI_SUCCESS;
2470 }
2471
2472 //
2473 // Do not enable DevSlp if DevSlp is not supported.
2474 //
2475 Capability2 = AhciReadReg (PciIo, AHCI_CAPABILITY2_OFFSET);
2476 DEBUG ((DEBUG_INFO, "AHCI CAPABILITY2 = %08x\n", Capability2));
2477 if ((Capability2 & AHCI_CAP2_SDS) == 0) {
2478 return EFI_UNSUPPORTED;
2479 }
2480
2481 //
2482 // Do not enable DevSlp if DevSlp is not present
2483 // Do not enable DevSlp if Hot Plug or Mechanical Presence Switch is supported
2484 //
2485 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH;
2486 PortCmd = AhciReadReg (PciIo, Offset + EFI_AHCI_PORT_CMD);
2487 PortDevSlp = AhciReadReg (PciIo, Offset + AHCI_PORT_DEVSLP);
2488 DEBUG ((DEBUG_INFO, "Port CMD/DEVSLP = %08x / %08x\n", PortCmd, PortDevSlp));
2489 if (((PortDevSlp & AHCI_PORT_DEVSLP_DSP) == 0) ||
2490 ((PortCmd & (EFI_AHCI_PORT_CMD_HPCP | EFI_AHCI_PORT_CMD_MPSP)) != 0)
2491 ) {
2492 return EFI_UNSUPPORTED;
2493 }
2494
2495 //
2496 // Do not enable DevSlp if the device doesn't support DevSlp
2497 //
2498 DEBUG ((DEBUG_INFO, "IDENTIFY DEVICE: [77] = %04x, [78] = %04x, [79] = %04x\n",
2499 IdentifyData->AtaData.reserved_77,
2500 IdentifyData->AtaData.serial_ata_features_supported, IdentifyData->AtaData.serial_ata_features_enabled));
2501 if ((IdentifyData->AtaData.serial_ata_features_supported & BIT8) == 0) {
2502 DEBUG ((DEBUG_INFO, "DevSlp feature is not supported for device at port [%d] PortMultiplier [%d]!\n",
2503 Port, PortMultiplier));
2504 return EFI_UNSUPPORTED;
2505 }
2506
2507 //
2508 // Enable DevSlp when it is not enabled.
2509 //
2510 if ((IdentifyData->AtaData.serial_ata_features_enabled & BIT8) != 0) {
2511 Status = AhciDeviceSetFeature (
2512 PciIo, AhciRegisters, Port, 0, ATA_SUB_CMD_ENABLE_SATA_FEATURE, 0x09, ATA_ATAPI_TIMEOUT
2513 );
2514 DEBUG ((DEBUG_INFO, "DevSlp set feature for device at port [%d] PortMultiplier [%d] - %r\n",
2515 Port, PortMultiplier, Status));
2516 if (EFI_ERROR (Status)) {
2517 return Status;
2518 }
2519 }
2520
2521 Status = AhciReadLogExt(PciIo, AhciRegisters, Port, PortMultiplier, LogData, 0x30, 0x08);
2522
2523 //
2524 // Clear PxCMD.ST and PxDEVSLP.ADSE before updating PxDEVSLP.DITO and PxDEVSLP.MDAT.
2525 //
2526 AhciWriteReg (PciIo, Offset + EFI_AHCI_PORT_CMD, PortCmd & ~EFI_AHCI_PORT_CMD_ST);
2527 PortDevSlp &= ~AHCI_PORT_DEVSLP_ADSE;
2528 AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
2529
2530 //
2531 // Set PxDEVSLP.DETO and PxDEVSLP.MDAT to 0.
2532 //
2533 PortDevSlp &= ~AHCI_PORT_DEVSLP_DETO_MASK;
2534 PortDevSlp &= ~AHCI_PORT_DEVSLP_MDAT_MASK;
2535 AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
2536 DEBUG ((DEBUG_INFO, "Read Log Ext at port [%d] PortMultiplier [%d] - %r\n", Port, PortMultiplier, Status));
2537 if (EFI_ERROR (Status)) {
2538 //
2539 // Assume DEVSLP TIMING VARIABLES is not supported if the Identify Device Data log (30h, 8) fails
2540 //
2541 ZeroMem (&DevSlpTiming, sizeof (DevSlpTiming));
2542 } else {
2543 CopyMem (&DevSlpTiming, &LogData[48], sizeof (DevSlpTiming));
2544 DEBUG ((DEBUG_INFO, "DevSlpTiming: Supported(%d), Deto(%d), Madt(%d)\n",
2545 DevSlpTiming.Supported, DevSlpTiming.Deto, DevSlpTiming.Madt));
2546 }
2547
2548 //
2549 // Use 20ms as default DETO when DEVSLP TIMING VARIABLES is not supported or the DETO is 0.
2550 //
2551 if ((DevSlpTiming.Supported == 0) || (DevSlpTiming.Deto == 0)) {
2552 DevSlpTiming.Deto = 20;
2553 }
2554
2555 //
2556 // Use 10ms as default MADT when DEVSLP TIMING VARIABLES is not supported or the MADT is 0.
2557 //
2558 if ((DevSlpTiming.Supported == 0) || (DevSlpTiming.Madt == 0)) {
2559 DevSlpTiming.Madt = 10;
2560 }
2561
2562 PortDevSlp |= DevSlpTiming.Deto << 2;
2563 PortDevSlp |= DevSlpTiming.Madt << 10;
2564 AhciOrReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
2565
2566 if (mAtaAtapiPolicy->AggressiveDeviceSleepEnable == 1) {
2567 if ((Capability2 & AHCI_CAP2_SADM) != 0) {
2568 PortDevSlp &= ~AHCI_PORT_DEVSLP_DITO_MASK;
2569 PortDevSlp |= (625 << 15);
2570 AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
2571
2572 PortDevSlp |= AHCI_PORT_DEVSLP_ADSE;
2573 AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
2574 }
2575 }
2576
2577
2578 AhciWriteReg (PciIo, Offset + EFI_AHCI_PORT_CMD, PortCmd);
2579
2580 DEBUG ((DEBUG_INFO, "Enabled DevSlp feature at port [%d] PortMultiplier [%d], Port CMD/DEVSLP = %08x / %08x\n",
2581 Port, PortMultiplier, PortCmd, PortDevSlp));
2582
2583 return EFI_SUCCESS;
2584 }
2585
2586 /**
2587 Spin-up disk if IDD was incomplete or PUIS feature is enabled
2588
2589 @param PciIo The PCI IO protocol instance.
2590 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2591 @param Port The number of port.
2592 @param PortMultiplier The multiplier of port.
2593 @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
2594
2595 **/
2596 EFI_STATUS
2597 AhciSpinUpDisk (
2598 IN EFI_PCI_IO_PROTOCOL *PciIo,
2599 IN EFI_AHCI_REGISTERS *AhciRegisters,
2600 IN UINT8 Port,
2601 IN UINT8 PortMultiplier,
2602 IN OUT EFI_IDENTIFY_DATA *IdentifyData
2603 )
2604 {
2605 EFI_STATUS Status;
2606 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2607 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
2608 UINT8 Buffer[512];
2609
2610 if (IdentifyData->AtaData.specific_config == ATA_SPINUP_CFG_REQUIRED_IDD_INCOMPLETE) {
2611 //
2612 // Use SET_FEATURE subcommand to spin up the device.
2613 //
2614 Status = AhciDeviceSetFeature (
2615 PciIo, AhciRegisters, Port, PortMultiplier,
2616 ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP, 0x00, ATA_SPINUP_TIMEOUT
2617 );
2618 DEBUG ((DEBUG_INFO, "CMD_PUIS_SET_DEVICE_SPINUP for device at port [%d] PortMultiplier [%d] - %r!\n",
2619 Port, PortMultiplier, Status));
2620 if (EFI_ERROR (Status)) {
2621 return Status;
2622 }
2623 } else {
2624 ASSERT (IdentifyData->AtaData.specific_config == ATA_SPINUP_CFG_NOT_REQUIRED_IDD_INCOMPLETE);
2625
2626 //
2627 // Use READ_SECTORS to spin up the device if SpinUp SET FEATURE subcommand is not supported
2628 //
2629 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2630 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
2631 //
2632 // Perform READ SECTORS PIO Data-In command to Read LBA 0
2633 //
2634 AtaCommandBlock.AtaCommand = ATA_CMD_READ_SECTORS;
2635 AtaCommandBlock.AtaSectorCount = 0x1;
2636
2637 Status = AhciPioTransfer (
2638 PciIo,
2639 AhciRegisters,
2640 Port,
2641 PortMultiplier,
2642 NULL,
2643 0,
2644 TRUE,
2645 &AtaCommandBlock,
2646 &AtaStatusBlock,
2647 &Buffer,
2648 sizeof (Buffer),
2649 ATA_SPINUP_TIMEOUT,
2650 NULL
2651 );
2652 DEBUG ((DEBUG_INFO, "Read LBA 0 for device at port [%d] PortMultiplier [%d] - %r!\n",
2653 Port, PortMultiplier, Status));
2654 if (EFI_ERROR (Status)) {
2655 return Status;
2656 }
2657 }
2658
2659 //
2660 // Read the complete IDENTIFY DEVICE data.
2661 //
2662 ZeroMem (IdentifyData, sizeof (*IdentifyData));
2663 Status = AhciIdentify (PciIo, AhciRegisters, Port, PortMultiplier, IdentifyData);
2664 if (EFI_ERROR (Status)) {
2665 DEBUG ((DEBUG_ERROR, "Read IDD failed for device at port [%d] PortMultiplier [%d] - %r!\n",
2666 Port, PortMultiplier, Status));
2667 return Status;
2668 }
2669
2670 DEBUG ((DEBUG_INFO, "IDENTIFY DEVICE: [0] = %016x, [2] = %016x, [83] = %016x, [86] = %016x\n",
2671 IdentifyData->AtaData.config, IdentifyData->AtaData.specific_config,
2672 IdentifyData->AtaData.command_set_supported_83, IdentifyData->AtaData.command_set_feature_enb_86));
2673 //
2674 // Check if IDD is incomplete
2675 //
2676 if ((IdentifyData->AtaData.config & BIT2) != 0) {
2677 return EFI_DEVICE_ERROR;
2678 }
2679
2680 return EFI_SUCCESS;
2681 }
2682
2683 /**
2684 Enable/disable/skip PUIS of the disk according to policy.
2685
2686 @param PciIo The PCI IO protocol instance.
2687 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2688 @param Port The number of port.
2689 @param PortMultiplier The multiplier of port.
2690
2691 **/
2692 EFI_STATUS
2693 AhciPuisEnable (
2694 IN EFI_PCI_IO_PROTOCOL *PciIo,
2695 IN EFI_AHCI_REGISTERS *AhciRegisters,
2696 IN UINT8 Port,
2697 IN UINT8 PortMultiplier
2698 )
2699 {
2700 EFI_STATUS Status;
2701
2702 Status = EFI_SUCCESS;
2703 if (mAtaAtapiPolicy->PuisEnable == 0) {
2704 Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, PortMultiplier, ATA_SUB_CMD_DISABLE_PUIS, 0x00, ATA_ATAPI_TIMEOUT);
2705 } else if (mAtaAtapiPolicy->PuisEnable == 1) {
2706 Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, PortMultiplier, ATA_SUB_CMD_ENABLE_PUIS, 0x00, ATA_ATAPI_TIMEOUT);
2707 }
2708 DEBUG ((DEBUG_INFO, "%a PUIS feature at port [%d] PortMultiplier [%d] - %r!\n",
2709 (mAtaAtapiPolicy->PuisEnable == 0) ? "Disable" : (
2710 (mAtaAtapiPolicy->PuisEnable == 1) ? "Enable" : "Skip"
2711 ), Port, PortMultiplier, Status));
2712 return Status;
2713 }
2714
2715 /**
2716 Initialize ATA host controller at AHCI mode.
2717
2718 The function is designed to initialize ATA host controller.
2719
2720 @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
2721
2722 **/
2723 EFI_STATUS
2724 EFIAPI
2725 AhciModeInitialization (
2726 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance
2727 )
2728 {
2729 EFI_STATUS Status;
2730 EFI_PCI_IO_PROTOCOL *PciIo;
2731 EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
2732 UINT32 Capability;
2733 UINT8 MaxPortNumber;
2734 UINT32 PortImplementBitMap;
2735
2736 EFI_AHCI_REGISTERS *AhciRegisters;
2737
2738 UINT8 Port;
2739 DATA_64 Data64;
2740 UINT32 Offset;
2741 UINT32 Data;
2742 EFI_IDENTIFY_DATA Buffer;
2743 EFI_ATA_DEVICE_TYPE DeviceType;
2744 EFI_ATA_COLLECTIVE_MODE *SupportedModes;
2745 EFI_ATA_TRANSFER_MODE TransferMode;
2746 UINT32 PhyDetectDelay;
2747 UINT32 Value;
2748
2749 if (Instance == NULL) {
2750 return EFI_INVALID_PARAMETER;
2751 }
2752
2753 PciIo = Instance->PciIo;
2754 IdeInit = Instance->IdeControllerInit;
2755
2756 Status = AhciReset (PciIo, EFI_AHCI_BUS_RESET_TIMEOUT);
2757
2758 if (EFI_ERROR (Status)) {
2759 return EFI_DEVICE_ERROR;
2760 }
2761
2762 //
2763 // Collect AHCI controller information
2764 //
2765 Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET);
2766
2767 //
2768 // Make sure that GHC.AE bit is set before accessing any AHCI registers.
2769 //
2770 Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
2771
2772 if ((Value & EFI_AHCI_GHC_ENABLE) == 0) {
2773 AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
2774 }
2775
2776 //
2777 // Enable 64-bit DMA support in the PCI layer if this controller
2778 // supports it.
2779 //
2780 if ((Capability & EFI_AHCI_CAP_S64A) != 0) {
2781 Status = PciIo->Attributes (
2782 PciIo,
2783 EfiPciIoAttributeOperationEnable,
2784 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,
2785 NULL
2786 );
2787 if (EFI_ERROR (Status)) {
2788 DEBUG ((EFI_D_WARN,
2789 "AhciModeInitialization: failed to enable 64-bit DMA on 64-bit capable controller (%r)\n",
2790 Status));
2791 }
2792 }
2793
2794 //
2795 // Get the number of command slots per port supported by this HBA.
2796 //
2797 MaxPortNumber = (UINT8) ((Capability & 0x1F) + 1);
2798
2799 //
2800 // Get the bit map of those ports exposed by this HBA.
2801 // It indicates which ports that the HBA supports are available for software to use.
2802 //
2803 PortImplementBitMap = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);
2804
2805 AhciRegisters = &Instance->AhciRegisters;
2806 Status = AhciCreateTransferDescriptor (PciIo, AhciRegisters);
2807
2808 if (EFI_ERROR (Status)) {
2809 return EFI_OUT_OF_RESOURCES;
2810 }
2811
2812 for (Port = 0; Port < EFI_AHCI_MAX_PORTS; Port ++) {
2813 if ((PortImplementBitMap & (((UINT32)BIT0) << Port)) != 0) {
2814 //
2815 // According to AHCI spec, MaxPortNumber should be equal or greater than the number of implemented ports.
2816 //
2817 if ((MaxPortNumber--) == 0) {
2818 //
2819 // Should never be here.
2820 //
2821 ASSERT (FALSE);
2822 return EFI_SUCCESS;
2823 }
2824
2825 IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelEnumeration, Port);
2826
2827 //
2828 // Initialize FIS Base Address Register and Command List Base Address Register for use.
2829 //
2830 Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFisPciAddr) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
2831 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FB;
2832 AhciWriteReg (PciIo, Offset, Data64.Uint32.Lower32);
2833 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FBU;
2834 AhciWriteReg (PciIo, Offset, Data64.Uint32.Upper32);
2835
2836 Data64.Uint64 = (UINTN) (AhciRegisters->AhciCmdListPciAddr);
2837 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLB;
2838 AhciWriteReg (PciIo, Offset, Data64.Uint32.Lower32);
2839 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLBU;
2840 AhciWriteReg (PciIo, Offset, Data64.Uint32.Upper32);
2841
2842 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
2843 Data = AhciReadReg (PciIo, Offset);
2844 if ((Data & EFI_AHCI_PORT_CMD_CPD) != 0) {
2845 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_POD);
2846 }
2847
2848 if ((Capability & EFI_AHCI_CAP_SSS) != 0) {
2849 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_SUD);
2850 }
2851
2852 //
2853 // Disable aggressive power management.
2854 //
2855 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;
2856 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_SCTL_IPM_INIT);
2857 //
2858 // Disable the reporting of the corresponding interrupt to system software.
2859 //
2860 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IE;
2861 AhciAndReg (PciIo, Offset, 0);
2862
2863 //
2864 // Now inform the IDE Controller Init Module.
2865 //
2866 IdeInit->NotifyPhase (IdeInit, EfiIdeBusBeforeDevicePresenceDetection, Port);
2867
2868 //
2869 // Enable FIS Receive DMA engine for the first D2H FIS.
2870 //
2871 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
2872 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);
2873
2874 //
2875 // Wait for the Phy to detect the presence of a device.
2876 //
2877 PhyDetectDelay = EFI_AHCI_BUS_PHY_DETECT_TIMEOUT;
2878 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
2879 do {
2880 Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_SSTS_DET_MASK;
2881 if ((Data == EFI_AHCI_PORT_SSTS_DET_PCE) || (Data == EFI_AHCI_PORT_SSTS_DET)) {
2882 break;
2883 }
2884
2885 MicroSecondDelay (1000);
2886 PhyDetectDelay--;
2887 } while (PhyDetectDelay > 0);
2888
2889 if (PhyDetectDelay == 0) {
2890 //
2891 // No device detected at this port.
2892 // Clear PxCMD.SUD for those ports at which there are no device present.
2893 //
2894 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
2895 AhciAndReg (PciIo, Offset, (UINT32) ~(EFI_AHCI_PORT_CMD_SUD));
2896 continue;
2897 }
2898
2899 Status = AhciWaitDeviceReady (PciIo, Port);
2900 if (EFI_ERROR (Status)) {
2901 continue;
2902 }
2903
2904 //
2905 // When the first D2H register FIS is received, the content of PxSIG register is updated.
2906 //
2907 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SIG;
2908 Status = AhciWaitMmioSet (
2909 PciIo,
2910 Offset,
2911 0x0000FFFF,
2912 0x00000101,
2913 EFI_TIMER_PERIOD_SECONDS(16)
2914 );
2915 if (EFI_ERROR (Status)) {
2916 continue;
2917 }
2918
2919 Data = AhciReadReg (PciIo, Offset);
2920 if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATAPI_DEVICE_SIG) {
2921 Status = AhciIdentifyPacket (PciIo, AhciRegisters, Port, 0, &Buffer);
2922
2923 if (EFI_ERROR (Status)) {
2924 continue;
2925 }
2926
2927 DeviceType = EfiIdeCdrom;
2928 } else if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATA_DEVICE_SIG) {
2929 Status = AhciIdentify (PciIo, AhciRegisters, Port, 0, &Buffer);
2930
2931 if (EFI_ERROR (Status)) {
2932 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED));
2933 continue;
2934 }
2935
2936 DEBUG ((
2937 DEBUG_INFO, "IDENTIFY DEVICE: [0] = %016x, [2] = %016x, [83] = %016x, [86] = %016x\n",
2938 Buffer.AtaData.config, Buffer.AtaData.specific_config,
2939 Buffer.AtaData.command_set_supported_83, Buffer.AtaData.command_set_feature_enb_86
2940 ));
2941 if ((Buffer.AtaData.config & BIT2) != 0) {
2942 //
2943 // SpinUp disk if device reported incomplete IDENTIFY DEVICE.
2944 //
2945 Status = AhciSpinUpDisk (
2946 PciIo,
2947 AhciRegisters,
2948 Port,
2949 0,
2950 &Buffer
2951 );
2952 if (EFI_ERROR (Status)) {
2953 DEBUG ((DEBUG_ERROR, "Spin up standby device failed - %r\n", Status));
2954 continue;
2955 }
2956 }
2957
2958 DeviceType = EfiIdeHarddisk;
2959 } else {
2960 continue;
2961 }
2962 DEBUG ((DEBUG_INFO, "port [%d] port multitplier [%d] has a [%a]\n",
2963 Port, 0, DeviceType == EfiIdeCdrom ? "cdrom" : "harddisk"));
2964
2965 //
2966 // If the device is a hard disk, then try to enable S.M.A.R.T feature
2967 //
2968 if ((DeviceType == EfiIdeHarddisk) && PcdGetBool (PcdAtaSmartEnable)) {
2969 AhciAtaSmartSupport (
2970 PciIo,
2971 AhciRegisters,
2972 Port,
2973 0,
2974 &Buffer,
2975 NULL
2976 );
2977 }
2978
2979 //
2980 // Submit identify data to IDE controller init driver
2981 //
2982 IdeInit->SubmitData (IdeInit, Port, 0, &Buffer);
2983
2984 //
2985 // Now start to config ide device parameter and transfer mode.
2986 //
2987 Status = IdeInit->CalculateMode (
2988 IdeInit,
2989 Port,
2990 0,
2991 &SupportedModes
2992 );
2993 if (EFI_ERROR (Status)) {
2994 DEBUG ((EFI_D_ERROR, "Calculate Mode Fail, Status = %r\n", Status));
2995 continue;
2996 }
2997
2998 //
2999 // Set best supported PIO mode on this IDE device
3000 //
3001 if (SupportedModes->PioMode.Mode <= EfiAtaPioMode2) {
3002 TransferMode.ModeCategory = EFI_ATA_MODE_DEFAULT_PIO;
3003 } else {
3004 TransferMode.ModeCategory = EFI_ATA_MODE_FLOW_PIO;
3005 }
3006
3007 TransferMode.ModeNumber = (UINT8) (SupportedModes->PioMode.Mode);
3008
3009 //
3010 // Set supported DMA mode on this IDE device. Note that UDMA & MDMA can't
3011 // be set together. Only one DMA mode can be set to a device. If setting
3012 // DMA mode operation fails, we can continue moving on because we only use
3013 // PIO mode at boot time. DMA modes are used by certain kind of OS booting
3014 //
3015 if (SupportedModes->UdmaMode.Valid) {
3016 TransferMode.ModeCategory = EFI_ATA_MODE_UDMA;
3017 TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);
3018 } else if (SupportedModes->MultiWordDmaMode.Valid) {
3019 TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;
3020 TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;
3021 }
3022
3023 Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, 0, 0x03, (UINT32)(*(UINT8 *)&TransferMode), ATA_ATAPI_TIMEOUT);
3024 if (EFI_ERROR (Status)) {
3025 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
3026 continue;
3027 }
3028
3029 //
3030 // Found a ATA or ATAPI device, add it into the device list.
3031 //
3032 CreateNewDeviceInfo (Instance, Port, 0xFFFF, DeviceType, &Buffer);
3033 if (DeviceType == EfiIdeHarddisk) {
3034 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));
3035 AhciEnableDevSlp (
3036 PciIo,
3037 AhciRegisters,
3038 Port,
3039 0,
3040 &Buffer
3041 );
3042 }
3043
3044 //
3045 // Enable/disable PUIS according to policy setting if PUIS is capable (Word[83].BIT5 is set).
3046 //
3047 if ((Buffer.AtaData.command_set_supported_83 & BIT5) != 0) {
3048 Status = AhciPuisEnable (
3049 PciIo,
3050 AhciRegisters,
3051 Port,
3052 0
3053 );
3054 if (EFI_ERROR (Status)) {
3055 DEBUG ((DEBUG_ERROR, "PUIS enable/disable failed, Status = %r\n", Status));
3056 continue;
3057 }
3058 }
3059 }
3060 }
3061
3062 return EFI_SUCCESS;
3063 }
3064
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