2 The file for AHCI mode of ATA host controller.
4 Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include "AtaAtapiPassThru.h"
19 Read AHCI Operation register.
21 @param PciIo The PCI IO protocol instance.
22 @param Offset The operation register offset.
24 @return The register content read.
30 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
36 ASSERT (PciIo
!= NULL
);
53 Write AHCI Operation register.
55 @param PciIo The PCI IO protocol instance.
56 @param Offset The operation register offset.
57 @param Data The data used to write down.
63 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
68 ASSERT (PciIo
!= NULL
);
83 Do AND operation with the value of AHCI Operation register.
85 @param PciIo The PCI IO protocol instance.
86 @param Offset The operation register offset.
87 @param AndData The data used to do AND operation.
93 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
100 ASSERT (PciIo
!= NULL
);
102 Data
= AhciReadReg (PciIo
, Offset
);
106 AhciWriteReg (PciIo
, Offset
, Data
);
110 Do OR operation with the value of AHCI Operation register.
112 @param PciIo The PCI IO protocol instance.
113 @param Offset The operation register offset.
114 @param OrData The data used to do OR operation.
120 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
127 ASSERT (PciIo
!= NULL
);
129 Data
= AhciReadReg (PciIo
, Offset
);
133 AhciWriteReg (PciIo
, Offset
, Data
);
137 Wait for the value of the specified MMIO register set to the test value.
139 @param PciIo The PCI IO protocol instance.
140 @param Offset The MMIO address to test.
141 @param MaskValue The mask value of memory.
142 @param TestValue The test value of memory.
143 @param Timeout The time out value for wait memory set, uses 100ns as a unit.
145 @retval EFI_TIMEOUT The MMIO setting is time out.
146 @retval EFI_SUCCESS The MMIO is correct set.
152 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
161 BOOLEAN InfiniteWait
;
166 InfiniteWait
= FALSE
;
169 Delay
= DivU64x32 (Timeout
, 1000) + 1;
173 // Access PCI MMIO space to see if the value is the tested one.
175 Value
= AhciReadReg (PciIo
, (UINT32
) Offset
) & MaskValue
;
177 if (Value
== TestValue
) {
182 // Stall for 100 microseconds.
184 MicroSecondDelay (100);
188 } while (InfiniteWait
|| (Delay
> 0));
194 Wait for the value of the specified system memory set to the test value.
196 @param Address The system memory address to test.
197 @param MaskValue The mask value of memory.
198 @param TestValue The test value of memory.
199 @param Timeout The time out value for wait memory set, uses 100ns as a unit.
201 @retval EFI_TIMEOUT The system memory setting is time out.
202 @retval EFI_SUCCESS The system memory is correct set.
208 IN EFI_PHYSICAL_ADDRESS Address
,
216 BOOLEAN InfiniteWait
;
221 InfiniteWait
= FALSE
;
224 Delay
= DivU64x32 (Timeout
, 1000) + 1;
228 // Access sytem memory to see if the value is the tested one.
230 // The system memory pointed by Address will be updated by the
231 // SATA Host Controller, "volatile" is introduced to prevent
232 // compiler from optimizing the access to the memory address
233 // to only read once.
235 Value
= *(volatile UINT32
*) (UINTN
) Address
;
238 if (Value
== TestValue
) {
243 // Stall for 100 microseconds.
245 MicroSecondDelay (100);
249 } while (InfiniteWait
|| (Delay
> 0));
255 Check the memory status to the test value.
257 @param[in] Address The memory address to test.
258 @param[in] MaskValue The mask value of memory.
259 @param[in] TestValue The test value of memory.
260 @param[in, out] Task Optional. Pointer to the ATA_NONBLOCK_TASK used by
261 non-blocking mode. If NULL, then just try once.
263 @retval EFI_NOTREADY The memory is not set.
264 @retval EFI_TIMEOUT The memory setting retry times out.
265 @retval EFI_SUCCESS The memory is correct set.
274 IN OUT ATA_NONBLOCK_TASK
*Task
283 Value
= *(volatile UINT32
*) Address
;
286 if (Value
== TestValue
) {
290 if ((Task
!= NULL
) && !Task
->InfiniteWait
&& (Task
->RetryTimes
== 0)) {
293 return EFI_NOT_READY
;
298 Check if the device is still on port. It also checks if the AHCI controller
299 supports the address and data count will be transferred.
301 @param PciIo The PCI IO protocol instance.
302 @param Port The number of port.
304 @retval EFI_SUCCESS The device is attached to port and the transfer data is
305 supported by AHCI controller.
306 @retval EFI_UNSUPPORTED The transfer address and count is not supported by AHCI
308 @retval EFI_NOT_READY The physical communication between AHCI controller and device
314 AhciCheckDeviceStatus (
315 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
322 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_SSTS
;
324 Data
= AhciReadReg (PciIo
, Offset
) & EFI_AHCI_PORT_SSTS_DET_MASK
;
326 if (Data
== EFI_AHCI_PORT_SSTS_DET_PCE
) {
330 return EFI_NOT_READY
;
335 Clear the port interrupt and error status. It will also clear
336 HBA interrupt status.
338 @param PciIo The PCI IO protocol instance.
339 @param Port The number of port.
344 AhciClearPortStatus (
345 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
352 // Clear any error status
354 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_SERR
;
355 AhciWriteReg (PciIo
, Offset
, AhciReadReg (PciIo
, Offset
));
358 // Clear any port interrupt status
360 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_IS
;
361 AhciWriteReg (PciIo
, Offset
, AhciReadReg (PciIo
, Offset
));
364 // Clear any HBA interrupt status
366 AhciWriteReg (PciIo
, EFI_AHCI_IS_OFFSET
, AhciReadReg (PciIo
, EFI_AHCI_IS_OFFSET
));
370 This function is used to dump the Status Registers and if there is ERR bit set
371 in the Status Register, the Error Register's value is also be dumped.
373 @param PciIo The PCI IO protocol instance.
374 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
375 @param Port The number of port.
376 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
382 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
383 IN EFI_AHCI_REGISTERS
*AhciRegisters
,
385 IN OUT EFI_ATA_STATUS_BLOCK
*AtaStatusBlock
393 ASSERT (PciIo
!= NULL
);
395 if (AtaStatusBlock
!= NULL
) {
396 ZeroMem (AtaStatusBlock
, sizeof (EFI_ATA_STATUS_BLOCK
));
398 FisBaseAddr
= (UINTN
)AhciRegisters
->AhciRFis
+ Port
* sizeof (EFI_AHCI_RECEIVED_FIS
);
399 Offset
= FisBaseAddr
+ EFI_AHCI_D2H_FIS_OFFSET
;
401 Status
= AhciCheckMemSet (Offset
, EFI_AHCI_FIS_TYPE_MASK
, EFI_AHCI_FIS_REGISTER_D2H
, NULL
);
402 if (!EFI_ERROR (Status
)) {
404 // If D2H FIS is received, update StatusBlock with its content.
406 CopyMem (AtaStatusBlock
, (UINT8
*)Offset
, sizeof (EFI_ATA_STATUS_BLOCK
));
409 // If D2H FIS is not received, only update Status & Error field through PxTFD
410 // as there is no other way to get the content of the Shadow Register Block.
412 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_TFD
;
413 Data
= AhciReadReg (PciIo
, (UINT32
)Offset
);
415 AtaStatusBlock
->AtaStatus
= (UINT8
)Data
;
416 if ((AtaStatusBlock
->AtaStatus
& BIT0
) != 0) {
417 AtaStatusBlock
->AtaError
= (UINT8
)(Data
>> 8);
425 Enable the FIS running for giving port.
427 @param PciIo The PCI IO protocol instance.
428 @param Port The number of port.
429 @param Timeout The timeout value of enabling FIS, uses 100ns as a unit.
431 @retval EFI_DEVICE_ERROR The FIS enable setting fails.
432 @retval EFI_TIMEOUT The FIS enable setting is time out.
433 @retval EFI_SUCCESS The FIS enable successfully.
438 AhciEnableFisReceive (
439 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
446 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_CMD
;
447 AhciOrReg (PciIo
, Offset
, EFI_AHCI_PORT_CMD_FRE
);
453 Disable the FIS running for giving port.
455 @param PciIo The PCI IO protocol instance.
456 @param Port The number of port.
457 @param Timeout The timeout value of disabling FIS, uses 100ns as a unit.
459 @retval EFI_DEVICE_ERROR The FIS disable setting fails.
460 @retval EFI_TIMEOUT The FIS disable setting is time out.
461 @retval EFI_UNSUPPORTED The port is in running state.
462 @retval EFI_SUCCESS The FIS disable successfully.
467 AhciDisableFisReceive (
468 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
476 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_CMD
;
477 Data
= AhciReadReg (PciIo
, Offset
);
480 // Before disabling Fis receive, the DMA engine of the port should NOT be in running status.
482 if ((Data
& (EFI_AHCI_PORT_CMD_ST
| EFI_AHCI_PORT_CMD_CR
)) != 0) {
483 return EFI_UNSUPPORTED
;
487 // Check if the Fis receive DMA engine for the port is running.
489 if ((Data
& EFI_AHCI_PORT_CMD_FR
) != EFI_AHCI_PORT_CMD_FR
) {
493 AhciAndReg (PciIo
, Offset
, (UINT32
)~(EFI_AHCI_PORT_CMD_FRE
));
495 return AhciWaitMmioSet (
498 EFI_AHCI_PORT_CMD_FR
,
507 Build the command list, command table and prepare the fis receiver.
509 @param PciIo The PCI IO protocol instance.
510 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
511 @param Port The number of port.
512 @param PortMultiplier The timeout value of stop.
513 @param CommandFis The control fis will be used for the transfer.
514 @param CommandList The command list will be used for the transfer.
515 @param AtapiCommand The atapi command will be used for the transfer.
516 @param AtapiCommandLength The length of the atapi command.
517 @param CommandSlotNumber The command slot will be used for the transfer.
518 @param DataPhysicalAddr The pointer to the data buffer pci bus master address.
519 @param DataLength The data count to be transferred.
525 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
526 IN EFI_AHCI_REGISTERS
*AhciRegisters
,
528 IN UINT8 PortMultiplier
,
529 IN EFI_AHCI_COMMAND_FIS
*CommandFis
,
530 IN EFI_AHCI_COMMAND_LIST
*CommandList
,
531 IN EFI_AHCI_ATAPI_COMMAND
*AtapiCommand OPTIONAL
,
532 IN UINT8 AtapiCommandLength
,
533 IN UINT8 CommandSlotNumber
,
534 IN OUT VOID
*DataPhysicalAddr
,
549 PrdtNumber
= (UINT32
)DivU64x32 (((UINT64
)DataLength
+ EFI_AHCI_MAX_DATA_PER_PRDT
- 1), EFI_AHCI_MAX_DATA_PER_PRDT
);
552 // According to AHCI 1.3 spec, a PRDT entry can point to a maximum 4MB data block.
553 // It also limits that the maximum amount of the PRDT entry in the command table
556 ASSERT (PrdtNumber
<= 65535);
558 Data64
.Uint64
= (UINTN
) (AhciRegisters
->AhciRFis
) + sizeof (EFI_AHCI_RECEIVED_FIS
) * Port
;
560 BaseAddr
= Data64
.Uint64
;
562 ZeroMem ((VOID
*)((UINTN
) BaseAddr
), sizeof (EFI_AHCI_RECEIVED_FIS
));
564 ZeroMem (AhciRegisters
->AhciCommandTable
, sizeof (EFI_AHCI_COMMAND_TABLE
));
566 CommandFis
->AhciCFisPmNum
= PortMultiplier
;
568 CopyMem (&AhciRegisters
->AhciCommandTable
->CommandFis
, CommandFis
, sizeof (EFI_AHCI_COMMAND_FIS
));
570 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_CMD
;
571 if (AtapiCommand
!= NULL
) {
573 &AhciRegisters
->AhciCommandTable
->AtapiCmd
,
578 CommandList
->AhciCmdA
= 1;
579 CommandList
->AhciCmdP
= 1;
581 AhciOrReg (PciIo
, Offset
, (EFI_AHCI_PORT_CMD_DLAE
| EFI_AHCI_PORT_CMD_ATAPI
));
583 AhciAndReg (PciIo
, Offset
, (UINT32
)~(EFI_AHCI_PORT_CMD_DLAE
| EFI_AHCI_PORT_CMD_ATAPI
));
586 RemainedData
= (UINTN
) DataLength
;
587 MemAddr
= (UINTN
) DataPhysicalAddr
;
588 CommandList
->AhciCmdPrdtl
= PrdtNumber
;
590 for (PrdtIndex
= 0; PrdtIndex
< PrdtNumber
; PrdtIndex
++) {
591 if (RemainedData
< EFI_AHCI_MAX_DATA_PER_PRDT
) {
592 AhciRegisters
->AhciCommandTable
->PrdtTable
[PrdtIndex
].AhciPrdtDbc
= (UINT32
)RemainedData
- 1;
594 AhciRegisters
->AhciCommandTable
->PrdtTable
[PrdtIndex
].AhciPrdtDbc
= EFI_AHCI_MAX_DATA_PER_PRDT
- 1;
597 Data64
.Uint64
= (UINT64
)MemAddr
;
598 AhciRegisters
->AhciCommandTable
->PrdtTable
[PrdtIndex
].AhciPrdtDba
= Data64
.Uint32
.Lower32
;
599 AhciRegisters
->AhciCommandTable
->PrdtTable
[PrdtIndex
].AhciPrdtDbau
= Data64
.Uint32
.Upper32
;
600 RemainedData
-= EFI_AHCI_MAX_DATA_PER_PRDT
;
601 MemAddr
+= EFI_AHCI_MAX_DATA_PER_PRDT
;
605 // Set the last PRDT to Interrupt On Complete
607 if (PrdtNumber
> 0) {
608 AhciRegisters
->AhciCommandTable
->PrdtTable
[PrdtNumber
- 1].AhciPrdtIoc
= 1;
612 (VOID
*) ((UINTN
) AhciRegisters
->AhciCmdList
+ (UINTN
) CommandSlotNumber
* sizeof (EFI_AHCI_COMMAND_LIST
)),
614 sizeof (EFI_AHCI_COMMAND_LIST
)
617 Data64
.Uint64
= (UINT64
)(UINTN
) AhciRegisters
->AhciCommandTablePciAddr
;
618 AhciRegisters
->AhciCmdList
[CommandSlotNumber
].AhciCmdCtba
= Data64
.Uint32
.Lower32
;
619 AhciRegisters
->AhciCmdList
[CommandSlotNumber
].AhciCmdCtbau
= Data64
.Uint32
.Upper32
;
620 AhciRegisters
->AhciCmdList
[CommandSlotNumber
].AhciCmdPmp
= PortMultiplier
;
627 @param CmdFis A pointer to the EFI_AHCI_COMMAND_FIS data structure.
628 @param AtaCommandBlock A pointer to the AhciBuildCommandFis data structure.
633 AhciBuildCommandFis (
634 IN OUT EFI_AHCI_COMMAND_FIS
*CmdFis
,
635 IN EFI_ATA_COMMAND_BLOCK
*AtaCommandBlock
638 ZeroMem (CmdFis
, sizeof (EFI_AHCI_COMMAND_FIS
));
640 CmdFis
->AhciCFisType
= EFI_AHCI_FIS_REGISTER_H2D
;
642 // Indicator it's a command
644 CmdFis
->AhciCFisCmdInd
= 0x1;
645 CmdFis
->AhciCFisCmd
= AtaCommandBlock
->AtaCommand
;
647 CmdFis
->AhciCFisFeature
= AtaCommandBlock
->AtaFeatures
;
648 CmdFis
->AhciCFisFeatureExp
= AtaCommandBlock
->AtaFeaturesExp
;
650 CmdFis
->AhciCFisSecNum
= AtaCommandBlock
->AtaSectorNumber
;
651 CmdFis
->AhciCFisSecNumExp
= AtaCommandBlock
->AtaSectorNumberExp
;
653 CmdFis
->AhciCFisClyLow
= AtaCommandBlock
->AtaCylinderLow
;
654 CmdFis
->AhciCFisClyLowExp
= AtaCommandBlock
->AtaCylinderLowExp
;
656 CmdFis
->AhciCFisClyHigh
= AtaCommandBlock
->AtaCylinderHigh
;
657 CmdFis
->AhciCFisClyHighExp
= AtaCommandBlock
->AtaCylinderHighExp
;
659 CmdFis
->AhciCFisSecCount
= AtaCommandBlock
->AtaSectorCount
;
660 CmdFis
->AhciCFisSecCountExp
= AtaCommandBlock
->AtaSectorCountExp
;
662 CmdFis
->AhciCFisDevHead
= (UINT8
) (AtaCommandBlock
->AtaDeviceHead
| 0xE0);
666 Start a PIO data transfer on specific port.
668 @param[in] PciIo The PCI IO protocol instance.
669 @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
670 @param[in] Port The number of port.
671 @param[in] PortMultiplier The timeout value of stop.
672 @param[in] AtapiCommand The atapi command will be used for the
674 @param[in] AtapiCommandLength The length of the atapi command.
675 @param[in] Read The transfer direction.
676 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
677 @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
678 @param[in, out] MemoryAddr The pointer to the data buffer.
679 @param[in] DataCount The data count to be transferred.
680 @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
681 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
682 used by non-blocking mode.
684 @retval EFI_DEVICE_ERROR The PIO data transfer abort with error occurs.
685 @retval EFI_TIMEOUT The operation is time out.
686 @retval EFI_UNSUPPORTED The device is not ready for transfer.
687 @retval EFI_SUCCESS The PIO data transfer executes successfully.
693 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
694 IN EFI_AHCI_REGISTERS
*AhciRegisters
,
696 IN UINT8 PortMultiplier
,
697 IN EFI_AHCI_ATAPI_COMMAND
*AtapiCommand OPTIONAL
,
698 IN UINT8 AtapiCommandLength
,
700 IN EFI_ATA_COMMAND_BLOCK
*AtaCommandBlock
,
701 IN OUT EFI_ATA_STATUS_BLOCK
*AtaStatusBlock
,
702 IN OUT VOID
*MemoryAddr
,
705 IN ATA_NONBLOCK_TASK
*Task
711 EFI_PHYSICAL_ADDRESS PhyAddr
;
714 EFI_PCI_IO_PROTOCOL_OPERATION Flag
;
716 EFI_AHCI_COMMAND_FIS CFis
;
717 EFI_AHCI_COMMAND_LIST CmdList
;
720 BOOLEAN InfiniteWait
;
721 BOOLEAN PioFisReceived
;
722 BOOLEAN D2hFisReceived
;
727 InfiniteWait
= FALSE
;
731 Flag
= EfiPciIoOperationBusMasterWrite
;
733 Flag
= EfiPciIoOperationBusMasterRead
;
737 // construct command list and command table with pci bus address
739 MapLength
= DataCount
;
740 Status
= PciIo
->Map (
749 if (EFI_ERROR (Status
) || (DataCount
!= MapLength
)) {
750 return EFI_BAD_BUFFER_SIZE
;
754 // Package read needed
756 AhciBuildCommandFis (&CFis
, AtaCommandBlock
);
758 ZeroMem (&CmdList
, sizeof (EFI_AHCI_COMMAND_LIST
));
760 CmdList
.AhciCmdCfl
= EFI_AHCI_FIS_REGISTER_H2D_LENGTH
/ 4;
761 CmdList
.AhciCmdW
= Read
? 0 : 1;
773 (VOID
*)(UINTN
)PhyAddr
,
777 Status
= AhciStartCommand (
783 if (EFI_ERROR (Status
)) {
788 // Check the status and wait the driver sending data
790 FisBaseAddr
= (UINTN
)AhciRegisters
->AhciRFis
+ Port
* sizeof (EFI_AHCI_RECEIVED_FIS
);
792 if (Read
&& (AtapiCommand
== 0)) {
794 // Wait device sends the PIO setup fis before data transfer
796 Status
= EFI_TIMEOUT
;
797 Delay
= DivU64x32 (Timeout
, 1000) + 1;
799 PioFisReceived
= FALSE
;
800 D2hFisReceived
= FALSE
;
801 Offset
= FisBaseAddr
+ EFI_AHCI_PIO_FIS_OFFSET
;
802 Status
= AhciCheckMemSet (Offset
, EFI_AHCI_FIS_TYPE_MASK
, EFI_AHCI_FIS_PIO_SETUP
, NULL
);
803 if (!EFI_ERROR (Status
)) {
804 PioFisReceived
= TRUE
;
807 // According to SATA 2.6 spec section 11.7, D2h FIS means an error encountered.
808 // But Qemu and Marvel 9230 sata controller may just receive a D2h FIS from device
809 // after the transaction is finished successfully.
810 // To get better device compatibilities, we further check if the PxTFD's ERR bit is set.
811 // By this way, we can know if there is a real error happened.
813 Offset
= FisBaseAddr
+ EFI_AHCI_D2H_FIS_OFFSET
;
814 Status
= AhciCheckMemSet (Offset
, EFI_AHCI_FIS_TYPE_MASK
, EFI_AHCI_FIS_REGISTER_D2H
, NULL
);
815 if (!EFI_ERROR (Status
)) {
816 D2hFisReceived
= TRUE
;
819 if (PioFisReceived
|| D2hFisReceived
) {
820 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_TFD
;
821 PortTfd
= AhciReadReg (PciIo
, (UINT32
) Offset
);
823 // PxTFD will be updated if there is a D2H or SetupFIS received.
825 if ((PortTfd
& EFI_AHCI_PORT_TFD_ERR
) != 0) {
826 Status
= EFI_DEVICE_ERROR
;
830 PrdCount
= *(volatile UINT32
*) (&(AhciRegisters
->AhciCmdList
[0].AhciCmdPrdbc
));
831 if (PrdCount
== DataCount
) {
832 Status
= EFI_SUCCESS
;
838 // Stall for 100 microseconds.
840 MicroSecondDelay(100);
844 Status
= EFI_TIMEOUT
;
846 } while (InfiniteWait
|| (Delay
> 0));
849 // Wait for D2H Fis is received
851 Offset
= FisBaseAddr
+ EFI_AHCI_D2H_FIS_OFFSET
;
852 Status
= AhciWaitMemSet (
854 EFI_AHCI_FIS_TYPE_MASK
,
855 EFI_AHCI_FIS_REGISTER_D2H
,
859 if (EFI_ERROR (Status
)) {
863 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_TFD
;
864 PortTfd
= AhciReadReg (PciIo
, (UINT32
) Offset
);
865 if ((PortTfd
& EFI_AHCI_PORT_TFD_ERR
) != 0) {
866 Status
= EFI_DEVICE_ERROR
;
877 AhciDisableFisReceive (
888 AhciDumpPortStatus (PciIo
, AhciRegisters
, Port
, AtaStatusBlock
);
894 Start a DMA data transfer on specific port
896 @param[in] Instance The ATA_ATAPI_PASS_THRU_INSTANCE protocol instance.
897 @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
898 @param[in] Port The number of port.
899 @param[in] PortMultiplier The timeout value of stop.
900 @param[in] AtapiCommand The atapi command will be used for the
902 @param[in] AtapiCommandLength The length of the atapi command.
903 @param[in] Read The transfer direction.
904 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
905 @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
906 @param[in, out] MemoryAddr The pointer to the data buffer.
907 @param[in] DataCount The data count to be transferred.
908 @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
909 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
910 used by non-blocking mode.
912 @retval EFI_DEVICE_ERROR The DMA data transfer abort with error occurs.
913 @retval EFI_TIMEOUT The operation is time out.
914 @retval EFI_UNSUPPORTED The device is not ready for transfer.
915 @retval EFI_SUCCESS The DMA data transfer executes successfully.
921 IN ATA_ATAPI_PASS_THRU_INSTANCE
*Instance
,
922 IN EFI_AHCI_REGISTERS
*AhciRegisters
,
924 IN UINT8 PortMultiplier
,
925 IN EFI_AHCI_ATAPI_COMMAND
*AtapiCommand OPTIONAL
,
926 IN UINT8 AtapiCommandLength
,
928 IN EFI_ATA_COMMAND_BLOCK
*AtaCommandBlock
,
929 IN OUT EFI_ATA_STATUS_BLOCK
*AtaStatusBlock
,
930 IN OUT VOID
*MemoryAddr
,
933 IN ATA_NONBLOCK_TASK
*Task
938 EFI_PHYSICAL_ADDRESS PhyAddr
;
941 EFI_PCI_IO_PROTOCOL_OPERATION Flag
;
942 EFI_AHCI_COMMAND_FIS CFis
;
943 EFI_AHCI_COMMAND_LIST CmdList
;
947 EFI_PCI_IO_PROTOCOL
*PciIo
;
951 PciIo
= Instance
->PciIo
;
954 return EFI_INVALID_PARAMETER
;
958 // Before starting the Blocking BlockIO operation, push to finish all non-blocking
960 // Delay 100us to simulate the blocking time out checking.
962 OldTpl
= gBS
->RaiseTPL (TPL_NOTIFY
);
963 while ((Task
== NULL
) && (!IsListEmpty (&Instance
->NonBlockingTaskList
))) {
964 AsyncNonBlockingTransferRoutine (NULL
, Instance
);
968 MicroSecondDelay (100);
970 gBS
->RestoreTPL (OldTpl
);
972 if ((Task
== NULL
) || ((Task
!= NULL
) && (!Task
->IsStart
))) {
974 // Mark the Task to indicate that it has been started.
977 Task
->IsStart
= TRUE
;
980 Flag
= EfiPciIoOperationBusMasterWrite
;
982 Flag
= EfiPciIoOperationBusMasterRead
;
986 // Construct command list and command table with pci bus address.
988 MapLength
= DataCount
;
989 Status
= PciIo
->Map (
998 if (EFI_ERROR (Status
) || (DataCount
!= MapLength
)) {
999 return EFI_BAD_BUFFER_SIZE
;
1006 // Package read needed
1008 AhciBuildCommandFis (&CFis
, AtaCommandBlock
);
1010 ZeroMem (&CmdList
, sizeof (EFI_AHCI_COMMAND_LIST
));
1012 CmdList
.AhciCmdCfl
= EFI_AHCI_FIS_REGISTER_H2D_LENGTH
/ 4;
1013 CmdList
.AhciCmdW
= Read
? 0 : 1;
1025 (VOID
*)(UINTN
)PhyAddr
,
1029 Status
= AhciStartCommand (
1035 if (EFI_ERROR (Status
)) {
1041 // Wait for command compelte
1043 FisBaseAddr
= (UINTN
)AhciRegisters
->AhciRFis
+ Port
* sizeof (EFI_AHCI_RECEIVED_FIS
);
1044 Offset
= FisBaseAddr
+ EFI_AHCI_D2H_FIS_OFFSET
;
1049 Status
= AhciCheckMemSet (
1051 EFI_AHCI_FIS_TYPE_MASK
,
1052 EFI_AHCI_FIS_REGISTER_D2H
,
1056 Status
= AhciWaitMemSet (
1058 EFI_AHCI_FIS_TYPE_MASK
,
1059 EFI_AHCI_FIS_REGISTER_D2H
,
1064 if (EFI_ERROR (Status
)) {
1068 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_TFD
;
1069 PortTfd
= AhciReadReg (PciIo
, (UINT32
) Offset
);
1070 if ((PortTfd
& EFI_AHCI_PORT_TFD_ERR
) != 0) {
1071 Status
= EFI_DEVICE_ERROR
;
1076 // For Blocking mode, the command should be stopped, the Fis should be disabled
1077 // and the PciIo should be unmapped.
1078 // For non-blocking mode, only when a error is happened (if the return status is
1079 // EFI_NOT_READY that means the command doesn't finished, try again.), first do the
1080 // context cleanup, then set the packet's Asb status.
1083 ((Task
!= NULL
) && (Status
!= EFI_NOT_READY
))
1091 AhciDisableFisReceive (
1099 (Task
!= NULL
) ? Task
->Map
: Map
1103 Task
->Packet
->Asb
->AtaStatus
= 0x01;
1107 AhciDumpPortStatus (PciIo
, AhciRegisters
, Port
, AtaStatusBlock
);
1112 Start a non data transfer on specific port.
1114 @param[in] PciIo The PCI IO protocol instance.
1115 @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1116 @param[in] Port The number of port.
1117 @param[in] PortMultiplier The timeout value of stop.
1118 @param[in] AtapiCommand The atapi command will be used for the
1120 @param[in] AtapiCommandLength The length of the atapi command.
1121 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
1122 @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
1123 @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
1124 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1125 used by non-blocking mode.
1127 @retval EFI_DEVICE_ERROR The non data transfer abort with error occurs.
1128 @retval EFI_TIMEOUT The operation is time out.
1129 @retval EFI_UNSUPPORTED The device is not ready for transfer.
1130 @retval EFI_SUCCESS The non data transfer executes successfully.
1135 AhciNonDataTransfer (
1136 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1137 IN EFI_AHCI_REGISTERS
*AhciRegisters
,
1139 IN UINT8 PortMultiplier
,
1140 IN EFI_AHCI_ATAPI_COMMAND
*AtapiCommand OPTIONAL
,
1141 IN UINT8 AtapiCommandLength
,
1142 IN EFI_ATA_COMMAND_BLOCK
*AtaCommandBlock
,
1143 IN OUT EFI_ATA_STATUS_BLOCK
*AtaStatusBlock
,
1145 IN ATA_NONBLOCK_TASK
*Task
1152 EFI_AHCI_COMMAND_FIS CFis
;
1153 EFI_AHCI_COMMAND_LIST CmdList
;
1156 // Package read needed
1158 AhciBuildCommandFis (&CFis
, AtaCommandBlock
);
1160 ZeroMem (&CmdList
, sizeof (EFI_AHCI_COMMAND_LIST
));
1162 CmdList
.AhciCmdCfl
= EFI_AHCI_FIS_REGISTER_H2D_LENGTH
/ 4;
1178 Status
= AhciStartCommand (
1184 if (EFI_ERROR (Status
)) {
1189 // Wait device sends the Response Fis
1191 FisBaseAddr
= (UINTN
)AhciRegisters
->AhciRFis
+ Port
* sizeof (EFI_AHCI_RECEIVED_FIS
);
1192 Offset
= FisBaseAddr
+ EFI_AHCI_D2H_FIS_OFFSET
;
1193 Status
= AhciWaitMemSet (
1195 EFI_AHCI_FIS_TYPE_MASK
,
1196 EFI_AHCI_FIS_REGISTER_D2H
,
1200 if (EFI_ERROR (Status
)) {
1204 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_TFD
;
1205 PortTfd
= AhciReadReg (PciIo
, (UINT32
) Offset
);
1206 if ((PortTfd
& EFI_AHCI_PORT_TFD_ERR
) != 0) {
1207 Status
= EFI_DEVICE_ERROR
;
1217 AhciDisableFisReceive (
1223 AhciDumpPortStatus (PciIo
, AhciRegisters
, Port
, AtaStatusBlock
);
1229 Stop command running for giving port
1231 @param PciIo The PCI IO protocol instance.
1232 @param Port The number of port.
1233 @param Timeout The timeout value of stop, uses 100ns as a unit.
1235 @retval EFI_DEVICE_ERROR The command stop unsuccessfully.
1236 @retval EFI_TIMEOUT The operation is time out.
1237 @retval EFI_SUCCESS The command stop successfully.
1243 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1251 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_CMD
;
1252 Data
= AhciReadReg (PciIo
, Offset
);
1254 if ((Data
& (EFI_AHCI_PORT_CMD_ST
| EFI_AHCI_PORT_CMD_CR
)) == 0) {
1258 if ((Data
& EFI_AHCI_PORT_CMD_ST
) != 0) {
1259 AhciAndReg (PciIo
, Offset
, (UINT32
)~(EFI_AHCI_PORT_CMD_ST
));
1262 return AhciWaitMmioSet (
1265 EFI_AHCI_PORT_CMD_CR
,
1272 Start command for give slot on specific port.
1274 @param PciIo The PCI IO protocol instance.
1275 @param Port The number of port.
1276 @param CommandSlot The number of Command Slot.
1277 @param Timeout The timeout value of start, uses 100ns as a unit.
1279 @retval EFI_DEVICE_ERROR The command start unsuccessfully.
1280 @retval EFI_TIMEOUT The operation is time out.
1281 @retval EFI_SUCCESS The command start successfully.
1287 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1289 IN UINT8 CommandSlot
,
1302 // Collect AHCI controller information
1304 Capability
= AhciReadReg(PciIo
, EFI_AHCI_CAPABILITY_OFFSET
);
1306 CmdSlotBit
= (UINT32
) (1 << CommandSlot
);
1308 AhciClearPortStatus (
1313 Status
= AhciEnableFisReceive (
1319 if (EFI_ERROR (Status
)) {
1323 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_CMD
;
1324 PortStatus
= AhciReadReg (PciIo
, Offset
);
1327 if ((PortStatus
& EFI_AHCI_PORT_CMD_ALPE
) != 0) {
1328 StartCmd
= AhciReadReg (PciIo
, Offset
);
1329 StartCmd
&= ~EFI_AHCI_PORT_CMD_ICC_MASK
;
1330 StartCmd
|= EFI_AHCI_PORT_CMD_ACTIVE
;
1333 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_TFD
;
1334 PortTfd
= AhciReadReg (PciIo
, Offset
);
1336 if ((PortTfd
& (EFI_AHCI_PORT_TFD_BSY
| EFI_AHCI_PORT_TFD_DRQ
)) != 0) {
1337 if ((Capability
& BIT24
) != 0) {
1338 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_CMD
;
1339 AhciOrReg (PciIo
, Offset
, EFI_AHCI_PORT_CMD_CLO
);
1344 EFI_AHCI_PORT_CMD_CLO
,
1351 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_CMD
;
1352 AhciOrReg (PciIo
, Offset
, EFI_AHCI_PORT_CMD_ST
| StartCmd
);
1355 // Setting the command
1357 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_CI
;
1358 AhciAndReg (PciIo
, Offset
, 0);
1359 AhciOrReg (PciIo
, Offset
, CmdSlotBit
);
1367 @param PciIo The PCI IO protocol instance.
1368 @param Port The number of port.
1369 @param Timeout The timeout value of reset, uses 100ns as a unit.
1371 @retval EFI_DEVICE_ERROR The port reset unsuccessfully
1372 @retval EFI_TIMEOUT The reset operation is time out.
1373 @retval EFI_SUCCESS The port reset successfully.
1379 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1387 AhciClearPortStatus (PciIo
, Port
);
1389 AhciStopCommand (PciIo
, Port
, Timeout
);
1391 AhciDisableFisReceive (PciIo
, Port
, Timeout
);
1393 AhciEnableFisReceive (PciIo
, Port
, Timeout
);
1395 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_SCTL
;
1397 AhciOrReg (PciIo
, Offset
, EFI_AHCI_PORT_SCTL_DET_INIT
);
1400 // wait 5 millisecond before de-assert DET
1402 MicroSecondDelay (5000);
1404 AhciAndReg (PciIo
, Offset
, (UINT32
)EFI_AHCI_PORT_SCTL_MASK
);
1407 // wait 5 millisecond before de-assert DET
1409 MicroSecondDelay (5000);
1412 // Wait for communication to be re-established
1414 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_SSTS
;
1415 Status
= AhciWaitMmioSet (
1418 EFI_AHCI_PORT_SSTS_DET_MASK
,
1419 EFI_AHCI_PORT_SSTS_DET_PCE
,
1423 if (EFI_ERROR (Status
)) {
1424 DEBUG ((EFI_D_ERROR
, "Port %d COMRESET failed: %r\n", Port
, Status
));
1428 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_SERR
;
1429 AhciOrReg (PciIo
, Offset
, EFI_AHCI_PORT_ERR_CLEAR
);
1437 @param PciIo The PCI IO protocol instance.
1438 @param Timeout The timeout value of reset, uses 100ns as a unit.
1440 @retval EFI_DEVICE_ERROR AHCI controller is failed to complete hardware reset.
1441 @retval EFI_TIMEOUT The reset operation is time out.
1442 @retval EFI_SUCCESS AHCI controller is reset successfully.
1448 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1456 // Make sure that GHC.AE bit is set before accessing any AHCI registers.
1458 Value
= AhciReadReg(PciIo
, EFI_AHCI_GHC_OFFSET
);
1460 if ((Value
& EFI_AHCI_GHC_ENABLE
) == 0) {
1461 AhciOrReg (PciIo
, EFI_AHCI_GHC_OFFSET
, EFI_AHCI_GHC_ENABLE
);
1464 AhciOrReg (PciIo
, EFI_AHCI_GHC_OFFSET
, EFI_AHCI_GHC_RESET
);
1466 Delay
= DivU64x32(Timeout
, 1000) + 1;
1469 Value
= AhciReadReg(PciIo
, EFI_AHCI_GHC_OFFSET
);
1471 if ((Value
& EFI_AHCI_GHC_RESET
) == 0) {
1476 // Stall for 100 microseconds.
1478 MicroSecondDelay(100);
1481 } while (Delay
> 0);
1491 Send SMART Return Status command to check if the execution of SMART cmd is successful or not.
1493 @param PciIo The PCI IO protocol instance.
1494 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1495 @param Port The number of port.
1496 @param PortMultiplier The port multiplier port number.
1497 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1499 @retval EFI_SUCCESS Successfully get the return status of S.M.A.R.T command execution.
1500 @retval Others Fail to get return status data.
1505 AhciAtaSmartReturnStatusCheck (
1506 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1507 IN EFI_AHCI_REGISTERS
*AhciRegisters
,
1509 IN UINT8 PortMultiplier
,
1510 IN OUT EFI_ATA_STATUS_BLOCK
*AtaStatusBlock
1514 EFI_ATA_COMMAND_BLOCK AtaCommandBlock
;
1520 ZeroMem (&AtaCommandBlock
, sizeof (EFI_ATA_COMMAND_BLOCK
));
1522 AtaCommandBlock
.AtaCommand
= ATA_CMD_SMART
;
1523 AtaCommandBlock
.AtaFeatures
= ATA_SMART_RETURN_STATUS
;
1524 AtaCommandBlock
.AtaCylinderLow
= ATA_CONSTANT_4F
;
1525 AtaCommandBlock
.AtaCylinderHigh
= ATA_CONSTANT_C2
;
1528 // Send S.M.A.R.T Read Return Status command to device
1530 Status
= AhciNonDataTransfer (
1534 (UINT8
)PortMultiplier
,
1543 if (EFI_ERROR (Status
)) {
1544 REPORT_STATUS_CODE (
1545 EFI_ERROR_CODE
| EFI_ERROR_MINOR
,
1546 (EFI_IO_BUS_ATA_ATAPI
| EFI_IOB_ATA_BUS_SMART_DISABLED
)
1548 return EFI_DEVICE_ERROR
;
1551 REPORT_STATUS_CODE (
1553 (EFI_IO_BUS_ATA_ATAPI
| EFI_IOB_ATA_BUS_SMART_ENABLE
)
1556 FisBaseAddr
= (UINTN
)AhciRegisters
->AhciRFis
+ Port
* sizeof (EFI_AHCI_RECEIVED_FIS
);
1558 Value
= *(UINT32
*) (FisBaseAddr
+ EFI_AHCI_D2H_FIS_OFFSET
);
1560 if ((Value
& EFI_AHCI_FIS_TYPE_MASK
) == EFI_AHCI_FIS_REGISTER_D2H
) {
1561 LBAMid
= ((UINT8
*)(UINTN
)(FisBaseAddr
+ EFI_AHCI_D2H_FIS_OFFSET
))[5];
1562 LBAHigh
= ((UINT8
*)(UINTN
)(FisBaseAddr
+ EFI_AHCI_D2H_FIS_OFFSET
))[6];
1564 if ((LBAMid
== 0x4f) && (LBAHigh
== 0xc2)) {
1566 // The threshold exceeded condition is not detected by the device
1568 DEBUG ((EFI_D_INFO
, "The S.M.A.R.T threshold exceeded condition is not detected\n"));
1569 REPORT_STATUS_CODE (
1571 (EFI_IO_BUS_ATA_ATAPI
| EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD
)
1573 } else if ((LBAMid
== 0xf4) && (LBAHigh
== 0x2c)) {
1575 // The threshold exceeded condition is detected by the device
1577 DEBUG ((EFI_D_INFO
, "The S.M.A.R.T threshold exceeded condition is detected\n"));
1578 REPORT_STATUS_CODE (
1580 (EFI_IO_BUS_ATA_ATAPI
| EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD
)
1589 Enable SMART command of the disk if supported.
1591 @param PciIo The PCI IO protocol instance.
1592 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1593 @param Port The number of port.
1594 @param PortMultiplier The port multiplier port number.
1595 @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
1596 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1601 AhciAtaSmartSupport (
1602 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1603 IN EFI_AHCI_REGISTERS
*AhciRegisters
,
1605 IN UINT8 PortMultiplier
,
1606 IN EFI_IDENTIFY_DATA
*IdentifyData
,
1607 IN OUT EFI_ATA_STATUS_BLOCK
*AtaStatusBlock
1611 EFI_ATA_COMMAND_BLOCK AtaCommandBlock
;
1614 // Detect if the device supports S.M.A.R.T.
1616 if ((IdentifyData
->AtaData
.command_set_supported_82
& 0x0001) != 0x0001) {
1618 // S.M.A.R.T is not supported by the device
1620 DEBUG ((EFI_D_INFO
, "S.M.A.R.T feature is not supported at port [%d] PortMultiplier [%d]!\n",
1621 Port
, PortMultiplier
));
1622 REPORT_STATUS_CODE (
1623 EFI_ERROR_CODE
| EFI_ERROR_MINOR
,
1624 (EFI_IO_BUS_ATA_ATAPI
| EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED
)
1628 // Check if the feature is enabled. If not, then enable S.M.A.R.T.
1630 if ((IdentifyData
->AtaData
.command_set_feature_enb_85
& 0x0001) != 0x0001) {
1632 REPORT_STATUS_CODE (
1634 (EFI_IO_BUS_ATA_ATAPI
| EFI_IOB_ATA_BUS_SMART_DISABLE
)
1637 ZeroMem (&AtaCommandBlock
, sizeof (EFI_ATA_COMMAND_BLOCK
));
1639 AtaCommandBlock
.AtaCommand
= ATA_CMD_SMART
;
1640 AtaCommandBlock
.AtaFeatures
= ATA_SMART_ENABLE_OPERATION
;
1641 AtaCommandBlock
.AtaCylinderLow
= ATA_CONSTANT_4F
;
1642 AtaCommandBlock
.AtaCylinderHigh
= ATA_CONSTANT_C2
;
1645 // Send S.M.A.R.T Enable command to device
1647 Status
= AhciNonDataTransfer (
1651 (UINT8
)PortMultiplier
,
1661 if (!EFI_ERROR (Status
)) {
1663 // Send S.M.A.R.T AutoSave command to device
1665 ZeroMem (&AtaCommandBlock
, sizeof (EFI_ATA_COMMAND_BLOCK
));
1667 AtaCommandBlock
.AtaCommand
= ATA_CMD_SMART
;
1668 AtaCommandBlock
.AtaFeatures
= 0xD2;
1669 AtaCommandBlock
.AtaSectorCount
= 0xF1;
1670 AtaCommandBlock
.AtaCylinderLow
= ATA_CONSTANT_4F
;
1671 AtaCommandBlock
.AtaCylinderHigh
= ATA_CONSTANT_C2
;
1673 Status
= AhciNonDataTransfer (
1677 (UINT8
)PortMultiplier
,
1686 if (!EFI_ERROR (Status
)) {
1687 Status
= AhciAtaSmartReturnStatusCheck (
1691 (UINT8
)PortMultiplier
,
1697 DEBUG ((EFI_D_INFO
, "Enabled S.M.A.R.T feature at port [%d] PortMultiplier [%d]!\n",
1698 Port
, PortMultiplier
));
1705 Send Buffer cmd to specific device.
1707 @param PciIo The PCI IO protocol instance.
1708 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1709 @param Port The number of port.
1710 @param PortMultiplier The port multiplier port number.
1711 @param Buffer The data buffer to store IDENTIFY PACKET data.
1713 @retval EFI_DEVICE_ERROR The cmd abort with error occurs.
1714 @retval EFI_TIMEOUT The operation is time out.
1715 @retval EFI_UNSUPPORTED The device is not ready for executing.
1716 @retval EFI_SUCCESS The cmd executes successfully.
1722 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1723 IN EFI_AHCI_REGISTERS
*AhciRegisters
,
1725 IN UINT8 PortMultiplier
,
1726 IN OUT EFI_IDENTIFY_DATA
*Buffer
1730 EFI_ATA_COMMAND_BLOCK AtaCommandBlock
;
1731 EFI_ATA_STATUS_BLOCK AtaStatusBlock
;
1733 if (PciIo
== NULL
|| AhciRegisters
== NULL
|| Buffer
== NULL
) {
1734 return EFI_INVALID_PARAMETER
;
1737 ZeroMem (&AtaCommandBlock
, sizeof (EFI_ATA_COMMAND_BLOCK
));
1738 ZeroMem (&AtaStatusBlock
, sizeof (EFI_ATA_STATUS_BLOCK
));
1740 AtaCommandBlock
.AtaCommand
= ATA_CMD_IDENTIFY_DRIVE
;
1741 AtaCommandBlock
.AtaSectorCount
= 1;
1743 Status
= AhciPioTransfer (
1754 sizeof (EFI_IDENTIFY_DATA
),
1763 Send Buffer cmd to specific device.
1765 @param PciIo The PCI IO protocol instance.
1766 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1767 @param Port The number of port.
1768 @param PortMultiplier The port multiplier port number.
1769 @param Buffer The data buffer to store IDENTIFY PACKET data.
1771 @retval EFI_DEVICE_ERROR The cmd abort with error occurs.
1772 @retval EFI_TIMEOUT The operation is time out.
1773 @retval EFI_UNSUPPORTED The device is not ready for executing.
1774 @retval EFI_SUCCESS The cmd executes successfully.
1779 AhciIdentifyPacket (
1780 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1781 IN EFI_AHCI_REGISTERS
*AhciRegisters
,
1783 IN UINT8 PortMultiplier
,
1784 IN OUT EFI_IDENTIFY_DATA
*Buffer
1788 EFI_ATA_COMMAND_BLOCK AtaCommandBlock
;
1789 EFI_ATA_STATUS_BLOCK AtaStatusBlock
;
1791 if (PciIo
== NULL
|| AhciRegisters
== NULL
) {
1792 return EFI_INVALID_PARAMETER
;
1795 ZeroMem (&AtaCommandBlock
, sizeof (EFI_ATA_COMMAND_BLOCK
));
1796 ZeroMem (&AtaStatusBlock
, sizeof (EFI_ATA_STATUS_BLOCK
));
1798 AtaCommandBlock
.AtaCommand
= ATA_CMD_IDENTIFY_DEVICE
;
1799 AtaCommandBlock
.AtaSectorCount
= 1;
1801 Status
= AhciPioTransfer (
1812 sizeof (EFI_IDENTIFY_DATA
),
1821 Send SET FEATURE cmd on specific device.
1823 @param PciIo The PCI IO protocol instance.
1824 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1825 @param Port The number of port.
1826 @param PortMultiplier The port multiplier port number.
1827 @param Feature The data to send Feature register.
1828 @param FeatureSpecificData The specific data for SET FEATURE cmd.
1830 @retval EFI_DEVICE_ERROR The cmd abort with error occurs.
1831 @retval EFI_TIMEOUT The operation is time out.
1832 @retval EFI_UNSUPPORTED The device is not ready for executing.
1833 @retval EFI_SUCCESS The cmd executes successfully.
1838 AhciDeviceSetFeature (
1839 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1840 IN EFI_AHCI_REGISTERS
*AhciRegisters
,
1842 IN UINT8 PortMultiplier
,
1844 IN UINT32 FeatureSpecificData
1848 EFI_ATA_COMMAND_BLOCK AtaCommandBlock
;
1849 EFI_ATA_STATUS_BLOCK AtaStatusBlock
;
1851 ZeroMem (&AtaCommandBlock
, sizeof (EFI_ATA_COMMAND_BLOCK
));
1852 ZeroMem (&AtaStatusBlock
, sizeof (EFI_ATA_STATUS_BLOCK
));
1854 AtaCommandBlock
.AtaCommand
= ATA_CMD_SET_FEATURES
;
1855 AtaCommandBlock
.AtaFeatures
= (UINT8
) Feature
;
1856 AtaCommandBlock
.AtaFeaturesExp
= (UINT8
) (Feature
>> 8);
1857 AtaCommandBlock
.AtaSectorCount
= (UINT8
) FeatureSpecificData
;
1858 AtaCommandBlock
.AtaSectorNumber
= (UINT8
) (FeatureSpecificData
>> 8);
1859 AtaCommandBlock
.AtaCylinderLow
= (UINT8
) (FeatureSpecificData
>> 16);
1860 AtaCommandBlock
.AtaCylinderHigh
= (UINT8
) (FeatureSpecificData
>> 24);
1862 Status
= AhciNonDataTransfer (
1866 (UINT8
)PortMultiplier
,
1879 This function is used to send out ATAPI commands conforms to the Packet Command
1882 @param PciIo The PCI IO protocol instance.
1883 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1884 @param Port The number of port.
1885 @param PortMultiplier The number of port multiplier.
1886 @param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
1888 @retval EFI_SUCCESS send out the ATAPI packet command successfully
1889 and device sends data successfully.
1890 @retval EFI_DEVICE_ERROR the device failed to send data.
1895 AhciPacketCommandExecute (
1896 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1897 IN EFI_AHCI_REGISTERS
*AhciRegisters
,
1899 IN UINT8 PortMultiplier
,
1900 IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET
*Packet
1906 EFI_ATA_COMMAND_BLOCK AtaCommandBlock
;
1907 EFI_ATA_STATUS_BLOCK AtaStatusBlock
;
1910 if (Packet
== NULL
|| Packet
->Cdb
== NULL
) {
1911 return EFI_INVALID_PARAMETER
;
1914 ZeroMem (&AtaCommandBlock
, sizeof (EFI_ATA_COMMAND_BLOCK
));
1915 ZeroMem (&AtaStatusBlock
, sizeof (EFI_ATA_STATUS_BLOCK
));
1916 AtaCommandBlock
.AtaCommand
= ATA_CMD_PACKET
;
1920 AtaCommandBlock
.AtaFeatures
= 0x00;
1922 // set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device
1923 // determine how many data should be transferred.
1925 AtaCommandBlock
.AtaCylinderLow
= (UINT8
) (ATAPI_MAX_BYTE_COUNT
& 0x00ff);
1926 AtaCommandBlock
.AtaCylinderHigh
= (UINT8
) (ATAPI_MAX_BYTE_COUNT
>> 8);
1928 if (Packet
->DataDirection
== EFI_EXT_SCSI_DATA_DIRECTION_READ
) {
1929 Buffer
= Packet
->InDataBuffer
;
1930 Length
= Packet
->InTransferLength
;
1933 Buffer
= Packet
->OutDataBuffer
;
1934 Length
= Packet
->OutTransferLength
;
1939 Status
= AhciNonDataTransfer (
1952 Status
= AhciPioTransfer (
1972 Allocate transfer-related data struct which is used at AHCI mode.
1974 @param PciIo The PCI IO protocol instance.
1975 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1980 AhciCreateTransferDescriptor (
1981 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1982 IN OUT EFI_AHCI_REGISTERS
*AhciRegisters
1990 UINT32 PortImplementBitMap
;
1991 UINT8 MaxPortNumber
;
1992 UINT8 MaxCommandSlotNumber
;
1993 BOOLEAN Support64Bit
;
1994 UINT64 MaxReceiveFisSize
;
1995 UINT64 MaxCommandListSize
;
1996 UINT64 MaxCommandTableSize
;
1997 EFI_PHYSICAL_ADDRESS AhciRFisPciAddr
;
1998 EFI_PHYSICAL_ADDRESS AhciCmdListPciAddr
;
1999 EFI_PHYSICAL_ADDRESS AhciCommandTablePciAddr
;
2003 // Collect AHCI controller information
2005 Capability
= AhciReadReg(PciIo
, EFI_AHCI_CAPABILITY_OFFSET
);
2007 // Get the number of command slots per port supported by this HBA.
2009 MaxCommandSlotNumber
= (UINT8
) (((Capability
& 0x1F00) >> 8) + 1);
2010 Support64Bit
= (BOOLEAN
) (((Capability
& BIT31
) != 0) ? TRUE
: FALSE
);
2012 PortImplementBitMap
= AhciReadReg(PciIo
, EFI_AHCI_PI_OFFSET
);
2014 // Get the highest bit of implemented ports which decides how many bytes are allocated for recived FIS.
2016 MaxPortNumber
= (UINT8
)(UINTN
)(HighBitSet32(PortImplementBitMap
) + 1);
2017 if (MaxPortNumber
== 0) {
2018 return EFI_DEVICE_ERROR
;
2021 MaxReceiveFisSize
= MaxPortNumber
* sizeof (EFI_AHCI_RECEIVED_FIS
);
2022 Status
= PciIo
->AllocateBuffer (
2025 EfiBootServicesData
,
2026 EFI_SIZE_TO_PAGES ((UINTN
) MaxReceiveFisSize
),
2031 if (EFI_ERROR (Status
)) {
2032 return EFI_OUT_OF_RESOURCES
;
2035 ZeroMem (Buffer
, (UINTN
)MaxReceiveFisSize
);
2037 AhciRegisters
->AhciRFis
= Buffer
;
2038 AhciRegisters
->MaxReceiveFisSize
= MaxReceiveFisSize
;
2039 Bytes
= (UINTN
)MaxReceiveFisSize
;
2041 Status
= PciIo
->Map (
2043 EfiPciIoOperationBusMasterCommonBuffer
,
2047 &AhciRegisters
->MapRFis
2050 if (EFI_ERROR (Status
) || (Bytes
!= MaxReceiveFisSize
)) {
2052 // Map error or unable to map the whole RFis buffer into a contiguous region.
2054 Status
= EFI_OUT_OF_RESOURCES
;
2058 if ((!Support64Bit
) && (AhciRFisPciAddr
> 0x100000000ULL
)) {
2060 // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2062 Status
= EFI_DEVICE_ERROR
;
2065 AhciRegisters
->AhciRFisPciAddr
= (EFI_AHCI_RECEIVED_FIS
*)(UINTN
)AhciRFisPciAddr
;
2068 // Allocate memory for command list
2069 // Note that the implemenation is a single task model which only use a command list for all ports.
2072 MaxCommandListSize
= MaxCommandSlotNumber
* sizeof (EFI_AHCI_COMMAND_LIST
);
2073 Status
= PciIo
->AllocateBuffer (
2076 EfiBootServicesData
,
2077 EFI_SIZE_TO_PAGES ((UINTN
) MaxCommandListSize
),
2082 if (EFI_ERROR (Status
)) {
2084 // Free mapped resource.
2086 Status
= EFI_OUT_OF_RESOURCES
;
2090 ZeroMem (Buffer
, (UINTN
)MaxCommandListSize
);
2092 AhciRegisters
->AhciCmdList
= Buffer
;
2093 AhciRegisters
->MaxCommandListSize
= MaxCommandListSize
;
2094 Bytes
= (UINTN
)MaxCommandListSize
;
2096 Status
= PciIo
->Map (
2098 EfiPciIoOperationBusMasterCommonBuffer
,
2101 &AhciCmdListPciAddr
,
2102 &AhciRegisters
->MapCmdList
2105 if (EFI_ERROR (Status
) || (Bytes
!= MaxCommandListSize
)) {
2107 // Map error or unable to map the whole cmd list buffer into a contiguous region.
2109 Status
= EFI_OUT_OF_RESOURCES
;
2113 if ((!Support64Bit
) && (AhciCmdListPciAddr
> 0x100000000ULL
)) {
2115 // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2117 Status
= EFI_DEVICE_ERROR
;
2120 AhciRegisters
->AhciCmdListPciAddr
= (EFI_AHCI_COMMAND_LIST
*)(UINTN
)AhciCmdListPciAddr
;
2123 // Allocate memory for command table
2124 // According to AHCI 1.3 spec, a PRD table can contain maximum 65535 entries.
2127 MaxCommandTableSize
= sizeof (EFI_AHCI_COMMAND_TABLE
);
2129 Status
= PciIo
->AllocateBuffer (
2132 EfiBootServicesData
,
2133 EFI_SIZE_TO_PAGES ((UINTN
) MaxCommandTableSize
),
2138 if (EFI_ERROR (Status
)) {
2140 // Free mapped resource.
2142 Status
= EFI_OUT_OF_RESOURCES
;
2146 ZeroMem (Buffer
, (UINTN
)MaxCommandTableSize
);
2148 AhciRegisters
->AhciCommandTable
= Buffer
;
2149 AhciRegisters
->MaxCommandTableSize
= MaxCommandTableSize
;
2150 Bytes
= (UINTN
)MaxCommandTableSize
;
2152 Status
= PciIo
->Map (
2154 EfiPciIoOperationBusMasterCommonBuffer
,
2157 &AhciCommandTablePciAddr
,
2158 &AhciRegisters
->MapCommandTable
2161 if (EFI_ERROR (Status
) || (Bytes
!= MaxCommandTableSize
)) {
2163 // Map error or unable to map the whole cmd list buffer into a contiguous region.
2165 Status
= EFI_OUT_OF_RESOURCES
;
2169 if ((!Support64Bit
) && (AhciCommandTablePciAddr
> 0x100000000ULL
)) {
2171 // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2173 Status
= EFI_DEVICE_ERROR
;
2176 AhciRegisters
->AhciCommandTablePciAddr
= (EFI_AHCI_COMMAND_TABLE
*)(UINTN
)AhciCommandTablePciAddr
;
2180 // Map error or unable to map the whole CmdList buffer into a contiguous region.
2185 AhciRegisters
->MapCommandTable
2190 EFI_SIZE_TO_PAGES ((UINTN
) MaxCommandTableSize
),
2191 AhciRegisters
->AhciCommandTable
2196 AhciRegisters
->MapCmdList
2201 EFI_SIZE_TO_PAGES ((UINTN
) MaxCommandListSize
),
2202 AhciRegisters
->AhciCmdList
2207 AhciRegisters
->MapRFis
2212 EFI_SIZE_TO_PAGES ((UINTN
) MaxReceiveFisSize
),
2213 AhciRegisters
->AhciRFis
2220 Initialize ATA host controller at AHCI mode.
2222 The function is designed to initialize ATA host controller.
2224 @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
2229 AhciModeInitialization (
2230 IN ATA_ATAPI_PASS_THRU_INSTANCE
*Instance
2234 EFI_PCI_IO_PROTOCOL
*PciIo
;
2235 EFI_IDE_CONTROLLER_INIT_PROTOCOL
*IdeInit
;
2237 UINT8 MaxPortNumber
;
2238 UINT32 PortImplementBitMap
;
2240 EFI_AHCI_REGISTERS
*AhciRegisters
;
2246 EFI_IDENTIFY_DATA Buffer
;
2247 EFI_ATA_DEVICE_TYPE DeviceType
;
2248 EFI_ATA_COLLECTIVE_MODE
*SupportedModes
;
2249 EFI_ATA_TRANSFER_MODE TransferMode
;
2250 UINT32 PhyDetectDelay
;
2253 if (Instance
== NULL
) {
2254 return EFI_INVALID_PARAMETER
;
2257 PciIo
= Instance
->PciIo
;
2258 IdeInit
= Instance
->IdeControllerInit
;
2260 Status
= AhciReset (PciIo
, EFI_AHCI_BUS_RESET_TIMEOUT
);
2262 if (EFI_ERROR (Status
)) {
2263 return EFI_DEVICE_ERROR
;
2267 // Collect AHCI controller information
2269 Capability
= AhciReadReg (PciIo
, EFI_AHCI_CAPABILITY_OFFSET
);
2272 // Make sure that GHC.AE bit is set before accessing any AHCI registers.
2274 Value
= AhciReadReg(PciIo
, EFI_AHCI_GHC_OFFSET
);
2276 if ((Value
& EFI_AHCI_GHC_ENABLE
) == 0) {
2277 AhciOrReg (PciIo
, EFI_AHCI_GHC_OFFSET
, EFI_AHCI_GHC_ENABLE
);
2281 // Enable 64-bit DMA support in the PCI layer if this controller
2284 if ((Capability
& EFI_AHCI_CAP_S64A
) != 0) {
2285 Status
= PciIo
->Attributes (
2287 EfiPciIoAttributeOperationEnable
,
2288 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
,
2291 if (EFI_ERROR (Status
)) {
2293 "AhciModeInitialization: failed to enable 64-bit DMA on 64-bit capable controller (%r)\n",
2299 // Get the number of command slots per port supported by this HBA.
2301 MaxPortNumber
= (UINT8
) ((Capability
& 0x1F) + 1);
2304 // Get the bit map of those ports exposed by this HBA.
2305 // It indicates which ports that the HBA supports are available for software to use.
2307 PortImplementBitMap
= AhciReadReg(PciIo
, EFI_AHCI_PI_OFFSET
);
2309 AhciRegisters
= &Instance
->AhciRegisters
;
2310 Status
= AhciCreateTransferDescriptor (PciIo
, AhciRegisters
);
2312 if (EFI_ERROR (Status
)) {
2313 return EFI_OUT_OF_RESOURCES
;
2316 for (Port
= 0; Port
< EFI_AHCI_MAX_PORTS
; Port
++) {
2317 if ((PortImplementBitMap
& (((UINT32
)BIT0
) << Port
)) != 0) {
2319 // According to AHCI spec, MaxPortNumber should be equal or greater than the number of implemented ports.
2321 if ((MaxPortNumber
--) == 0) {
2323 // Should never be here.
2329 IdeInit
->NotifyPhase (IdeInit
, EfiIdeBeforeChannelEnumeration
, Port
);
2332 // Initialize FIS Base Address Register and Command List Base Address Register for use.
2334 Data64
.Uint64
= (UINTN
) (AhciRegisters
->AhciRFisPciAddr
) + sizeof (EFI_AHCI_RECEIVED_FIS
) * Port
;
2335 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_FB
;
2336 AhciWriteReg (PciIo
, Offset
, Data64
.Uint32
.Lower32
);
2337 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_FBU
;
2338 AhciWriteReg (PciIo
, Offset
, Data64
.Uint32
.Upper32
);
2340 Data64
.Uint64
= (UINTN
) (AhciRegisters
->AhciCmdListPciAddr
);
2341 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_CLB
;
2342 AhciWriteReg (PciIo
, Offset
, Data64
.Uint32
.Lower32
);
2343 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_CLBU
;
2344 AhciWriteReg (PciIo
, Offset
, Data64
.Uint32
.Upper32
);
2346 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_CMD
;
2347 Data
= AhciReadReg (PciIo
, Offset
);
2348 if ((Data
& EFI_AHCI_PORT_CMD_CPD
) != 0) {
2349 AhciOrReg (PciIo
, Offset
, EFI_AHCI_PORT_CMD_POD
);
2352 if ((Capability
& EFI_AHCI_CAP_SSS
) != 0) {
2353 AhciOrReg (PciIo
, Offset
, EFI_AHCI_PORT_CMD_SUD
);
2357 // Disable aggressive power management.
2359 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_SCTL
;
2360 AhciOrReg (PciIo
, Offset
, EFI_AHCI_PORT_SCTL_IPM_INIT
);
2362 // Disable the reporting of the corresponding interrupt to system software.
2364 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_IE
;
2365 AhciAndReg (PciIo
, Offset
, 0);
2368 // Now inform the IDE Controller Init Module.
2370 IdeInit
->NotifyPhase (IdeInit
, EfiIdeBusBeforeDevicePresenceDetection
, Port
);
2373 // Enable FIS Receive DMA engine for the first D2H FIS.
2375 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_CMD
;
2376 AhciOrReg (PciIo
, Offset
, EFI_AHCI_PORT_CMD_FRE
);
2379 // Wait for the Phy to detect the presence of a device.
2381 PhyDetectDelay
= EFI_AHCI_BUS_PHY_DETECT_TIMEOUT
;
2382 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_SSTS
;
2384 Data
= AhciReadReg (PciIo
, Offset
) & EFI_AHCI_PORT_SSTS_DET_MASK
;
2385 if ((Data
== EFI_AHCI_PORT_SSTS_DET_PCE
) || (Data
== EFI_AHCI_PORT_SSTS_DET
)) {
2389 MicroSecondDelay (1000);
2391 } while (PhyDetectDelay
> 0);
2393 if (PhyDetectDelay
== 0) {
2395 // No device detected at this port.
2396 // Clear PxCMD.SUD for those ports at which there are no device present.
2398 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_CMD
;
2399 AhciAndReg (PciIo
, Offset
, (UINT32
) ~(EFI_AHCI_PORT_CMD_SUD
));
2404 // According to SATA1.0a spec section 5.2, we need to wait for PxTFD.BSY and PxTFD.DRQ
2405 // and PxTFD.ERR to be zero. The maximum wait time is 16s which is defined at ATA spec.
2407 PhyDetectDelay
= 16 * 1000;
2409 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_SERR
;
2410 if (AhciReadReg(PciIo
, Offset
) != 0) {
2411 AhciWriteReg (PciIo
, Offset
, AhciReadReg(PciIo
, Offset
));
2413 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_TFD
;
2415 Data
= AhciReadReg (PciIo
, Offset
) & EFI_AHCI_PORT_TFD_MASK
;
2420 MicroSecondDelay (1000);
2422 } while (PhyDetectDelay
> 0);
2424 if (PhyDetectDelay
== 0) {
2425 DEBUG ((EFI_D_ERROR
, "Port %d Device presence detected but phy not ready (TFD=0x%X)\n", Port
, Data
));
2430 // When the first D2H register FIS is received, the content of PxSIG register is updated.
2432 Offset
= EFI_AHCI_PORT_START
+ Port
* EFI_AHCI_PORT_REG_WIDTH
+ EFI_AHCI_PORT_SIG
;
2433 Status
= AhciWaitMmioSet (
2438 EFI_TIMER_PERIOD_SECONDS(16)
2440 if (EFI_ERROR (Status
)) {
2444 Data
= AhciReadReg (PciIo
, Offset
);
2445 if ((Data
& EFI_AHCI_ATAPI_SIG_MASK
) == EFI_AHCI_ATAPI_DEVICE_SIG
) {
2446 Status
= AhciIdentifyPacket (PciIo
, AhciRegisters
, Port
, 0, &Buffer
);
2448 if (EFI_ERROR (Status
)) {
2452 DeviceType
= EfiIdeCdrom
;
2453 } else if ((Data
& EFI_AHCI_ATAPI_SIG_MASK
) == EFI_AHCI_ATA_DEVICE_SIG
) {
2454 Status
= AhciIdentify (PciIo
, AhciRegisters
, Port
, 0, &Buffer
);
2456 if (EFI_ERROR (Status
)) {
2457 REPORT_STATUS_CODE (EFI_PROGRESS_CODE
, (EFI_PERIPHERAL_FIXED_MEDIA
| EFI_P_EC_NOT_DETECTED
));
2461 DeviceType
= EfiIdeHarddisk
;
2465 DEBUG ((EFI_D_INFO
, "port [%d] port mulitplier [%d] has a [%a]\n",
2466 Port
, 0, DeviceType
== EfiIdeCdrom
? "cdrom" : "harddisk"));
2469 // If the device is a hard disk, then try to enable S.M.A.R.T feature
2471 if ((DeviceType
== EfiIdeHarddisk
) && PcdGetBool (PcdAtaSmartEnable
)) {
2472 AhciAtaSmartSupport (
2483 // Submit identify data to IDE controller init driver
2485 IdeInit
->SubmitData (IdeInit
, Port
, 0, &Buffer
);
2488 // Now start to config ide device parameter and transfer mode.
2490 Status
= IdeInit
->CalculateMode (
2496 if (EFI_ERROR (Status
)) {
2497 DEBUG ((EFI_D_ERROR
, "Calculate Mode Fail, Status = %r\n", Status
));
2502 // Set best supported PIO mode on this IDE device
2504 if (SupportedModes
->PioMode
.Mode
<= EfiAtaPioMode2
) {
2505 TransferMode
.ModeCategory
= EFI_ATA_MODE_DEFAULT_PIO
;
2507 TransferMode
.ModeCategory
= EFI_ATA_MODE_FLOW_PIO
;
2510 TransferMode
.ModeNumber
= (UINT8
) (SupportedModes
->PioMode
.Mode
);
2513 // Set supported DMA mode on this IDE device. Note that UDMA & MDMA cann't
2514 // be set together. Only one DMA mode can be set to a device. If setting
2515 // DMA mode operation fails, we can continue moving on because we only use
2516 // PIO mode at boot time. DMA modes are used by certain kind of OS booting
2518 if (SupportedModes
->UdmaMode
.Valid
) {
2519 TransferMode
.ModeCategory
= EFI_ATA_MODE_UDMA
;
2520 TransferMode
.ModeNumber
= (UINT8
) (SupportedModes
->UdmaMode
.Mode
);
2521 } else if (SupportedModes
->MultiWordDmaMode
.Valid
) {
2522 TransferMode
.ModeCategory
= EFI_ATA_MODE_MDMA
;
2523 TransferMode
.ModeNumber
= (UINT8
) SupportedModes
->MultiWordDmaMode
.Mode
;
2526 Status
= AhciDeviceSetFeature (PciIo
, AhciRegisters
, Port
, 0, 0x03, (UINT32
)(*(UINT8
*)&TransferMode
));
2527 if (EFI_ERROR (Status
)) {
2528 DEBUG ((EFI_D_ERROR
, "Set transfer Mode Fail, Status = %r\n", Status
));
2533 // Found a ATA or ATAPI device, add it into the device list.
2535 CreateNewDeviceInfo (Instance
, Port
, 0xFFFF, DeviceType
, &Buffer
);
2536 if (DeviceType
== EfiIdeHarddisk
) {
2537 REPORT_STATUS_CODE (EFI_PROGRESS_CODE
, (EFI_PERIPHERAL_FIXED_MEDIA
| EFI_P_PC_ENABLE
));