2 Header file for AHCI mode of ATA host controller.
4 Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #ifndef __ATA_HC_AHCI_MODE_H__
15 #define __ATA_HC_AHCI_MODE_H__
17 #define EFI_AHCI_BAR_INDEX 0x05
19 #define EFI_AHCI_CAPABILITY_OFFSET 0x0000
20 #define EFI_AHCI_CAP_SAM BIT18
21 #define EFI_AHCI_CAP_SSS BIT27
22 #define EFI_AHCI_CAP_S64A BIT31
23 #define EFI_AHCI_GHC_OFFSET 0x0004
24 #define EFI_AHCI_GHC_RESET BIT0
25 #define EFI_AHCI_GHC_IE BIT1
26 #define EFI_AHCI_GHC_ENABLE BIT31
27 #define EFI_AHCI_IS_OFFSET 0x0008
28 #define EFI_AHCI_PI_OFFSET 0x000C
30 #define EFI_AHCI_MAX_PORTS 32
43 // Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.
44 // Add a bit of margin for robustness.
46 #define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 15
48 // Refer SATA1.0a spec, the FIS enable time should be less than 500ms.
50 #define EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT EFI_TIMER_PERIOD_MILLISECONDS(500)
52 // Refer SATA1.0a spec, the bus reset time should be less than 1s.
54 #define EFI_AHCI_BUS_RESET_TIMEOUT EFI_TIMER_PERIOD_SECONDS(1)
56 #define EFI_AHCI_ATAPI_DEVICE_SIG 0xEB140000
57 #define EFI_AHCI_ATA_DEVICE_SIG 0x00000000
58 #define EFI_AHCI_PORT_MULTIPLIER_SIG 0x96690000
59 #define EFI_AHCI_ATAPI_SIG_MASK 0xFFFF0000
62 // Each PRDT entry can point to a memory block up to 4M byte
64 #define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000
66 #define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device
67 #define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20
68 #define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host
69 #define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20
70 #define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host
71 #define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4
72 #define EFI_AHCI_FIS_DMA_SETUP 0x41 //DMA Setup FIS - Bi-directional
73 #define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28
74 #define EFI_AHCI_FIS_DATA 0x46 //Data FIS - Bi-directional
75 #define EFI_AHCI_FIS_BIST 0x58 //BIST Activate FIS - Bi-directional
76 #define EFI_AHCI_FIS_BIST_LENGTH 12
77 #define EFI_AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host
78 #define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20
79 #define EFI_AHCI_FIS_SET_DEVICE 0xA1 //Set Device Bits FIS - Device to Host
80 #define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8
82 #define EFI_AHCI_D2H_FIS_OFFSET 0x40
83 #define EFI_AHCI_DMA_FIS_OFFSET 0x00
84 #define EFI_AHCI_PIO_FIS_OFFSET 0x20
85 #define EFI_AHCI_SDB_FIS_OFFSET 0x58
86 #define EFI_AHCI_FIS_TYPE_MASK 0xFF
87 #define EFI_AHCI_U_FIS_OFFSET 0x60
92 #define EFI_AHCI_PORT_START 0x0100
93 #define EFI_AHCI_PORT_REG_WIDTH 0x0080
94 #define EFI_AHCI_PORT_CLB 0x0000
95 #define EFI_AHCI_PORT_CLBU 0x0004
96 #define EFI_AHCI_PORT_FB 0x0008
97 #define EFI_AHCI_PORT_FBU 0x000C
98 #define EFI_AHCI_PORT_IS 0x0010
99 #define EFI_AHCI_PORT_IS_DHRS BIT0
100 #define EFI_AHCI_PORT_IS_PSS BIT1
101 #define EFI_AHCI_PORT_IS_SSS BIT2
102 #define EFI_AHCI_PORT_IS_SDBS BIT3
103 #define EFI_AHCI_PORT_IS_UFS BIT4
104 #define EFI_AHCI_PORT_IS_DPS BIT5
105 #define EFI_AHCI_PORT_IS_PCS BIT6
106 #define EFI_AHCI_PORT_IS_DIS BIT7
107 #define EFI_AHCI_PORT_IS_PRCS BIT22
108 #define EFI_AHCI_PORT_IS_IPMS BIT23
109 #define EFI_AHCI_PORT_IS_OFS BIT24
110 #define EFI_AHCI_PORT_IS_INFS BIT26
111 #define EFI_AHCI_PORT_IS_IFS BIT27
112 #define EFI_AHCI_PORT_IS_HBDS BIT28
113 #define EFI_AHCI_PORT_IS_HBFS BIT29
114 #define EFI_AHCI_PORT_IS_TFES BIT30
115 #define EFI_AHCI_PORT_IS_CPDS BIT31
116 #define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF
117 #define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F
119 #define EFI_AHCI_PORT_IE 0x0014
120 #define EFI_AHCI_PORT_CMD 0x0018
121 #define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE
122 #define EFI_AHCI_PORT_CMD_ST BIT0
123 #define EFI_AHCI_PORT_CMD_SUD BIT1
124 #define EFI_AHCI_PORT_CMD_POD BIT2
125 #define EFI_AHCI_PORT_CMD_CLO BIT3
126 #define EFI_AHCI_PORT_CMD_CR BIT15
127 #define EFI_AHCI_PORT_CMD_FRE BIT4
128 #define EFI_AHCI_PORT_CMD_FR BIT14
129 #define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)
130 #define EFI_AHCI_PORT_CMD_PMA BIT17
131 #define EFI_AHCI_PORT_CMD_HPCP BIT18
132 #define EFI_AHCI_PORT_CMD_MPSP BIT19
133 #define EFI_AHCI_PORT_CMD_CPD BIT20
134 #define EFI_AHCI_PORT_CMD_ESP BIT21
135 #define EFI_AHCI_PORT_CMD_ATAPI BIT24
136 #define EFI_AHCI_PORT_CMD_DLAE BIT25
137 #define EFI_AHCI_PORT_CMD_ALPE BIT26
138 #define EFI_AHCI_PORT_CMD_ASP BIT27
139 #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
140 #define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 )
141 #define EFI_AHCI_PORT_TFD 0x0020
142 #define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)
143 #define EFI_AHCI_PORT_TFD_BSY BIT7
144 #define EFI_AHCI_PORT_TFD_DRQ BIT3
145 #define EFI_AHCI_PORT_TFD_ERR BIT0
146 #define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00
147 #define EFI_AHCI_PORT_SIG 0x0024
148 #define EFI_AHCI_PORT_SSTS 0x0028
149 #define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F
150 #define EFI_AHCI_PORT_SSTS_DET 0x0001
151 #define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003
152 #define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0
153 #define EFI_AHCI_PORT_SCTL 0x002C
154 #define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F
155 #define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK)
156 #define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001
157 #define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003
158 #define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0
159 #define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00
160 #define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300
161 #define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100
162 #define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200
163 #define EFI_AHCI_PORT_SERR 0x0030
164 #define EFI_AHCI_PORT_SERR_RDIE BIT0
165 #define EFI_AHCI_PORT_SERR_RCE BIT1
166 #define EFI_AHCI_PORT_SERR_TDIE BIT8
167 #define EFI_AHCI_PORT_SERR_PCDIE BIT9
168 #define EFI_AHCI_PORT_SERR_PE BIT10
169 #define EFI_AHCI_PORT_SERR_IE BIT11
170 #define EFI_AHCI_PORT_SERR_PRC BIT16
171 #define EFI_AHCI_PORT_SERR_PIE BIT17
172 #define EFI_AHCI_PORT_SERR_CW BIT18
173 #define EFI_AHCI_PORT_SERR_BDE BIT19
174 #define EFI_AHCI_PORT_SERR_DE BIT20
175 #define EFI_AHCI_PORT_SERR_CRCE BIT21
176 #define EFI_AHCI_PORT_SERR_HE BIT22
177 #define EFI_AHCI_PORT_SERR_LSE BIT23
178 #define EFI_AHCI_PORT_SERR_TSTE BIT24
179 #define EFI_AHCI_PORT_SERR_UFT BIT25
180 #define EFI_AHCI_PORT_SERR_EX BIT26
181 #define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF
182 #define EFI_AHCI_PORT_SACT 0x0034
183 #define EFI_AHCI_PORT_CI 0x0038
184 #define EFI_AHCI_PORT_SNTF 0x003C
189 // Command List structure includes total 32 entries.
190 // The entry data structure is listed at the following.
193 UINT32 AhciCmdCfl
:5; //Command FIS Length
194 UINT32 AhciCmdA
:1; //ATAPI
195 UINT32 AhciCmdW
:1; //Write
196 UINT32 AhciCmdP
:1; //Prefetchable
197 UINT32 AhciCmdR
:1; //Reset
198 UINT32 AhciCmdB
:1; //BIST
199 UINT32 AhciCmdC
:1; //Clear Busy upon R_OK
200 UINT32 AhciCmdRsvd
:1;
201 UINT32 AhciCmdPmp
:4; //Port Multiplier Port
202 UINT32 AhciCmdPrdtl
:16; //Physical Region Descriptor Table Length
203 UINT32 AhciCmdPrdbc
; //Physical Region Descriptor Byte Count
204 UINT32 AhciCmdCtba
; //Command Table Descriptor Base Address
205 UINT32 AhciCmdCtbau
; //Command Table Descriptor Base Address Upper 32-BITs
206 UINT32 AhciCmdRsvd1
[4];
207 } EFI_AHCI_COMMAND_LIST
;
210 // This is a software constructed FIS.
211 // For data transfer operations, this is the H2D Register FIS format as
212 // specified in the Serial ATA Revision 2.6 specification.
216 UINT8 AhciCFisPmNum
:4;
217 UINT8 AhciCFisRsvd
:1;
218 UINT8 AhciCFisRsvd1
:1;
219 UINT8 AhciCFisRsvd2
:1;
220 UINT8 AhciCFisCmdInd
:1;
222 UINT8 AhciCFisFeature
;
223 UINT8 AhciCFisSecNum
;
224 UINT8 AhciCFisClyLow
;
225 UINT8 AhciCFisClyHigh
;
226 UINT8 AhciCFisDevHead
;
227 UINT8 AhciCFisSecNumExp
;
228 UINT8 AhciCFisClyLowExp
;
229 UINT8 AhciCFisClyHighExp
;
230 UINT8 AhciCFisFeatureExp
;
231 UINT8 AhciCFisSecCount
;
232 UINT8 AhciCFisSecCountExp
;
234 UINT8 AhciCFisControl
;
235 UINT8 AhciCFisRsvd4
[4];
236 UINT8 AhciCFisRsvd5
[44];
237 } EFI_AHCI_COMMAND_FIS
;
240 // ACMD: ATAPI command (12 or 16 bytes)
243 UINT8 AtapiCmd
[0x10];
244 } EFI_AHCI_ATAPI_COMMAND
;
247 // Physical Region Descriptor Table includes up to 65535 entries
248 // The entry data structure is listed at the following.
249 // the actual entry number comes from the PRDTL field in the command
250 // list entry for this command slot.
253 UINT32 AhciPrdtDba
; //Data Base Address
254 UINT32 AhciPrdtDbau
; //Data Base Address Upper 32-BITs
256 UINT32 AhciPrdtDbc
:22; //Data Byte Count
257 UINT32 AhciPrdtRsvd1
:9;
258 UINT32 AhciPrdtIoc
:1; //Interrupt on Completion
259 } EFI_AHCI_COMMAND_PRDT
;
262 // Command table data strucute which is pointed to by the entry in the command list
265 EFI_AHCI_COMMAND_FIS CommandFis
; // A software constructed FIS.
266 EFI_AHCI_ATAPI_COMMAND AtapiCmd
; // 12 or 16 bytes ATAPI cmd.
267 UINT8 Reserved
[0x30];
268 EFI_AHCI_COMMAND_PRDT PrdtTable
[65535]; // The scatter/gather list for data transfer
269 } EFI_AHCI_COMMAND_TABLE
;
272 // Received FIS structure
275 UINT8 AhciDmaSetupFis
[0x1C]; // Dma Setup Fis: offset 0x00
276 UINT8 AhciDmaSetupFisRsvd
[0x04];
277 UINT8 AhciPioSetupFis
[0x14]; // Pio Setup Fis: offset 0x20
278 UINT8 AhciPioSetupFisRsvd
[0x0C];
279 UINT8 AhciD2HRegisterFis
[0x14]; // D2H Register Fis: offset 0x40
280 UINT8 AhciD2HRegisterFisRsvd
[0x04];
281 UINT64 AhciSetDeviceBitsFis
; // Set Device Bits Fix: offset 0x58
282 UINT8 AhciUnknownFis
[0x40]; // Unkonwn Fis: offset 0x60
283 UINT8 AhciUnknownFisRsvd
[0x60];
284 } EFI_AHCI_RECEIVED_FIS
;
289 EFI_AHCI_RECEIVED_FIS
*AhciRFis
;
290 EFI_AHCI_COMMAND_LIST
*AhciCmdList
;
291 EFI_AHCI_COMMAND_TABLE
*AhciCommandTable
;
292 EFI_AHCI_RECEIVED_FIS
*AhciRFisPciAddr
;
293 EFI_AHCI_COMMAND_LIST
*AhciCmdListPciAddr
;
294 EFI_AHCI_COMMAND_TABLE
*AhciCommandTablePciAddr
;
295 UINT64 MaxCommandListSize
;
296 UINT64 MaxCommandTableSize
;
297 UINT64 MaxReceiveFisSize
;
300 VOID
*MapCommandTable
;
301 } EFI_AHCI_REGISTERS
;
304 This function is used to send out ATAPI commands conforms to the Packet Command
307 @param PciIo The PCI IO protocol instance.
308 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
309 @param Port The number of port.
310 @param PortMultiplier The number of port multiplier.
311 @param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
313 @retval EFI_SUCCESS send out the ATAPI packet command successfully
314 and device sends data successfully.
315 @retval EFI_DEVICE_ERROR the device failed to send data.
320 AhciPacketCommandExecute (
321 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
322 IN EFI_AHCI_REGISTERS
*AhciRegisters
,
324 IN UINT8 PortMultiplier
,
325 IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET
*Packet
329 Start command for give slot on specific port.
331 @param PciIo The PCI IO protocol instance.
332 @param Port The number of port.
333 @param CommandSlot The number of CommandSlot.
334 @param Timeout The timeout value of start, uses 100ns as a unit.
336 @retval EFI_DEVICE_ERROR The command start unsuccessfully.
337 @retval EFI_TIMEOUT The operation is time out.
338 @retval EFI_SUCCESS The command start successfully.
344 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
346 IN UINT8 CommandSlot
,
351 Stop command running for giving port
353 @param PciIo The PCI IO protocol instance.
354 @param Port The number of port.
355 @param Timeout The timeout value of stop, uses 100ns as a unit.
357 @retval EFI_DEVICE_ERROR The command stop unsuccessfully.
358 @retval EFI_TIMEOUT The operation is time out.
359 @retval EFI_SUCCESS The command stop successfully.
365 IN EFI_PCI_IO_PROTOCOL
*PciIo
,