MdeModulePkg/Bus/Ata/AtaAtapiPassThru/IdeMode.h

   1 /** @file
   2   Header file for IDE mode of ATA host controller.
   3
   4   Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8 #ifndef __ATA_HC_IDE_MODE_H__
   9 #define __ATA_HC_IDE_MODE_H__
  10
  11 typedef enum {
  12   EfiIdePrimary    = 0,
  13   EfiIdeSecondary  = 1,
  14   EfiIdeMaxChannel = 2
  15 } EFI_IDE_CHANNEL;
  16
  17 typedef enum {
  18   EfiIdeMaster    = 0,
  19   EfiIdeSlave     = 1,
  20   EfiIdeMaxDevice = 2
  21 } EFI_IDE_DEVICE;
  22
  23 ///
  24 /// PIO mode definition
  25 ///
  26 typedef enum {
  27   EfiAtaPioModeBelow2,
  28   EfiAtaPioMode2,
  29   EfiAtaPioMode3,
  30   EfiAtaPioMode4
  31 } EFI_ATA_PIO_MODE;
  32
  33 //
  34 // Multi word DMA definition
  35 //
  36 typedef enum {
  37   EfiAtaMdmaMode0,
  38   EfiAtaMdmaMode1,
  39   EfiAtaMdmaMode2
  40 } EFI_ATA_MDMA_MODE;
  41
  42 //
  43 // UDMA mode definition
  44 //
  45 typedef enum {
  46   EfiAtaUdmaMode0,
  47   EfiAtaUdmaMode1,
  48   EfiAtaUdmaMode2,
  49   EfiAtaUdmaMode3,
  50   EfiAtaUdmaMode4,
  51   EfiAtaUdmaMode5
  52 } EFI_ATA_UDMA_MODE;
  53
  54 //
  55 // Bus Master Reg
  56 //
  57 #define BMIC_NREAD      BIT3
  58 #define BMIC_START      BIT0
  59 #define BMIS_INTERRUPT  BIT2
  60 #define BMIS_ERROR      BIT1
  61
  62 #define BMIC_OFFSET    0x00
  63 #define BMIS_OFFSET    0x02
  64 #define BMID_OFFSET    0x04
  65
  66 //
  67 // IDE transfer mode
  68 //
  69 #define EFI_ATA_MODE_DEFAULT_PIO 0x00
  70 #define EFI_ATA_MODE_FLOW_PIO    0x01
  71 #define EFI_ATA_MODE_MDMA        0x04
  72 #define EFI_ATA_MODE_UDMA        0x08
  73
  74 typedef struct {
  75   UINT32  RegionBaseAddr;
  76   UINT16  ByteCount;
  77   UINT16  EndOfTable;
  78 } EFI_ATA_DMA_PRD;
  79
  80 typedef struct {
  81   UINT8 ModeNumber   : 3;
  82   UINT8 ModeCategory : 5;
  83 } EFI_ATA_TRANSFER_MODE;
  84
  85 typedef struct {
  86   UINT8 Sector;
  87   UINT8 Heads;
  88   UINT8 MultipleSector;
  89 } EFI_ATA_DRIVE_PARMS;
  90
  91 //
  92 // IDE registers set
  93 //
  94 typedef struct {
  95   UINT16                          Data;
  96   UINT16                          ErrOrFeature;
  97   UINT16                          SectorCount;
  98   UINT16                          SectorNumber;
  99   UINT16                          CylinderLsb;
 100   UINT16                          CylinderMsb;
 101   UINT16                          Head;
 102   UINT16                          CmdOrStatus;
 103   UINT16                          AltOrDev;
 104
 105   UINT16                          BusMasterBaseAddr;
 106 } EFI_IDE_REGISTERS;
 107
 108 //
 109 // Bit definitions in Programming Interface byte of the Class Code field
 110 // in PCI IDE controller's Configuration Space
 111 //
 112 #define IDE_PRIMARY_OPERATING_MODE            BIT0
 113 #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR    BIT1
 114 #define IDE_SECONDARY_OPERATING_MODE          BIT2
 115 #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR  BIT3
 116
 117 /**
 118   Get IDE i/o port registers' base addresses by mode.
 119
 120   In 'Compatibility' mode, use fixed addresses.
 121   In Native-PCI mode, get base addresses from BARs in the PCI IDE controller's
 122   Configuration Space.
 123
 124   The steps to get IDE i/o port registers' base addresses for each channel
 125   as follows:
 126
 127   1. Examine the Programming Interface byte of the Class Code fields in PCI IDE
 128   controller's Configuration Space to determine the operating mode.
 129
 130   2. a) In 'Compatibility' mode, use fixed addresses shown in the Table 1 below.
 131    ___________________________________________
 132   |           | Command Block | Control Block |
 133   |  Channel  |   Registers   |   Registers   |
 134   |___________|_______________|_______________|
 135   |  Primary  |  1F0h - 1F7h  |  3F6h - 3F7h  |
 136   |___________|_______________|_______________|
 137   | Secondary |  170h - 177h  |  376h - 377h  |
 138   |___________|_______________|_______________|
 139
 140   Table 1. Compatibility resource mappings
 141
 142   b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs
 143   in IDE controller's PCI Configuration Space, shown in the Table 2 below.
 144    ___________________________________________________
 145   |           |   Command Block   |   Control Block   |
 146   |  Channel  |     Registers     |     Registers     |
 147   |___________|___________________|___________________|
 148   |  Primary  | BAR at offset 0x10| BAR at offset 0x14|
 149   |___________|___________________|___________________|
 150   | Secondary | BAR at offset 0x18| BAR at offset 0x1C|
 151   |___________|___________________|___________________|
 152
 153   Table 2. BARs for Register Mapping
 154
 155   @param[in]      PciIo          Pointer to the EFI_PCI_IO_PROTOCOL instance
 156   @param[in, out] IdeRegisters   Pointer to EFI_IDE_REGISTERS which is used to
 157                                  store the IDE i/o port registers' base addresses
 158
 159   @retval EFI_UNSUPPORTED        Return this value when the BARs is not IO type
 160   @retval EFI_SUCCESS            Get the Base address successfully
 161   @retval Other                  Read the pci configureation data error
 162
 163 **/
 164 EFI_STATUS
 165 EFIAPI
 166 GetIdeRegisterIoAddr (
 167   IN     EFI_PCI_IO_PROTOCOL         *PciIo,
 168   IN OUT EFI_IDE_REGISTERS           *IdeRegisters
 169   );
 170
 171 /**
 172   This function is used to send out ATAPI commands conforms to the Packet Command
 173   with PIO Data In Protocol.
 174
 175   @param[in] PciIo          Pointer to the EFI_PCI_IO_PROTOCOL instance
 176   @param[in] IdeRegisters   Pointer to EFI_IDE_REGISTERS which is used to
 177                             store the IDE i/o port registers' base addresses
 178   @param[in] Channel        The channel number of device.
 179   @param[in] Device         The device number of device.
 180   @param[in] Packet         A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET data structure.
 181
 182   @retval EFI_SUCCESS       send out the ATAPI packet command successfully
 183                             and device sends data successfully.
 184   @retval EFI_DEVICE_ERROR  the device failed to send data.
 185
 186 **/
 187 EFI_STATUS
 188 EFIAPI
 189 AtaPacketCommandExecute (
 190   IN  EFI_PCI_IO_PROTOCOL                           *PciIo,
 191   IN  EFI_IDE_REGISTERS                             *IdeRegisters,
 192   IN  UINT8                                         Channel,
 193   IN  UINT8                                         Device,
 194   IN  EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET    *Packet
 195   );
 196
 197 #endif
 198