MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h

   1 /** @file
   2
   3   This file contains the definination for host controller register operation routines.
   4
   5 Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _EFI_EHCI_REG_H_
  17 #define _EFI_EHCI_REG_H_
  18
  19 //
  20 // EHCI register offset
  21 //
  22
  23
  24 //
  25 // Capability register offset
  26 //
  27 #define EHC_CAPLENGTH_OFFSET    0    // Capability register length offset
  28 #define EHC_HCSPARAMS_OFFSET    0x04 // Structural Parameters 04-07h
  29 #define EHC_HCCPARAMS_OFFSET    0x08 // Capability parameters offset
  30
  31 //
  32 // Capability register bit definition
  33 //
  34 #define HCSP_NPORTS             0x0F // Number of root hub port
  35 #define HCSP_PPC                0x10 // Port Power Control
  36 #define HCCP_64BIT              0x01 // 64-bit addressing capability
  37
  38 //
  39 // Operational register offset
  40 //
  41 #define EHC_USBCMD_OFFSET       0x0  // USB command register offset
  42 #define EHC_USBSTS_OFFSET       0x04 // Statue register offset
  43 #define EHC_USBINTR_OFFSET      0x08 // USB interrutp offset
  44 #define EHC_FRINDEX_OFFSET      0x0C // Frame index offset
  45 #define EHC_CTRLDSSEG_OFFSET    0x10 // Control data structure segment offset
  46 #define EHC_FRAME_BASE_OFFSET   0x14 // Frame list base address offset
  47 #define EHC_ASYNC_HEAD_OFFSET   0x18 // Next asynchronous list address offset
  48 #define EHC_CONFIG_FLAG_OFFSET  0x40 // Configure flag register offset
  49 #define EHC_PORT_STAT_OFFSET    0x44 // Port status/control offset
  50
  51 #define EHC_FRAME_LEN           1024
  52
  53 //
  54 // Register bit definition
  55 //
  56 #define CONFIGFLAG_ROUTE_EHC    0x01 // Route port to EHC
  57
  58 #define USBCMD_RUN              0x01   // Run/stop
  59 #define USBCMD_RESET            0x02   // Start the host controller reset
  60 #define USBCMD_ENABLE_PERIOD    0x10   // Enable periodic schedule
  61 #define USBCMD_ENABLE_ASYNC     0x20   // Enable asynchronous schedule
  62 #define USBCMD_IAAD             0x40   // Interrupt on async advance doorbell
  63
  64 #define USBSTS_IAA              0x20   // Interrupt on async advance
  65 #define USBSTS_PERIOD_ENABLED   0x4000 // Periodic schedule status
  66 #define USBSTS_ASYNC_ENABLED    0x8000 // Asynchronous schedule status
  67 #define USBSTS_HALT             0x1000 // Host controller halted
  68 #define USBSTS_SYS_ERROR        0x10   // Host system error
  69 #define USBSTS_INTACK_MASK      0x003F // Mask for the interrupt ACK, the WC
  70                                        // (write clean) bits in USBSTS register
  71
  72 #define PORTSC_CONN             0x01   // Current Connect Status
  73 #define PORTSC_CONN_CHANGE      0x02   // Connect Status Change
  74 #define PORTSC_ENABLED          0x04   // Port Enable / Disable
  75 #define PORTSC_ENABLE_CHANGE    0x08   // Port Enable / Disable Change
  76 #define PORTSC_OVERCUR          0x10   // Over current Active
  77 #define PORTSC_OVERCUR_CHANGE   0x20   // Over current Change
  78 #define PORSTSC_RESUME          0x40   // Force Port Resume
  79 #define PORTSC_SUSPEND          0x80   // Port Suspend State
  80 #define PORTSC_RESET            0x100  // Port Reset
  81 #define PORTSC_LINESTATE_K      0x400  // Line Status K-state
  82 #define PORTSC_LINESTATE_J      0x800  // Line Status J-state
  83 #define PORTSC_POWER            0x1000 // Port Power
  84 #define PORTSC_OWNER            0x2000 // Port Owner
  85 #define PORTSC_CHANGE_MASK      0x2A   // Mask of the port change bits,
  86                                        // they are WC (write clean)
  87 //
  88 // PCI Configuration Registers
  89 //
  90 #define EHC_BAR_INDEX           0      // how many bytes away from USB_BASE to 0x10
  91
  92 //
  93 // Debug port capability id
  94 //
  95 #define EHC_DEBUG_PORT_CAP_ID   0x0A
  96
  97 #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
  98
  99 #define EHC_ADDR(High, QhHw32)   \
 100         ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
 101
 102 #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
 103
 104 //
 105 // Structure to map the hardware port states to the
 106 // UEFI's port states.
 107 //
 108 typedef struct {
 109   UINT16                  HwState;
 110   UINT16                  UefiState;
 111 } USB_PORT_STATE_MAP;
 112
 113 //
 114 // Ehci Data and Ctrl Structures
 115 //
 116 #pragma pack(1)
 117 typedef struct {
 118   UINT8                   ProgInterface;
 119   UINT8                   SubClassCode;
 120   UINT8                   BaseCode;
 121 } USB_CLASSC;
 122 #pragma pack()
 123
 124 /**
 125   Read EHCI capability register.
 126
 127   @param  Ehc     The EHCI device.
 128   @param  Offset  Capability register address.
 129
 130   @return The register content.
 131
 132 **/
 133 UINT32
 134 EhcReadCapRegister (
 135   IN  USB2_HC_DEV         *Ehc,
 136   IN  UINT32              Offset
 137   );
 138
 139 /**
 140   Check whether the host controller has an in-use debug port.
 141
 142   @param[in] Ehc         The Enhanced Host Controller to query.
 143
 144   @param[in] PortNumber  If PortNumber is not NULL, then query whether
 145                          PortNumber is an in-use debug port on Ehc. (PortNumber
 146                          is taken in UEFI notation, i.e., zero-based.)
 147                          Otherwise, query whether Ehc has any in-use debug
 148                          port.
 149
 150   @retval TRUE   PortNumber is an in-use debug port on Ehc (if PortNumber is
 151                  not NULL), or some port on Ehc is an in-use debug port
 152                  (otherwise).
 153
 154   @retval FALSE  PortNumber is not an in-use debug port on Ehc (if PortNumber
 155                  is not NULL), or no port on Ehc is an in-use debug port
 156                  (otherwise).
 157 **/
 158 BOOLEAN
 159 EhcIsDebugPortInUse (
 160   IN CONST USB2_HC_DEV *Ehc,
 161   IN CONST UINT8       *PortNumber OPTIONAL
 162   );
 163
 164 /**
 165   Read EHCI Operation register.
 166
 167   @param  Ehc      The EHCI device.
 168   @param  Offset   The operation register offset.
 169
 170   @return The register content.
 171
 172 **/
 173 UINT32
 174 EhcReadOpReg (
 175   IN  USB2_HC_DEV         *Ehc,
 176   IN  UINT32              Offset
 177   );
 178
 179
 180 /**
 181   Write  the data to the EHCI operation register.
 182
 183   @param  Ehc      The EHCI device.
 184   @param  Offset   EHCI operation register offset.
 185   @param  Data     The data to write.
 186
 187 **/
 188 VOID
 189 EhcWriteOpReg (
 190   IN USB2_HC_DEV          *Ehc,
 191   IN UINT32               Offset,
 192   IN UINT32               Data
 193   );
 194
 195 /**
 196   Set one bit of the operational register while keeping other bits.
 197
 198   @param  Ehc          The EHCI device.
 199   @param  Offset       The offset of the operational register.
 200   @param  Bit          The bit mask of the register to set.
 201
 202 **/
 203 VOID
 204 EhcSetOpRegBit (
 205   IN USB2_HC_DEV          *Ehc,
 206   IN UINT32               Offset,
 207   IN UINT32               Bit
 208   );
 209
 210 /**
 211   Clear one bit of the operational register while keeping other bits.
 212
 213   @param  Ehc          The EHCI device.
 214   @param  Offset       The offset of the operational register.
 215   @param  Bit          The bit mask of the register to clear.
 216
 217 **/
 218 VOID
 219 EhcClearOpRegBit (
 220   IN USB2_HC_DEV          *Ehc,
 221   IN UINT32               Offset,
 222   IN UINT32               Bit
 223   );
 224
 225 /**
 226   Add support for UEFI Over Legacy (UoL) feature, stop
 227   the legacy USB SMI support.
 228
 229   @param  Ehc      The EHCI device.
 230
 231 **/
 232 VOID
 233 EhcClearLegacySupport (
 234   IN USB2_HC_DEV          *Ehc
 235   );
 236
 237
 238
 239 /**
 240   Set door bell and wait it to be ACKed by host controller.
 241   This function is used to synchronize with the hardware.
 242
 243   @param  Ehc          The EHCI device.
 244   @param  Timeout      The time to wait before abort (in millisecond, ms).
 245
 246   @retval EFI_SUCCESS  Synchronized with the hardware.
 247   @retval EFI_TIMEOUT  Time out happened while waiting door bell to set.
 248
 249 **/
 250 EFI_STATUS
 251 EhcSetAndWaitDoorBell (
 252   IN  USB2_HC_DEV         *Ehc,
 253   IN  UINT32               Timeout
 254   );
 255
 256
 257 /**
 258   Clear all the interrutp status bits, these bits are Write-Clean.
 259
 260   @param  Ehc      The EHCI device.
 261
 262 **/
 263 VOID
 264 EhcAckAllInterrupt (
 265   IN  USB2_HC_DEV         *Ehc
 266   );
 267
 268
 269
 270 /**
 271   Whether Ehc is halted.
 272
 273   @param  Ehc     The EHCI device.
 274
 275   @retval TRUE    The controller is halted.
 276   @retval FALSE   It isn't halted.
 277
 278 **/
 279 BOOLEAN
 280 EhcIsHalt (
 281   IN USB2_HC_DEV          *Ehc
 282   );
 283
 284
 285 /**
 286   Whether system error occurred.
 287
 288   @param  Ehc      The EHCI device.
 289
 290   @retval TRUE     System error happened.
 291   @retval FALSE    No system error.
 292
 293 **/
 294 BOOLEAN
 295 EhcIsSysError (
 296   IN USB2_HC_DEV          *Ehc
 297   );
 298
 299
 300 /**
 301   Reset the host controller.
 302
 303   @param  Ehc          The EHCI device.
 304   @param  Timeout      Time to wait before abort (in millisecond, ms).
 305
 306   @retval EFI_SUCCESS  The host controller is reset.
 307   @return Others       Failed to reset the host.
 308
 309 **/
 310 EFI_STATUS
 311 EhcResetHC (
 312   IN USB2_HC_DEV          *Ehc,
 313   IN UINT32               Timeout
 314   );
 315
 316
 317 /**
 318   Halt the host controller.
 319
 320   @param  Ehc          The EHCI device.
 321   @param  Timeout      Time to wait before abort.
 322
 323   @return EFI_SUCCESS  The EHCI is halt.
 324   @return EFI_TIMEOUT  Failed to halt the controller before Timeout.
 325
 326 **/
 327 EFI_STATUS
 328 EhcHaltHC (
 329   IN USB2_HC_DEV         *Ehc,
 330   IN UINT32              Timeout
 331   );
 332
 333
 334 /**
 335   Set the EHCI to run.
 336
 337   @param  Ehc          The EHCI device.
 338   @param  Timeout      Time to wait before abort.
 339
 340   @return EFI_SUCCESS  The EHCI is running.
 341   @return Others       Failed to set the EHCI to run.
 342
 343 **/
 344 EFI_STATUS
 345 EhcRunHC (
 346   IN USB2_HC_DEV          *Ehc,
 347   IN UINT32               Timeout
 348   );
 349
 350
 351
 352 /**
 353   Initialize the HC hardware.
 354   EHCI spec lists the five things to do to initialize the hardware:
 355   1. Program CTRLDSSEGMENT
 356   2. Set USBINTR to enable interrupts
 357   3. Set periodic list base
 358   4. Set USBCMD, interrupt threshold, frame list size etc
 359   5. Write 1 to CONFIGFLAG to route all ports to EHCI
 360
 361   @param  Ehc          The EHCI device.
 362
 363   @return EFI_SUCCESS  The EHCI has come out of halt state.
 364   @return EFI_TIMEOUT  Time out happened.
 365
 366 **/
 367 EFI_STATUS
 368 EhcInitHC (
 369   IN USB2_HC_DEV          *Ehc
 370   );
 371
 372 #endif