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git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h
3 This file contains the definination for host controller register operation routines.
5 Copyright (c) 2007 - 2009, Intel Corporation
6 All rights reserved. This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #ifndef _EFI_EHCI_REG_H_
17 #define _EFI_EHCI_REG_H_
22 // Capability register offset
24 EHC_CAPLENGTH_OFFSET
= 0, // Capability register length offset
25 EHC_HCSPARAMS_OFFSET
= 0x04, // Structural Parameters 04-07h
26 EHC_HCCPARAMS_OFFSET
= 0x08, // Capability parameters offset
29 // Capability register bit definition
31 HCSP_NPORTS
= 0x0F, // Number of root hub port
32 HCCP_64BIT
= 0x01, // 64-bit addressing capability
35 // Operational register offset
37 EHC_USBCMD_OFFSET
= 0x0, // USB command register offset
38 EHC_USBSTS_OFFSET
= 0x04, // Statue register offset
39 EHC_USBINTR_OFFSET
= 0x08, // USB interrutp offset
40 EHC_FRINDEX_OFFSET
= 0x0C, // Frame index offset
41 EHC_CTRLDSSEG_OFFSET
= 0x10, // Control data structure segment offset
42 EHC_FRAME_BASE_OFFSET
= 0x14, // Frame list base address offset
43 EHC_ASYNC_HEAD_OFFSET
= 0x18, // Next asynchronous list address offset
44 EHC_CONFIG_FLAG_OFFSET
= 0x40, // Configure flag register offset
45 EHC_PORT_STAT_OFFSET
= 0x44, // Port status/control offset
50 // Register bit definition
52 CONFIGFLAG_ROUTE_EHC
= 0x01, // Route port to EHC
54 USBCMD_RUN
= 0x01, // Run/stop
55 USBCMD_RESET
= 0x02, // Start the host controller reset
56 USBCMD_ENABLE_PERIOD
= 0x10, // Enable periodic schedule
57 USBCMD_ENABLE_ASYNC
= 0x20, // Enable asynchronous schedule
58 USBCMD_IAAD
= 0x40, // Interrupt on async advance doorbell
60 USBSTS_IAA
= 0x20, // Interrupt on async advance
61 USBSTS_PERIOD_ENABLED
= 0x4000, // Periodic schedule status
62 USBSTS_ASYNC_ENABLED
= 0x8000, // Asynchronous schedule status
63 USBSTS_HALT
= 0x1000, // Host controller halted
64 USBSTS_SYS_ERROR
= 0x10, // Host system error
65 USBSTS_INTACK_MASK
= 0x003F, // Mask for the interrupt ACK, the WC
66 // (write clean) bits in USBSTS register
68 PORTSC_CONN
= 0x01, // Current Connect Status
69 PORTSC_CONN_CHANGE
= 0x02, // Connect Status Change
70 PORTSC_ENABLED
= 0x04, // Port Enable / Disable
71 PORTSC_ENABLE_CHANGE
= 0x08, // Port Enable / Disable Change
72 PORTSC_OVERCUR
= 0x10, // Over current Active
73 PORTSC_OVERCUR_CHANGE
= 0x20, // Over current Change
74 PORSTSC_RESUME
= 0x40, // Force Port Resume
75 PORTSC_SUSPEND
= 0x80, // Port Suspend State
76 PORTSC_RESET
= 0x100, // Port Reset
77 PORTSC_LINESTATE_K
= 0x400, // Line Status K-state
78 PORTSC_LINESTATE_J
= 0x800, // Line Status J-state
79 PORTSC_POWER
= 0x1000, // Port Power
80 PORTSC_OWNER
= 0x2000, // Port Owner
81 PORTSC_CHANGE_MASK
= 0x2A, // Mask of the port change bits,
82 // they are WC (write clean)
84 // PCI Configuration Registers
86 EHC_BAR_INDEX
= 0 /* how many bytes away from USB_BASE to 0x10 */
87 }EHCI_REGISTER_OFFSET
;
89 #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
91 #define EHC_ADDR(High, QhHw32) \
92 ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
94 #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
97 // Structure to map the hardware port states to the
98 // UEFI's port states.
103 } USB_PORT_STATE_MAP
;
106 // Ehci Data and Ctrl Structures
117 Read EHCI capability register.
119 @param Ehc The EHCI device.
120 @param Offset Capability register address.
122 @return The register content.
133 Read EHCI Operation register.
135 @param Ehc The EHCI device.
136 @param Offset The operation register offset.
138 @return The register content.
149 Write the data to the EHCI operation register.
151 @param Ehc The EHCI device.
152 @param Offset EHCI operation register offset.
153 @param Data The data to write.
164 Set one bit of the operational register while keeping other bits.
166 @param Ehc The EHCI device.
167 @param Offset The offset of the operational register.
168 @param Bit The bit mask of the register to set.
179 Clear one bit of the operational register while keeping other bits.
181 @param Ehc The EHCI device.
182 @param Offset The offset of the operational register.
183 @param Bit The bit mask of the register to clear.
194 Add support for UEFI Over Legacy (UoL) feature, stop
195 the legacy USB SMI support.
197 @param Ehc The EHCI device.
201 EhcClearLegacySupport (
208 Set door bell and wait it to be ACKed by host controller.
209 This function is used to synchronize with the hardware.
211 @param Ehc The EHCI device.
212 @param Timeout The time to wait before abort (in millisecond, ms).
214 @retval EFI_SUCCESS Synchronized with the hardware.
215 @retval EFI_TIMEOUT Time out happened while waiting door bell to set.
219 EhcSetAndWaitDoorBell (
226 Clear all the interrutp status bits, these bits are Write-Clean.
228 @param Ehc The EHCI device.
239 Whether Ehc is halted.
241 @param Ehc The EHCI device.
243 @retval TRUE The controller is halted.
244 @retval FALSE It isn't halted.
254 Whether system error occurred.
256 @param Ehc The EHCI device.
258 @retval TRUE System error happened.
259 @retval FALSE No system error.
269 Reset the host controller.
271 @param Ehc The EHCI device.
272 @param Timeout Time to wait before abort (in millisecond, ms).
274 @retval EFI_SUCCESS The host controller is reset.
275 @return Others Failed to reset the host.
286 Halt the host controller.
288 @param Ehc The EHCI device.
289 @param Timeout Time to wait before abort.
291 @return EFI_SUCCESS The EHCI is halt.
292 @return EFI_TIMEOUT Failed to halt the controller before Timeout.
305 @param Ehc The EHCI device.
306 @param Timeout Time to wait before abort.
308 @return EFI_SUCCESS The EHCI is running.
309 @return Others Failed to set the EHCI to run.
321 Initialize the HC hardware.
322 EHCI spec lists the five things to do to initialize the hardware:
323 1. Program CTRLDSSEGMENT
324 2. Set USBINTR to enable interrupts
325 3. Set periodic list base
326 4. Set USBCMD, interrupt threshold, frame list size etc
327 5. Write 1 to CONFIGFLAG to route all ports to EHCI
329 @param Ehc The EHCI device.
331 @return EFI_SUCCESS The EHCI has come out of halt state.
332 @return EFI_TIMEOUT Time out happened.