3 This file contains URB request, each request is warpped in a
4 URB (Usb Request Block).
6 Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 Create a single QTD to hold the data.
23 @param Ehc The EHCI device.
24 @param Data The cpu memory address of current data not associated with a QTD.
25 @param DataPhy The pci bus address of current data not associated with a QTD.
26 @param DataLen The length of the data.
27 @param PktId Packet ID to use in the QTD.
28 @param Toggle Data toggle to use in the QTD.
29 @param MaxPacket Maximu packet length of the endpoint.
31 @return Created QTD or NULL if failed to create one.
53 Qtd
= UsbHcAllocateMem (Ehc
->MemPool
, sizeof (EHC_QTD
));
59 Qtd
->Signature
= EHC_QTD_SIG
;
63 InitializeListHead (&Qtd
->QtdList
);
66 QtdHw
->NextQtd
= QTD_LINK (NULL
, TRUE
);
67 QtdHw
->AltNext
= QTD_LINK (NULL
, TRUE
);
68 QtdHw
->Status
= QTD_STAT_ACTIVE
;
70 QtdHw
->ErrCnt
= QTD_MAX_ERR
;
72 QtdHw
->TotalBytes
= 0;
73 QtdHw
->DataToggle
= Toggle
;
76 // Fill in the buffer points
81 for (Index
= 0; Index
<= QTD_MAX_BUFFER
; Index
++) {
83 // Set the buffer point (Check page 41 EHCI Spec 1.0). No need to
84 // compute the offset and clear Reserved fields. This is already
85 // done in the data point.
87 QtdHw
->Page
[Index
] = EHC_LOW_32BIT (DataPhy
);
88 QtdHw
->PageHigh
[Index
] = EHC_HIGH_32BIT (DataPhy
);
90 ThisBufLen
= QTD_BUF_LEN
- (EHC_LOW_32BIT (DataPhy
) & QTD_BUF_MASK
);
92 if (Len
+ ThisBufLen
>= DataLen
) {
99 DataPhy
+= ThisBufLen
;
103 // Need to fix the last pointer if the Qtd can't hold all the
104 // user's data to make sure that the length is in the unit of
105 // max packets. If it can hold all the data, there is no such
109 Len
= Len
- Len
% MaxPacket
;
112 QtdHw
->TotalBytes
= (UINT32
) Len
;
122 Initialize the queue head for interrupt transfer,
123 that is, initialize the following three fields:
124 1. SplitXState in the Status field
128 @param Ep The queue head's related endpoint.
129 @param QhHw The queue head to initialize.
139 // Because UEFI interface can't utilitize an endpoint with
140 // poll rate faster than 1ms, only need to set one bit in
141 // the queue head. simple. But it may be changed later. If
142 // sub-1ms interrupt is supported, need to update the S-Mask
145 if (Ep
->DevSpeed
== EFI_USB_SPEED_HIGH
) {
146 QhHw
->SMask
= QH_MICROFRAME_0
;
151 // For low/full speed device, the transfer must go through
152 // the split transaction. Need to update three fields
153 // 1. SplitXState in the status
154 // 2. Microframe S-Mask
155 // 3. Microframe C-Mask
156 // UEFI USB doesn't exercise admission control. It simplely
157 // schedule the high speed transactions in microframe 0, and
158 // full/low speed transactions at microframe 1. This also
159 // avoid the use of FSTN.
161 QhHw
->SMask
= QH_MICROFRAME_1
;
162 QhHw
->CMask
= QH_MICROFRAME_3
| QH_MICROFRAME_4
| QH_MICROFRAME_5
;
168 Allocate and initialize a EHCI queue head.
170 @param Ehci The EHCI device.
171 @param Ep The endpoint to create queue head for.
173 @return Created queue head or NULL if failed to create one.
178 IN USB2_HC_DEV
*Ehci
,
185 Qh
= UsbHcAllocateMem (Ehci
->MemPool
, sizeof (EHC_QH
));
191 Qh
->Signature
= EHC_QH_SIG
;
193 Qh
->Interval
= Ep
->PollRate
;
195 InitializeListHead (&Qh
->Qtds
);
198 QhHw
->HorizonLink
= QH_LINK (NULL
, 0, TRUE
);
199 QhHw
->DeviceAddr
= Ep
->DevAddr
;
201 QhHw
->EpNum
= Ep
->EpAddr
;
202 QhHw
->EpSpeed
= Ep
->DevSpeed
;
204 QhHw
->ReclaimHead
= 0;
205 QhHw
->MaxPacketLen
= (UINT32
) Ep
->MaxPacket
;
207 QhHw
->NakReload
= QH_NAK_RELOAD
;
208 QhHw
->HubAddr
= Ep
->HubAddr
;
209 QhHw
->PortNum
= Ep
->HubPort
;
210 QhHw
->Multiplier
= 1;
211 QhHw
->DataToggle
= Ep
->Toggle
;
213 if (Ep
->DevSpeed
!= EFI_USB_SPEED_HIGH
) {
214 QhHw
->Status
|= QTD_STAT_DO_SS
;
218 case EHC_CTRL_TRANSFER
:
220 // Special initialization for the control transfer:
221 // 1. Control transfer initialize data toggle from each QTD
222 // 2. Set the Control Endpoint Flag (C) for low/full speed endpoint.
226 if (Ep
->DevSpeed
!= EFI_USB_SPEED_HIGH
) {
231 case EHC_INT_TRANSFER_ASYNC
:
232 case EHC_INT_TRANSFER_SYNC
:
234 // Special initialization for the interrupt transfer
235 // to set the S-Mask and C-Mask
238 EhcInitIntQh (Ep
, QhHw
);
241 case EHC_BULK_TRANSFER
:
242 if ((Ep
->DevSpeed
== EFI_USB_SPEED_HIGH
) && (Ep
->Direction
== EfiUsbDataOut
)) {
243 QhHw
->Status
|= QTD_STAT_DO_PING
;
254 Convert the poll interval from application to that
255 be used by EHCI interface data structure. Only need
256 to get the max 2^n that is less than interval. UEFI
257 can't support high speed endpoint with a interval less
258 than 8 microframe because interval is specified in
259 the unit of ms (millisecond).
261 @param Interval The interval to convert.
263 @return The converted interval.
278 // Find the index (1 based) of the highest non-zero bit
282 while (Interval
!= 0) {
287 return (UINTN
)1 << (BitCount
- 1);
294 @param Ehc The EHCI device.
295 @param Qtds The list head of the QTD.
308 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, Qtds
) {
309 Qtd
= EFI_LIST_CONTAINER (Entry
, EHC_QTD
, QtdList
);
311 RemoveEntryList (&Qtd
->QtdList
);
312 UsbHcFreeMem (Ehc
->MemPool
, Qtd
, sizeof (EHC_QTD
));
318 Free an allocated URB. It is possible for it to be partially inited.
320 @param Ehc The EHCI device.
321 @param Urb The URB to free.
330 EFI_PCI_IO_PROTOCOL
*PciIo
;
334 if (Urb
->RequestPhy
!= NULL
) {
335 PciIo
->Unmap (PciIo
, Urb
->RequestMap
);
338 if (Urb
->DataMap
!= NULL
) {
339 PciIo
->Unmap (PciIo
, Urb
->DataMap
);
342 if (Urb
->Qh
!= NULL
) {
344 // Ensure that this queue head has been unlinked from the
345 // schedule data structures. Free all the associated QTDs
347 EhcFreeQtds (Ehc
, &Urb
->Qh
->Qtds
);
348 UsbHcFreeMem (Ehc
->MemPool
, Urb
->Qh
, sizeof (EHC_QH
));
356 Create a list of QTDs for the URB.
358 @param Ehc The EHCI device.
359 @param Urb The URB to create QTDs for.
361 @retval EFI_OUT_OF_RESOURCES Failed to allocate resource for QTD.
362 @retval EFI_SUCCESS The QTDs are allocated for the URB.
381 EFI_PHYSICAL_ADDRESS PhyAddr
;
383 ASSERT ((Urb
!= NULL
) && (Urb
->Qh
!= NULL
));
386 // EHCI follows the alternet next QTD pointer if it meets
387 // a short read and the AlterNext pointer is valid. UEFI
388 // EHCI driver should terminate the transfer except the
395 AlterNext
= QTD_LINK (NULL
, TRUE
);
397 PhyAddr
= UsbHcGetPciAddressForHostMem (Ehc
->MemPool
, Ehc
->ShortReadStop
, sizeof (EHC_QTD
));
398 if (Ep
->Direction
== EfiUsbDataIn
) {
399 AlterNext
= QTD_LINK (PhyAddr
, FALSE
);
403 // Build the Setup and status packets for control transfer
405 if (Urb
->Ep
.Type
== EHC_CTRL_TRANSFER
) {
406 Len
= sizeof (EFI_USB_DEVICE_REQUEST
);
407 Qtd
= EhcCreateQtd (Ehc
, (UINT8
*)Urb
->Request
, (UINT8
*)Urb
->RequestPhy
, Len
, QTD_PID_SETUP
, 0, Ep
->MaxPacket
);
410 return EFI_OUT_OF_RESOURCES
;
413 InsertTailList (&Qh
->Qtds
, &Qtd
->QtdList
);
416 // Create the status packet now. Set the AlterNext to it. So, when
417 // EHCI meets a short control read, it can resume at the status stage.
418 // Use the opposite direction of the data stage, or IN if there is
421 if (Ep
->Direction
== EfiUsbDataIn
) {
422 Pid
= QTD_PID_OUTPUT
;
427 StatusQtd
= EhcCreateQtd (Ehc
, NULL
, NULL
, 0, Pid
, 1, Ep
->MaxPacket
);
429 if (StatusQtd
== NULL
) {
433 if (Ep
->Direction
== EfiUsbDataIn
) {
434 PhyAddr
= UsbHcGetPciAddressForHostMem (Ehc
->MemPool
, StatusQtd
, sizeof (EHC_QTD
));
435 AlterNext
= QTD_LINK (PhyAddr
, FALSE
);
442 // Build the data packets for all the transfers
444 if (Ep
->Direction
== EfiUsbDataIn
) {
447 Pid
= QTD_PID_OUTPUT
;
453 while (Len
< Urb
->DataLen
) {
456 (UINT8
*) Urb
->Data
+ Len
,
457 (UINT8
*) Urb
->DataPhy
+ Len
,
468 Qtd
->QtdHw
.AltNext
= AlterNext
;
469 InsertTailList (&Qh
->Qtds
, &Qtd
->QtdList
);
472 // Switch the Toggle bit if odd number of packets are included in the QTD.
474 if (((Qtd
->DataLen
+ Ep
->MaxPacket
- 1) / Ep
->MaxPacket
) % 2) {
475 Toggle
= (UINT8
) (1 - Toggle
);
482 // Insert the status packet for control transfer
484 if (Ep
->Type
== EHC_CTRL_TRANSFER
) {
485 InsertTailList (&Qh
->Qtds
, &StatusQtd
->QtdList
);
489 // OK, all the QTDs needed are created. Now, fix the NextQtd point
491 EFI_LIST_FOR_EACH (Entry
, &Qh
->Qtds
) {
492 Qtd
= EFI_LIST_CONTAINER (Entry
, EHC_QTD
, QtdList
);
495 // break if it is the last entry on the list
497 if (Entry
->ForwardLink
== &Qh
->Qtds
) {
501 NextQtd
= EFI_LIST_CONTAINER (Entry
->ForwardLink
, EHC_QTD
, QtdList
);
502 PhyAddr
= UsbHcGetPciAddressForHostMem (Ehc
->MemPool
, NextQtd
, sizeof (EHC_QTD
));
503 Qtd
->QtdHw
.NextQtd
= QTD_LINK (PhyAddr
, FALSE
);
507 // Link the QTDs to the queue head
509 NextQtd
= EFI_LIST_CONTAINER (Qh
->Qtds
.ForwardLink
, EHC_QTD
, QtdList
);
510 PhyAddr
= UsbHcGetPciAddressForHostMem (Ehc
->MemPool
, NextQtd
, sizeof (EHC_QTD
));
511 Qh
->QhHw
.NextQtd
= QTD_LINK (PhyAddr
, FALSE
);
515 EhcFreeQtds (Ehc
, &Qh
->Qtds
);
516 return EFI_OUT_OF_RESOURCES
;
521 Create a new URB and its associated QTD.
523 @param Ehc The EHCI device.
524 @param DevAddr The device address.
525 @param EpAddr Endpoint addrress & its direction.
526 @param DevSpeed The device speed.
527 @param Toggle Initial data toggle to use.
528 @param MaxPacket The max packet length of the endpoint.
529 @param Hub The transaction translator to use.
530 @param Type The transaction type.
531 @param Request The standard USB request for control transfer.
532 @param Data The user data to transfer.
533 @param DataLen The length of data buffer.
534 @param Callback The function to call when data is transferred.
535 @param Context The context to the callback.
536 @param Interval The interval for interrupt transfer.
538 @return Created URB or NULL.
549 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR
*Hub
,
551 IN EFI_USB_DEVICE_REQUEST
*Request
,
554 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback
,
560 EFI_PHYSICAL_ADDRESS PhyAddr
;
561 EFI_PCI_IO_PROTOCOL_OPERATION MapOp
;
562 EFI_PCI_IO_PROTOCOL
*PciIo
;
568 Urb
= AllocateZeroPool (sizeof (URB
));
574 Urb
->Signature
= EHC_URB_SIG
;
575 InitializeListHead (&Urb
->UrbList
);
578 Ep
->DevAddr
= DevAddr
;
579 Ep
->EpAddr
= (UINT8
) (EpAddr
& 0x0F);
580 Ep
->Direction
= (((EpAddr
& 0x80) != 0) ? EfiUsbDataIn
: EfiUsbDataOut
);
581 Ep
->DevSpeed
= DevSpeed
;
582 Ep
->MaxPacket
= MaxPacket
;
587 if (DevSpeed
!= EFI_USB_SPEED_HIGH
) {
588 ASSERT (Hub
!= NULL
);
590 Ep
->HubAddr
= Hub
->TranslatorHubAddress
;
591 Ep
->HubPort
= Hub
->TranslatorPortNumber
;
596 Ep
->PollRate
= EhcConvertPollRate (Interval
);
598 Urb
->Request
= Request
;
600 Urb
->DataLen
= DataLen
;
601 Urb
->Callback
= Callback
;
602 Urb
->Context
= Context
;
605 Urb
->Qh
= EhcCreateQh (Ehc
, &Urb
->Ep
);
607 if (Urb
->Qh
== NULL
) {
612 // Map the request and user data
614 if (Request
!= NULL
) {
615 Len
= sizeof (EFI_USB_DEVICE_REQUEST
);
616 MapOp
= EfiPciIoOperationBusMasterRead
;
617 Status
= PciIo
->Map (PciIo
, MapOp
, Request
, &Len
, &PhyAddr
, &Map
);
619 if (EFI_ERROR (Status
) || (Len
!= sizeof (EFI_USB_DEVICE_REQUEST
))) {
623 Urb
->RequestPhy
= (VOID
*) ((UINTN
) PhyAddr
);
624 Urb
->RequestMap
= Map
;
630 if (Ep
->Direction
== EfiUsbDataIn
) {
631 MapOp
= EfiPciIoOperationBusMasterWrite
;
633 MapOp
= EfiPciIoOperationBusMasterRead
;
636 Status
= PciIo
->Map (PciIo
, MapOp
, Data
, &Len
, &PhyAddr
, &Map
);
638 if (EFI_ERROR (Status
) || (Len
!= DataLen
)) {
642 Urb
->DataPhy
= (VOID
*) ((UINTN
) PhyAddr
);
646 Status
= EhcCreateQtds (Ehc
, Urb
);
648 if (EFI_ERROR (Status
)) {
655 EhcFreeUrb (Ehc
, Urb
);