MdeModulePkg/Bus/Pci/EhciPei/EhcPeim.h

   1 /** @file
   2 Private Header file for Usb Host Controller PEIM
   3
   4 Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
   5 Copyright (c) Microsoft Corporation.<BR>
   6
   7 SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 #ifndef _RECOVERY_EHC_H_
  12 #define _RECOVERY_EHC_H_
  13
  14 #include <PiPei.h>
  15
  16 #include <Ppi/UsbController.h>
  17 #include <Ppi/Usb2HostController.h>
  18 #include <Ppi/IoMmu.h>
  19 #include <Ppi/EndOfPeiPhase.h>
  20
  21 #include <Library/BaseLib.h>
  22 #include <Library/DebugLib.h>
  23 #include <Library/PeimEntryPoint.h>
  24 #include <Library/PeiServicesLib.h>
  25 #include <Library/BaseMemoryLib.h>
  26 #include <Library/TimerLib.h>
  27 #include <Library/IoLib.h>
  28
  29 typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV;
  30
  31 #define EFI_LIST_ENTRY  LIST_ENTRY
  32
  33 #include "UsbHcMem.h"
  34 #include "EhciReg.h"
  35 #include "EhciUrb.h"
  36 #include "EhciSched.h"
  37
  38 #define EFI_USB_SPEED_FULL  0x0000
  39 #define EFI_USB_SPEED_LOW   0x0001
  40 #define EFI_USB_SPEED_HIGH  0x0002
  41
  42 #define PAGESIZE  4096
  43
  44 #define EHC_1_MICROSECOND  1
  45 #define EHC_1_MILLISECOND  (1000 * EHC_1_MICROSECOND)
  46 #define EHC_1_SECOND       (1000 * EHC_1_MILLISECOND)
  47
  48 //
  49 // EHCI register operation timeout, set by experience
  50 //
  51 #define EHC_RESET_TIMEOUT    (1 * EHC_1_SECOND)
  52 #define EHC_GENERIC_TIMEOUT  (10 * EHC_1_MILLISECOND)
  53
  54 //
  55 // Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]
  56 //
  57 #define EHC_ROOT_PORT_RECOVERY_STALL  (20 * EHC_1_MILLISECOND)
  58
  59 //
  60 // Sync transfer polling interval, set by experience.
  61 //
  62 #define EHC_SYNC_POLL_INTERVAL  (6 * EHC_1_MILLISECOND)
  63
  64 #define EFI_LIST_CONTAINER(Entry, Type, Field)  BASE_CR(Entry, Type, Field)
  65
  66 #define EHC_LOW_32BIT(Addr64)      ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
  67 #define EHC_HIGH_32BIT(Addr64)     ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
  68 #define EHC_BIT_IS_SET(Data, Bit)  ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
  69
  70 #define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \
  71           (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))
  72
  73 #define USB2_HC_DEV_SIGNATURE  SIGNATURE_32 ('e', 'h', 'c', 'i')
  74
  75 struct _PEI_USB2_HC_DEV {
  76   UINTN                           Signature;
  77   PEI_USB2_HOST_CONTROLLER_PPI    Usb2HostControllerPpi;
  78   EDKII_IOMMU_PPI                 *IoMmu;
  79   EFI_PEI_PPI_DESCRIPTOR          PpiDescriptor;
  80   //
  81   // EndOfPei callback is used to stop the EHC DMA operation
  82   // after exit PEI phase.
  83   //
  84   EFI_PEI_NOTIFY_DESCRIPTOR       EndOfPeiNotifyList;
  85   UINT32                          UsbHostControllerBaseAddress;
  86   PEI_URB                         *Urb;
  87   USBHC_MEM_POOL                  *MemPool;
  88
  89   //
  90   // Schedule data shared between asynchronous and periodic
  91   // transfers:
  92   // ShortReadStop, as its name indicates, is used to terminate
  93   // the short read except the control transfer. EHCI follows
  94   // the alternative next QTD point when a short read happens.
  95   // For control transfer, even the short read happens, try the
  96   // status stage.
  97   //
  98   PEI_EHC_QTD       *ShortReadStop;
  99   EFI_EVENT         PollTimer;
 100
 101   //
 102   // Asynchronous(bulk and control) transfer schedule data:
 103   // ReclaimHead is used as the head of the asynchronous transfer
 104   // list. It acts as the reclamation header.
 105   //
 106   PEI_EHC_QH        *ReclaimHead;
 107
 108   //
 109   // Periodic (interrupt) transfer schedule data:
 110   //
 111   VOID              *PeriodFrame;                       // Mapped as common buffer
 112   VOID              *PeriodFrameMap;
 113
 114   PEI_EHC_QH        *PeriodOne;
 115   EFI_LIST_ENTRY    AsyncIntTransfers;
 116
 117   //
 118   // EHCI configuration data
 119   //
 120   UINT32            HcStructParams;                   // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
 121   UINT32            HcCapParams;                      // Cache of HC capability parameter, HCCPARAMS
 122   UINT32            CapLen;                           // Capability length
 123   UINT32            High32bitAddr;
 124 };
 125
 126 #define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a)    CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)
 127 #define PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY(a)  CR (a, PEI_USB2_HC_DEV, EndOfPeiNotifyList, USB2_HC_DEV_SIGNATURE)
 128
 129 /**
 130   @param  EhcDev                 EHCI Device.
 131
 132   @retval EFI_SUCCESS            EHCI successfully initialized.
 133   @retval EFI_ABORTED            EHCI was failed to be initialized.
 134
 135 **/
 136 EFI_STATUS
 137 InitializeUsbHC (
 138   IN PEI_USB2_HC_DEV  *EhcDev
 139   );
 140
 141 /**
 142   Initialize the memory management pool for the host controller.
 143
 144   @param  Ehc                   The EHCI device.
 145   @param  Check4G               Whether the host controller requires allocated memory
 146                                 from one 4G address space.
 147   @param  Which4G               The 4G memory area each memory allocated should be from.
 148
 149   @retval EFI_SUCCESS           The memory pool is initialized.
 150   @retval EFI_OUT_OF_RESOURCE   Fail to init the memory pool.
 151
 152 **/
 153 USBHC_MEM_POOL *
 154 UsbHcInitMemPool (
 155   IN PEI_USB2_HC_DEV  *Ehc,
 156   IN BOOLEAN          Check4G,
 157   IN UINT32           Which4G
 158   )
 159 ;
 160
 161 /**
 162   Release the memory management pool.
 163
 164   @param  Ehc                   The EHCI device.
 165   @param  Pool                  The USB memory pool to free.
 166
 167   @retval EFI_DEVICE_ERROR      Fail to free the memory pool.
 168   @retval EFI_SUCCESS           The memory pool is freed.
 169
 170 **/
 171 EFI_STATUS
 172 UsbHcFreeMemPool (
 173   IN PEI_USB2_HC_DEV  *Ehc,
 174   IN USBHC_MEM_POOL   *Pool
 175   )
 176 ;
 177
 178 /**
 179   Allocate some memory from the host controller's memory pool
 180   which can be used to communicate with host controller.
 181
 182   @param  Ehc       The EHCI device.
 183   @param  Pool      The host controller's memory pool.
 184   @param  Size      Size of the memory to allocate.
 185
 186   @return The allocated memory or NULL.
 187
 188 **/
 189 VOID *
 190 UsbHcAllocateMem (
 191   IN PEI_USB2_HC_DEV  *Ehc,
 192   IN  USBHC_MEM_POOL  *Pool,
 193   IN  UINTN           Size
 194   )
 195 ;
 196
 197 /**
 198   Free the allocated memory back to the memory pool.
 199
 200   @param  Ehc            The EHCI device.
 201   @param  Pool           The memory pool of the host controller.
 202   @param  Mem            The memory to free.
 203   @param  Size           The size of the memory to free.
 204
 205 **/
 206 VOID
 207 UsbHcFreeMem (
 208   IN PEI_USB2_HC_DEV  *Ehc,
 209   IN USBHC_MEM_POOL   *Pool,
 210   IN VOID             *Mem,
 211   IN UINTN            Size
 212   )
 213 ;
 214
 215 /**
 216   Provides the controller-specific addresses required to access system memory from a
 217   DMA bus master.
 218
 219   @param IoMmu                  Pointer to IOMMU PPI.
 220   @param Operation              Indicates if the bus master is going to read or write to system memory.
 221   @param HostAddress            The system memory address to map to the PCI controller.
 222   @param NumberOfBytes          On input the number of bytes to map. On output the number of bytes
 223                                 that were mapped.
 224   @param DeviceAddress          The resulting map address for the bus master PCI controller to use to
 225                                 access the hosts HostAddress.
 226   @param Mapping                A resulting value to pass to Unmap().
 227
 228   @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
 229   @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.
 230   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 231   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 232   @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
 233
 234 **/
 235 EFI_STATUS
 236 IoMmuMap (
 237   IN EDKII_IOMMU_PPI        *IoMmu,
 238   IN EDKII_IOMMU_OPERATION  Operation,
 239   IN VOID                   *HostAddress,
 240   IN OUT UINTN              *NumberOfBytes,
 241   OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,
 242   OUT VOID                  **Mapping
 243   );
 244
 245 /**
 246   Completes the Map() operation and releases any corresponding resources.
 247
 248   @param IoMmu              Pointer to IOMMU PPI.
 249   @param Mapping            The mapping value returned from Map().
 250
 251 **/
 252 VOID
 253 IoMmuUnmap (
 254   IN EDKII_IOMMU_PPI  *IoMmu,
 255   IN VOID             *Mapping
 256   );
 257
 258 /**
 259   Allocates pages that are suitable for an OperationBusMasterCommonBuffer or
 260   OperationBusMasterCommonBuffer64 mapping.
 261
 262   @param IoMmu                  Pointer to IOMMU PPI.
 263   @param Pages                  The number of pages to allocate.
 264   @param HostAddress            A pointer to store the base system memory address of the
 265                                 allocated range.
 266   @param DeviceAddress          The resulting map address for the bus master PCI controller to use to
 267                                 access the hosts HostAddress.
 268   @param Mapping                A resulting value to pass to Unmap().
 269
 270   @retval EFI_SUCCESS           The requested memory pages were allocated.
 271   @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are
 272                                 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
 273   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 274   @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
 275
 276 **/
 277 EFI_STATUS
 278 IoMmuAllocateBuffer (
 279   IN EDKII_IOMMU_PPI        *IoMmu,
 280   IN UINTN                  Pages,
 281   OUT VOID                  **HostAddress,
 282   OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,
 283   OUT VOID                  **Mapping
 284   );
 285
 286 /**
 287   Frees memory that was allocated with AllocateBuffer().
 288
 289   @param IoMmu              Pointer to IOMMU PPI.
 290   @param Pages              The number of pages to free.
 291   @param HostAddress        The base system memory address of the allocated range.
 292   @param Mapping            The mapping value returned from Map().
 293
 294 **/
 295 VOID
 296 IoMmuFreeBuffer (
 297   IN EDKII_IOMMU_PPI  *IoMmu,
 298   IN UINTN            Pages,
 299   IN VOID             *HostAddress,
 300   IN VOID             *Mapping
 301   );
 302
 303 /**
 304   Initialize IOMMU.
 305
 306   @param IoMmu              Pointer to pointer to IOMMU PPI.
 307
 308 **/
 309 VOID
 310 IoMmuInit (
 311   OUT EDKII_IOMMU_PPI  **IoMmu
 312   );
 313
 314 #endif