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git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h
2 Private Header file for Usb Host Controller PEIM
4 Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions
8 of the BSD License which accompanies this distribution. The
9 full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #ifndef _EFI_EHCI_REG_H_
18 #define _EFI_EHCI_REG_H_
23 // Capability register offset
25 #define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
26 #define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
27 #define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
30 // Capability register bit definition
32 #define HCSP_NPORTS 0x0F // Number of root hub port
33 #define HCCP_64BIT 0x01 // 64-bit addressing capability
36 // Operational register offset
38 #define EHC_USBCMD_OFFSET 0x0 // USB command register offset
39 #define EHC_USBSTS_OFFSET 0x04 // Statue register offset
40 #define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset
41 #define EHC_FRINDEX_OFFSET 0x0C // Frame index offset
42 #define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset
43 #define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset
44 #define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset
45 #define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset
46 #define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset
48 #define EHC_FRAME_LEN 1024
51 // Register bit definition
53 #define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
55 #define USBCMD_RUN 0x01 // Run/stop
56 #define USBCMD_RESET 0x02 // Start the host controller reset
57 #define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
58 #define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
59 #define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
61 #define USBSTS_IAA 0x20 // Interrupt on async advance
62 #define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
63 #define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
64 #define USBSTS_HALT 0x1000 // Host controller halted
65 #define USBSTS_SYS_ERROR 0x10 // Host system error
66 #define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
67 // (write clean) bits in USBSTS register
69 #define PORTSC_CONN 0x01 // Current Connect Status
70 #define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
71 #define PORTSC_ENABLED 0x04 // Port Enable / Disable
72 #define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
73 #define PORTSC_OVERCUR 0x10 // Over current Active
74 #define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
75 #define PORSTSC_RESUME 0x40 // Force Port Resume
76 #define PORTSC_SUSPEND 0x80 // Port Suspend State
77 #define PORTSC_RESET 0x100 // Port Reset
78 #define PORTSC_LINESTATE_K 0x400 // Line Status K-state
79 #define PORTSC_LINESTATE_J 0x800 // Line Status J-state
80 #define PORTSC_POWER 0x1000 // Port Power
81 #define PORTSC_OWNER 0x2000 // Port Owner
82 #define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
83 // they are WC (write clean)
85 // PCI Configuration Registers
87 #define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
89 #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
91 #define EHC_ADDR(High, QhHw32) \
92 ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
94 #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
97 // Structure to map the hardware port states to the
98 // UEFI's port states.
103 } USB_PORT_STATE_MAP
;
106 // Ehci Data and Ctrl Structures
118 Read EHCI capability register.
120 @param Ehc The EHCI device.
121 @param Offset Capability register address.
123 @retval the register content read.
128 IN PEI_USB2_HC_DEV
*Ehc
,
134 Read Ehc Operation register.
136 @param Ehc The EHCI device.
137 @param Offset The operation register offset.
139 @retval the register content read.
144 IN PEI_USB2_HC_DEV
*Ehc
,
150 Write the data to the EHCI operation register.
152 @param Ehc The EHCI device.
153 @param Offset EHCI operation register offset.
154 @param Data The data to write.
159 IN PEI_USB2_HC_DEV
*Ehc
,
166 Stop the legacy USB SMI support.
168 @param Ehc The EHCI device.
172 EhcClearLegacySupport (
173 IN PEI_USB2_HC_DEV
*Ehc
178 Set door bell and wait it to be ACKed by host controller.
179 This function is used to synchronize with the hardware.
181 @param Ehc The EHCI device.
182 @param Timeout The time to wait before abort (in millisecond, ms).
184 @retval EFI_TIMEOUT Time out happened while waiting door bell to set.
185 @retval EFI_SUCCESS Synchronized with the hardware.
189 EhcSetAndWaitDoorBell (
190 IN PEI_USB2_HC_DEV
*Ehc
,
196 Clear all the interrutp status bits, these bits
199 @param Ehc The EHCI device.
204 IN PEI_USB2_HC_DEV
*Ehc
209 Check whether Ehc is halted.
211 @param Ehc The EHCI device.
213 @retval TRUE The controller is halted.
214 @retval FALSE The controller isn't halted.
219 IN PEI_USB2_HC_DEV
*Ehc
224 Check whether system error occurred.
226 @param Ehc The EHCI device.
228 @retval TRUE System error happened.
229 @retval FALSE No system error.
234 IN PEI_USB2_HC_DEV
*Ehc
239 Reset the host controller.
241 @param Ehc The EHCI device.
242 @param Timeout Time to wait before abort (in millisecond, ms).
244 @retval EFI_TIMEOUT The transfer failed due to time out.
245 @retval Others Failed to reset the host.
250 IN PEI_USB2_HC_DEV
*Ehc
,
256 Halt the host controller.
258 @param Ehc The EHCI device.
259 @param Timeout Time to wait before abort.
261 @retval EFI_TIMEOUT Failed to halt the controller before Timeout.
262 @retval EFI_SUCCESS The EHCI is halt.
267 IN PEI_USB2_HC_DEV
*Ehc
,
275 @param Ehc The EHCI device.
276 @param Timeout Time to wait before abort.
278 @retval EFI_SUCCESS The EHCI is running.
279 @retval Others Failed to set the EHCI to run.
284 IN PEI_USB2_HC_DEV
*Ehc
,
290 Initialize the HC hardware.
291 EHCI spec lists the five things to do to initialize the hardware.
292 1. Program CTRLDSSEGMENT.
293 2. Set USBINTR to enable interrupts.
294 3. Set periodic list base.
295 4. Set USBCMD, interrupt threshold, frame list size etc.
296 5. Write 1 to CONFIGFLAG to route all ports to EHCI.
298 @param Ehc The EHCI device.
300 @retval EFI_SUCCESS The EHCI has come out of halt state.
301 @retval EFI_TIMEOUT Time out happened.
306 IN PEI_USB2_HC_DEV
*Ehc