MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h

   1 /** @file
   2 Private Header file for Usb Host Controller PEIM
   3
   4 Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
   5
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef _EFI_EHCI_REG_H_
  11 #define _EFI_EHCI_REG_H_
  12
  13 //
  14 // Capability register offset
  15 //
  16 #define EHC_CAPLENGTH_OFFSET  0      // Capability register length offset
  17 #define EHC_HCSPARAMS_OFFSET  0x04   // Structural Parameters 04-07h
  18 #define EHC_HCCPARAMS_OFFSET  0x08   // Capability parameters offset
  19
  20 //
  21 // Capability register bit definition
  22 //
  23 #define HCSP_NPORTS  0x0F            // Number of root hub port
  24 #define HCCP_64BIT   0x01            // 64-bit addressing capability
  25
  26 //
  27 // Operational register offset
  28 //
  29 #define EHC_USBCMD_OFFSET       0x0  // USB command register offset
  30 #define EHC_USBSTS_OFFSET       0x04 // Statue register offset
  31 #define EHC_USBINTR_OFFSET      0x08 // USB interrutp offset
  32 #define EHC_FRINDEX_OFFSET      0x0C // Frame index offset
  33 #define EHC_CTRLDSSEG_OFFSET    0x10 // Control data structure segment offset
  34 #define EHC_FRAME_BASE_OFFSET   0x14 // Frame list base address offset
  35 #define EHC_ASYNC_HEAD_OFFSET   0x18 // Next asynchronous list address offset
  36 #define EHC_CONFIG_FLAG_OFFSET  0x40 // Configure flag register offset
  37 #define EHC_PORT_STAT_OFFSET    0x44 // Port status/control offset
  38
  39 #define EHC_FRAME_LEN  1024
  40
  41 //
  42 // Register bit definition
  43 //
  44 #define CONFIGFLAG_ROUTE_EHC  0x01   // Route port to EHC
  45
  46 #define USBCMD_RUN            0x01     // Run/stop
  47 #define USBCMD_RESET          0x02     // Start the host controller reset
  48 #define USBCMD_ENABLE_PERIOD  0x10     // Enable periodic schedule
  49 #define USBCMD_ENABLE_ASYNC   0x20     // Enable asynchronous schedule
  50 #define USBCMD_IAAD           0x40     // Interrupt on async advance doorbell
  51
  52 #define USBSTS_IAA             0x20    // Interrupt on async advance
  53 #define USBSTS_PERIOD_ENABLED  0x4000  // Periodic schedule status
  54 #define USBSTS_ASYNC_ENABLED   0x8000  // Asynchronous schedule status
  55 #define USBSTS_HALT            0x1000  // Host controller halted
  56 #define USBSTS_SYS_ERROR       0x10    // Host system error
  57 #define USBSTS_INTACK_MASK     0x003F  // Mask for the interrupt ACK, the WC
  58                                        // (write clean) bits in USBSTS register
  59
  60 #define PORTSC_CONN            0x01    // Current Connect Status
  61 #define PORTSC_CONN_CHANGE     0x02    // Connect Status Change
  62 #define PORTSC_ENABLED         0x04    // Port Enable / Disable
  63 #define PORTSC_ENABLE_CHANGE   0x08    // Port Enable / Disable Change
  64 #define PORTSC_OVERCUR         0x10    // Over current Active
  65 #define PORTSC_OVERCUR_CHANGE  0x20    // Over current Change
  66 #define PORSTSC_RESUME         0x40    // Force Port Resume
  67 #define PORTSC_SUSPEND         0x80    // Port Suspend State
  68 #define PORTSC_RESET           0x100   // Port Reset
  69 #define PORTSC_LINESTATE_K     0x400   // Line Status K-state
  70 #define PORTSC_LINESTATE_J     0x800   // Line Status J-state
  71 #define PORTSC_POWER           0x1000  // Port Power
  72 #define PORTSC_OWNER           0x2000  // Port Owner
  73 #define PORTSC_CHANGE_MASK     0x2A    // Mask of the port change bits,
  74                                        // they are WC (write clean)
  75 //
  76 // PCI Configuration Registers
  77 //
  78 #define EHC_BAR_INDEX  0               // how many bytes away from USB_BASE to 0x10
  79
  80 #define EHC_LINK_TERMINATED(Link)  (((Link) & 0x01) != 0)
  81
  82 #define EHC_ADDR(High, QhHw32)   \
  83         ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
  84
  85 #define EHCI_IS_DATAIN(EndpointAddr)  EHC_BIT_IS_SET((EndpointAddr), 0x80)
  86
  87 //
  88 // Structure to map the hardware port states to the
  89 // UEFI's port states.
  90 //
  91 typedef struct {
  92   UINT16    HwState;
  93   UINT16    UefiState;
  94 } USB_PORT_STATE_MAP;
  95
  96 //
  97 // Ehci Data and Ctrl Structures
  98 //
  99 #pragma pack(1)
 100 typedef struct {
 101   UINT8    Pi;
 102   UINT8    SubClassCode;
 103   UINT8    BaseCode;
 104 } USB_CLASSC;
 105 #pragma pack()
 106
 107 /**
 108   Read EHCI capability register.
 109
 110   @param  Ehc       The EHCI device.
 111   @param  Offset    Capability register address.
 112
 113   @retval the register content read.
 114
 115 **/
 116 UINT32
 117 EhcReadCapRegister (
 118   IN  PEI_USB2_HC_DEV  *Ehc,
 119   IN  UINT32           Offset
 120   )
 121 ;
 122
 123 /**
 124   Read Ehc Operation register.
 125
 126   @param  Ehc       The EHCI device.
 127   @param  Offset    The operation register offset.
 128
 129   @retval the register content read.
 130
 131 **/
 132 UINT32
 133 EhcReadOpReg (
 134   IN  PEI_USB2_HC_DEV  *Ehc,
 135   IN  UINT32           Offset
 136   )
 137 ;
 138
 139 /**
 140   Write the data to the EHCI operation register.
 141
 142   @param  Ehc       The EHCI device.
 143   @param  Offset    EHCI operation register offset.
 144   @param  Data      The data to write.
 145
 146 **/
 147 VOID
 148 EhcWriteOpReg (
 149   IN PEI_USB2_HC_DEV  *Ehc,
 150   IN UINT32           Offset,
 151   IN UINT32           Data
 152   )
 153 ;
 154
 155 /**
 156   Stop the legacy USB SMI support.
 157
 158   @param  Ehc       The EHCI device.
 159
 160 **/
 161 VOID
 162 EhcClearLegacySupport (
 163   IN PEI_USB2_HC_DEV  *Ehc
 164   )
 165 ;
 166
 167 /**
 168   Set door bell and wait it to be ACKed by host controller.
 169   This function is used to synchronize with the hardware.
 170
 171   @param  Ehc       The EHCI device.
 172   @param  Timeout   The time to wait before abort (in millisecond, ms).
 173
 174   @retval EFI_TIMEOUT       Time out happened while waiting door bell to set.
 175   @retval EFI_SUCCESS       Synchronized with the hardware.
 176
 177 **/
 178 EFI_STATUS
 179 EhcSetAndWaitDoorBell (
 180   IN  PEI_USB2_HC_DEV  *Ehc,
 181   IN  UINT32           Timeout
 182   )
 183 ;
 184
 185 /**
 186   Clear all the interrutp status bits, these bits
 187   are Write-Clean.
 188
 189   @param  Ehc       The EHCI device.
 190
 191 **/
 192 VOID
 193 EhcAckAllInterrupt (
 194   IN  PEI_USB2_HC_DEV  *Ehc
 195   )
 196 ;
 197
 198 /**
 199   Check whether Ehc is halted.
 200
 201   @param  Ehc       The EHCI device.
 202
 203   @retval TRUE      The controller is halted.
 204   @retval FALSE     The controller isn't halted.
 205
 206 **/
 207 BOOLEAN
 208 EhcIsHalt (
 209   IN PEI_USB2_HC_DEV  *Ehc
 210   )
 211 ;
 212
 213 /**
 214   Check whether system error occurred.
 215
 216   @param  Ehc       The EHCI device.
 217
 218   @retval TRUE      System error happened.
 219   @retval FALSE     No system error.
 220
 221 **/
 222 BOOLEAN
 223 EhcIsSysError (
 224   IN PEI_USB2_HC_DEV  *Ehc
 225   )
 226 ;
 227
 228 /**
 229   Reset the host controller.
 230
 231   @param  Ehc             The EHCI device.
 232   @param  Timeout         Time to wait before abort (in millisecond, ms).
 233
 234   @retval EFI_TIMEOUT     The transfer failed due to time out.
 235   @retval Others          Failed to reset the host.
 236
 237 **/
 238 EFI_STATUS
 239 EhcResetHC (
 240   IN PEI_USB2_HC_DEV  *Ehc,
 241   IN UINT32           Timeout
 242   )
 243 ;
 244
 245 /**
 246   Halt the host controller.
 247
 248   @param  Ehc             The EHCI device.
 249   @param  Timeout         Time to wait before abort.
 250
 251   @retval EFI_TIMEOUT     Failed to halt the controller before Timeout.
 252   @retval EFI_SUCCESS     The EHCI is halt.
 253
 254 **/
 255 EFI_STATUS
 256 EhcHaltHC (
 257   IN PEI_USB2_HC_DEV  *Ehc,
 258   IN UINT32           Timeout
 259   )
 260 ;
 261
 262 /**
 263   Set the EHCI to run
 264
 265   @param  Ehc             The EHCI device.
 266   @param  Timeout         Time to wait before abort.
 267
 268   @retval EFI_SUCCESS     The EHCI is running.
 269   @retval Others          Failed to set the EHCI to run.
 270
 271 **/
 272 EFI_STATUS
 273 EhcRunHC (
 274   IN PEI_USB2_HC_DEV  *Ehc,
 275   IN UINT32           Timeout
 276   )
 277 ;
 278
 279 /**
 280   Initialize the HC hardware.
 281   EHCI spec lists the five things to do to initialize the hardware.
 282   1. Program CTRLDSSEGMENT.
 283   2. Set USBINTR to enable interrupts.
 284   3. Set periodic list base.
 285   4. Set USBCMD, interrupt threshold, frame list size etc.
 286   5. Write 1 to CONFIGFLAG to route all ports to EHCI.
 287
 288   @param  Ehc             The EHCI device.
 289
 290   @retval EFI_SUCCESS     The EHCI has come out of halt state.
 291   @retval EFI_TIMEOUT     Time out happened.
 292
 293 **/
 294 EFI_STATUS
 295 EhcInitHC (
 296   IN PEI_USB2_HC_DEV  *Ehc
 297   )
 298 ;
 299
 300 #endif