2 NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows
3 NVM Express specification.
5 Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include "NvmExpress.h"
19 Read Nvm Express controller capability register.
21 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
22 @param Cap The buffer used to store capability register content.
24 @return EFI_SUCCESS Successfully read the controller capability register content.
25 @return EFI_DEVICE_ERROR Fail to read the controller capability register.
29 ReadNvmeControllerCapabilities (
30 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
34 EFI_PCI_IO_PROTOCOL
*PciIo
;
38 PciIo
= Private
->PciIo
;
39 Status
= PciIo
->Mem
.Read (
48 if (EFI_ERROR(Status
)) {
52 WriteUnaligned64 ((UINT64
*)Cap
, Data
);
57 Read Nvm Express controller configuration register.
59 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
60 @param Cc The buffer used to store configuration register content.
62 @return EFI_SUCCESS Successfully read the controller configuration register content.
63 @return EFI_DEVICE_ERROR Fail to read the controller configuration register.
67 ReadNvmeControllerConfiguration (
68 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
72 EFI_PCI_IO_PROTOCOL
*PciIo
;
76 PciIo
= Private
->PciIo
;
77 Status
= PciIo
->Mem
.Read (
86 if (EFI_ERROR(Status
)) {
90 WriteUnaligned32 ((UINT32
*)Cc
, Data
);
95 Write Nvm Express controller configuration register.
97 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
98 @param Cc The buffer used to store the content to be written into configuration register.
100 @return EFI_SUCCESS Successfully write data into the controller configuration register.
101 @return EFI_DEVICE_ERROR Fail to write data into the controller configuration register.
105 WriteNvmeControllerConfiguration (
106 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
110 EFI_PCI_IO_PROTOCOL
*PciIo
;
114 PciIo
= Private
->PciIo
;
115 Data
= ReadUnaligned32 ((UINT32
*)Cc
);
116 Status
= PciIo
->Mem
.Write (
125 if (EFI_ERROR(Status
)) {
129 DEBUG ((EFI_D_INFO
, "Cc.En: %d\n", Cc
->En
));
130 DEBUG ((EFI_D_INFO
, "Cc.Css: %d\n", Cc
->Css
));
131 DEBUG ((EFI_D_INFO
, "Cc.Mps: %d\n", Cc
->Mps
));
132 DEBUG ((EFI_D_INFO
, "Cc.Ams: %d\n", Cc
->Ams
));
133 DEBUG ((EFI_D_INFO
, "Cc.Shn: %d\n", Cc
->Shn
));
134 DEBUG ((EFI_D_INFO
, "Cc.Iosqes: %d\n", Cc
->Iosqes
));
135 DEBUG ((EFI_D_INFO
, "Cc.Iocqes: %d\n", Cc
->Iocqes
));
141 Read Nvm Express controller status register.
143 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
144 @param Csts The buffer used to store status register content.
146 @return EFI_SUCCESS Successfully read the controller status register content.
147 @return EFI_DEVICE_ERROR Fail to read the controller status register.
151 ReadNvmeControllerStatus (
152 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
156 EFI_PCI_IO_PROTOCOL
*PciIo
;
160 PciIo
= Private
->PciIo
;
161 Status
= PciIo
->Mem
.Read (
170 if (EFI_ERROR(Status
)) {
174 WriteUnaligned32 ((UINT32
*)Csts
, Data
);
179 Read Nvm Express admin queue attributes register.
181 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
182 @param Aqa The buffer used to store admin queue attributes register content.
184 @return EFI_SUCCESS Successfully read the admin queue attributes register content.
185 @return EFI_DEVICE_ERROR Fail to read the admin queue attributes register.
189 ReadNvmeAdminQueueAttributes (
190 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
194 EFI_PCI_IO_PROTOCOL
*PciIo
;
198 PciIo
= Private
->PciIo
;
199 Status
= PciIo
->Mem
.Read (
208 if (EFI_ERROR(Status
)) {
212 WriteUnaligned32 ((UINT32
*)Aqa
, Data
);
217 Write Nvm Express admin queue attributes register.
219 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
220 @param Aqa The buffer used to store the content to be written into admin queue attributes register.
222 @return EFI_SUCCESS Successfully write data into the admin queue attributes register.
223 @return EFI_DEVICE_ERROR Fail to write data into the admin queue attributes register.
227 WriteNvmeAdminQueueAttributes (
228 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
232 EFI_PCI_IO_PROTOCOL
*PciIo
;
236 PciIo
= Private
->PciIo
;
237 Data
= ReadUnaligned32 ((UINT32
*)Aqa
);
238 Status
= PciIo
->Mem
.Write (
247 if (EFI_ERROR(Status
)) {
251 DEBUG ((EFI_D_INFO
, "Aqa.Asqs: %d\n", Aqa
->Asqs
));
252 DEBUG ((EFI_D_INFO
, "Aqa.Acqs: %d\n", Aqa
->Acqs
));
258 Read Nvm Express admin submission queue base address register.
260 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
261 @param Asq The buffer used to store admin submission queue base address register content.
263 @return EFI_SUCCESS Successfully read the admin submission queue base address register content.
264 @return EFI_DEVICE_ERROR Fail to read the admin submission queue base address register.
268 ReadNvmeAdminSubmissionQueueBaseAddress (
269 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
273 EFI_PCI_IO_PROTOCOL
*PciIo
;
277 PciIo
= Private
->PciIo
;
278 Status
= PciIo
->Mem
.Read (
287 if (EFI_ERROR(Status
)) {
291 WriteUnaligned64 ((UINT64
*)Asq
, Data
);
296 Write Nvm Express admin submission queue base address register.
298 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
299 @param Asq The buffer used to store the content to be written into admin submission queue base address register.
301 @return EFI_SUCCESS Successfully write data into the admin submission queue base address register.
302 @return EFI_DEVICE_ERROR Fail to write data into the admin submission queue base address register.
306 WriteNvmeAdminSubmissionQueueBaseAddress (
307 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
311 EFI_PCI_IO_PROTOCOL
*PciIo
;
315 PciIo
= Private
->PciIo
;
316 Data
= ReadUnaligned64 ((UINT64
*)Asq
);
318 Status
= PciIo
->Mem
.Write (
327 if (EFI_ERROR(Status
)) {
331 DEBUG ((EFI_D_INFO
, "Asq.Asqb: %lx\n", Asq
->Asqb
));
337 Read Nvm Express admin completion queue base address register.
339 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
340 @param Acq The buffer used to store admin completion queue base address register content.
342 @return EFI_SUCCESS Successfully read the admin completion queue base address register content.
343 @return EFI_DEVICE_ERROR Fail to read the admin completion queue base address register.
347 ReadNvmeAdminCompletionQueueBaseAddress (
348 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
352 EFI_PCI_IO_PROTOCOL
*PciIo
;
356 PciIo
= Private
->PciIo
;
358 Status
= PciIo
->Mem
.Read (
367 if (EFI_ERROR(Status
)) {
371 WriteUnaligned64 ((UINT64
*)Acq
, Data
);
376 Write Nvm Express admin completion queue base address register.
378 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
379 @param Acq The buffer used to store the content to be written into admin completion queue base address register.
381 @return EFI_SUCCESS Successfully write data into the admin completion queue base address register.
382 @return EFI_DEVICE_ERROR Fail to write data into the admin completion queue base address register.
386 WriteNvmeAdminCompletionQueueBaseAddress (
387 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
391 EFI_PCI_IO_PROTOCOL
*PciIo
;
395 PciIo
= Private
->PciIo
;
396 Data
= ReadUnaligned64 ((UINT64
*)Acq
);
398 Status
= PciIo
->Mem
.Write (
407 if (EFI_ERROR(Status
)) {
411 DEBUG ((EFI_D_INFO
, "Acq.Acqb: %lxh\n", Acq
->Acqb
));
417 Disable the Nvm Express controller.
419 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
421 @return EFI_SUCCESS Successfully disable the controller.
422 @return EFI_DEVICE_ERROR Fail to disable the controller.
426 NvmeDisableController (
427 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
435 // Read Controller Configuration Register.
437 Status
= ReadNvmeControllerConfiguration (Private
, &Cc
);
438 if (EFI_ERROR(Status
)) {
445 // Disable the controller.
447 Status
= WriteNvmeControllerConfiguration (Private
, &Cc
);
449 if (EFI_ERROR(Status
)) {
456 // Check if the controller is reset
458 Status
= ReadNvmeControllerStatus (Private
, &Csts
);
460 if (EFI_ERROR(Status
)) {
465 return EFI_DEVICE_ERROR
;
468 DEBUG ((EFI_D_INFO
, "NVMe controller is disabled with status [%r].\n", Status
));
473 Enable the Nvm Express controller.
475 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
477 @return EFI_SUCCESS Successfully enable the controller.
478 @return EFI_DEVICE_ERROR Fail to enable the controller.
479 @return EFI_TIMEOUT Fail to enable the controller in given time slot.
483 NvmeEnableController (
484 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
494 // Enable the controller
496 ZeroMem (&Cc
, sizeof (NVME_CC
));
500 Status
= WriteNvmeControllerConfiguration (Private
, &Cc
);
502 if (EFI_ERROR(Status
)) {
507 // Cap.To specifies max delay time in 500ms increments for Csts.Rdy to set after
508 // Cc.Enable. Loop produces a 1 millisecond delay per itteration, up to 500 * Cap.To.
510 if (Private
->Cap
.To
== 0) {
513 Timeout
= Private
->Cap
.To
;
516 for(Index
= (Timeout
* 500); Index
!= 0; --Index
) {
520 // Check if the controller is initialized
522 Status
= ReadNvmeControllerStatus (Private
, &Csts
);
524 if (EFI_ERROR(Status
)) {
534 Status
= EFI_TIMEOUT
;
537 DEBUG ((EFI_D_INFO
, "NVMe controller is enabled with status [%r].\n", Status
));
542 Get identify controller data.
544 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
545 @param Buffer The buffer used to store the identify controller data.
547 @return EFI_SUCCESS Successfully get the identify controller data.
548 @return EFI_DEVICE_ERROR Fail to get the identify controller data.
552 NvmeIdentifyController (
553 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
557 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket
;
558 NVM_EXPRESS_COMMAND Command
;
559 NVM_EXPRESS_RESPONSE Response
;
562 ZeroMem (&CommandPacket
, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET
));
563 ZeroMem (&Command
, sizeof(NVM_EXPRESS_COMMAND
));
564 ZeroMem (&Response
, sizeof(NVM_EXPRESS_RESPONSE
));
566 Command
.Cdw0
.Opcode
= NVME_ADMIN_IDENTIFY_OPC
;
567 Command
.Cdw0
.Cid
= Private
->Cid
[0]++;
569 // According to Nvm Express 1.1 spec Figure 38, When not used, the field shall be cleared to 0h.
570 // For the Identify command, the Namespace Identifier is only used for the Namespace data structure.
574 CommandPacket
.NvmeCmd
= &Command
;
575 CommandPacket
.NvmeResponse
= &Response
;
576 CommandPacket
.TransferBuffer
= Buffer
;
577 CommandPacket
.TransferLength
= sizeof (NVME_ADMIN_CONTROLLER_DATA
);
578 CommandPacket
.CommandTimeout
= NVME_GENERIC_TIMEOUT
;
579 CommandPacket
.QueueId
= NVME_ADMIN_QUEUE
;
581 // Set bit 0 (Cns bit) to 1 to identify a controller
584 Command
.Flags
= CDW10_VALID
;
586 Status
= Private
->Passthru
.PassThru (
598 Get specified identify namespace data.
600 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
601 @param NamespaceId The specified namespace identifier.
602 @param Buffer The buffer used to store the identify namespace data.
604 @return EFI_SUCCESS Successfully get the identify namespace data.
605 @return EFI_DEVICE_ERROR Fail to get the identify namespace data.
609 NvmeIdentifyNamespace (
610 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
611 IN UINT32 NamespaceId
,
615 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket
;
616 NVM_EXPRESS_COMMAND Command
;
617 NVM_EXPRESS_RESPONSE Response
;
620 ZeroMem (&CommandPacket
, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET
));
621 ZeroMem (&Command
, sizeof(NVM_EXPRESS_COMMAND
));
622 ZeroMem (&Response
, sizeof(NVM_EXPRESS_RESPONSE
));
624 CommandPacket
.NvmeCmd
= &Command
;
625 CommandPacket
.NvmeResponse
= &Response
;
627 Command
.Cdw0
.Opcode
= NVME_ADMIN_IDENTIFY_OPC
;
628 Command
.Cdw0
.Cid
= Private
->Cid
[0]++;
629 Command
.Nsid
= NamespaceId
;
630 CommandPacket
.TransferBuffer
= Buffer
;
631 CommandPacket
.TransferLength
= sizeof (NVME_ADMIN_NAMESPACE_DATA
);
632 CommandPacket
.CommandTimeout
= NVME_GENERIC_TIMEOUT
;
633 CommandPacket
.QueueId
= NVME_ADMIN_QUEUE
;
635 // Set bit 0 (Cns bit) to 1 to identify a namespace
637 CommandPacket
.NvmeCmd
->Cdw10
= 0;
638 CommandPacket
.NvmeCmd
->Flags
= CDW10_VALID
;
640 Status
= Private
->Passthru
.PassThru (
652 Create io completion queue.
654 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
656 @return EFI_SUCCESS Successfully create io completion queue.
657 @return EFI_DEVICE_ERROR Fail to create io completion queue.
661 NvmeCreateIoCompletionQueue (
662 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
665 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket
;
666 NVM_EXPRESS_COMMAND Command
;
667 NVM_EXPRESS_RESPONSE Response
;
669 NVME_ADMIN_CRIOCQ CrIoCq
;
671 ZeroMem (&CommandPacket
, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET
));
672 ZeroMem (&Command
, sizeof(NVM_EXPRESS_COMMAND
));
673 ZeroMem (&Response
, sizeof(NVM_EXPRESS_RESPONSE
));
674 ZeroMem (&CrIoCq
, sizeof(NVME_ADMIN_CRIOCQ
));
676 CommandPacket
.NvmeCmd
= &Command
;
677 CommandPacket
.NvmeResponse
= &Response
;
679 Command
.Cdw0
.Opcode
= NVME_ADMIN_CRIOCQ_OPC
;
680 Command
.Cdw0
.Cid
= Private
->Cid
[0]++;
681 CommandPacket
.TransferBuffer
= Private
->CqBufferPciAddr
[1];
682 CommandPacket
.TransferLength
= EFI_PAGE_SIZE
;
683 CommandPacket
.CommandTimeout
= NVME_GENERIC_TIMEOUT
;
684 CommandPacket
.QueueId
= NVME_ADMIN_QUEUE
;
686 CrIoCq
.Qid
= NVME_IO_QUEUE
;
687 CrIoCq
.Qsize
= NVME_CCQ_SIZE
;
689 CopyMem (&CommandPacket
.NvmeCmd
->Cdw10
, &CrIoCq
, sizeof (NVME_ADMIN_CRIOCQ
));
690 CommandPacket
.NvmeCmd
->Flags
= CDW10_VALID
| CDW11_VALID
;
692 Status
= Private
->Passthru
.PassThru (
704 Create io submission queue.
706 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
708 @return EFI_SUCCESS Successfully create io submission queue.
709 @return EFI_DEVICE_ERROR Fail to create io submission queue.
713 NvmeCreateIoSubmissionQueue (
714 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
717 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket
;
718 NVM_EXPRESS_COMMAND Command
;
719 NVM_EXPRESS_RESPONSE Response
;
721 NVME_ADMIN_CRIOSQ CrIoSq
;
723 ZeroMem (&CommandPacket
, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET
));
724 ZeroMem (&Command
, sizeof(NVM_EXPRESS_COMMAND
));
725 ZeroMem (&Response
, sizeof(NVM_EXPRESS_RESPONSE
));
726 ZeroMem (&CrIoSq
, sizeof(NVME_ADMIN_CRIOSQ
));
728 CommandPacket
.NvmeCmd
= &Command
;
729 CommandPacket
.NvmeResponse
= &Response
;
731 Command
.Cdw0
.Opcode
= NVME_ADMIN_CRIOSQ_OPC
;
732 Command
.Cdw0
.Cid
= Private
->Cid
[0]++;
733 CommandPacket
.TransferBuffer
= Private
->SqBufferPciAddr
[1];
734 CommandPacket
.TransferLength
= EFI_PAGE_SIZE
;
735 CommandPacket
.CommandTimeout
= NVME_GENERIC_TIMEOUT
;
736 CommandPacket
.QueueId
= NVME_ADMIN_QUEUE
;
738 CrIoSq
.Qid
= NVME_IO_QUEUE
;
739 CrIoSq
.Qsize
= NVME_CSQ_SIZE
;
741 CrIoSq
.Cqid
= NVME_IO_QUEUE
;
743 CopyMem (&CommandPacket
.NvmeCmd
->Cdw10
, &CrIoSq
, sizeof (NVME_ADMIN_CRIOSQ
));
744 CommandPacket
.NvmeCmd
->Flags
= CDW10_VALID
| CDW11_VALID
;
746 Status
= Private
->Passthru
.PassThru (
758 Initialize the Nvm Express controller.
760 @param[in] Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
762 @retval EFI_SUCCESS The NVM Express Controller is initialized successfully.
763 @retval Others A device error occurred while initializing the controller.
768 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
772 EFI_PCI_IO_PROTOCOL
*PciIo
;
779 // Save original PCI attributes and enable this controller.
781 PciIo
= Private
->PciIo
;
782 Status
= PciIo
->Attributes (
784 EfiPciIoAttributeOperationGet
,
786 &Private
->PciAttributes
789 if (EFI_ERROR (Status
)) {
793 Status
= PciIo
->Attributes (
795 EfiPciIoAttributeOperationSupported
,
800 if (!EFI_ERROR (Status
)) {
801 Supports
&= EFI_PCI_DEVICE_ENABLE
;
802 Status
= PciIo
->Attributes (
804 EfiPciIoAttributeOperationEnable
,
810 if (EFI_ERROR (Status
)) {
811 DEBUG ((EFI_D_INFO
, "NvmeControllerInit: failed to enable controller\n"));
816 // Read the Controller Capabilities register and verify that the NVM command set is supported
818 Status
= ReadNvmeControllerCapabilities (Private
, &Private
->Cap
);
819 if (EFI_ERROR (Status
)) {
823 if (Private
->Cap
.Css
!= 0x01) {
824 DEBUG ((EFI_D_INFO
, "NvmeControllerInit: the controller doesn't support NVMe command set\n"));
825 return EFI_UNSUPPORTED
;
829 // Currently the driver only supports 4k page size.
831 ASSERT ((Private
->Cap
.Mpsmin
+ 12) <= EFI_PAGE_SHIFT
);
836 Status
= NvmeDisableController (Private
);
838 if (EFI_ERROR(Status
)) {
843 // set number of entries admin submission & completion queues.
845 Aqa
.Asqs
= NVME_ASQ_SIZE
;
847 Aqa
.Acqs
= NVME_ACQ_SIZE
;
851 // Address of admin submission queue.
854 Asq
.Asqb
= (UINT64
)(UINTN
)(Private
->BufferPciAddr
) >> 12;
857 // Address of admin completion queue.
860 Acq
.Acqb
= (UINT64
)(UINTN
)(Private
->BufferPciAddr
+ EFI_PAGE_SIZE
) >> 12;
863 // Address of I/O submission & completion queue.
865 Private
->SqBuffer
[0] = (NVME_SQ
*)(UINTN
)(Private
->Buffer
);
866 Private
->SqBufferPciAddr
[0] = (NVME_SQ
*)(UINTN
)(Private
->BufferPciAddr
);
867 Private
->CqBuffer
[0] = (NVME_CQ
*)(UINTN
)(Private
->Buffer
+ 1 * EFI_PAGE_SIZE
);
868 Private
->CqBufferPciAddr
[0] = (NVME_CQ
*)(UINTN
)(Private
->BufferPciAddr
+ 1 * EFI_PAGE_SIZE
);
869 Private
->SqBuffer
[1] = (NVME_SQ
*)(UINTN
)(Private
->Buffer
+ 2 * EFI_PAGE_SIZE
);
870 Private
->SqBufferPciAddr
[1] = (NVME_SQ
*)(UINTN
)(Private
->BufferPciAddr
+ 2 * EFI_PAGE_SIZE
);
871 Private
->CqBuffer
[1] = (NVME_CQ
*)(UINTN
)(Private
->Buffer
+ 3 * EFI_PAGE_SIZE
);
872 Private
->CqBufferPciAddr
[1] = (NVME_CQ
*)(UINTN
)(Private
->BufferPciAddr
+ 3 * EFI_PAGE_SIZE
);
874 DEBUG ((EFI_D_INFO
, "Private->Buffer = [%016X]\n", (UINT64
)(UINTN
)Private
->Buffer
));
875 DEBUG ((EFI_D_INFO
, "Admin Submission Queue size (Aqa.Asqs) = [%08X]\n", Aqa
.Asqs
));
876 DEBUG ((EFI_D_INFO
, "Admin Completion Queue size (Aqa.Acqs) = [%08X]\n", Aqa
.Acqs
));
877 DEBUG ((EFI_D_INFO
, "Admin Submission Queue (SqBuffer[0]) = [%016X]\n", Private
->SqBuffer
[0]));
878 DEBUG ((EFI_D_INFO
, "Admin Completion Queue (CqBuffer[0]) = [%016X]\n", Private
->CqBuffer
[0]));
879 DEBUG ((EFI_D_INFO
, "I/O Submission Queue (SqBuffer[1]) = [%016X]\n", Private
->SqBuffer
[1]));
880 DEBUG ((EFI_D_INFO
, "I/O Completion Queue (CqBuffer[1]) = [%016X]\n", Private
->CqBuffer
[1]));
883 // Program admin queue attributes.
885 Status
= WriteNvmeAdminQueueAttributes (Private
, &Aqa
);
887 if (EFI_ERROR(Status
)) {
892 // Program admin submission queue address.
894 Status
= WriteNvmeAdminSubmissionQueueBaseAddress (Private
, &Asq
);
896 if (EFI_ERROR(Status
)) {
901 // Program admin completion queue address.
903 Status
= WriteNvmeAdminCompletionQueueBaseAddress (Private
, &Acq
);
905 if (EFI_ERROR(Status
)) {
909 Status
= NvmeEnableController (Private
);
910 if (EFI_ERROR(Status
)) {
915 // Create one I/O completion queue.
917 Status
= NvmeCreateIoCompletionQueue (Private
);
918 if (EFI_ERROR(Status
)) {
923 // Create one I/O Submission queue.
925 Status
= NvmeCreateIoSubmissionQueue (Private
);
926 if (EFI_ERROR(Status
)) {
931 // Allocate buffer for Identify Controller data
933 Private
->ControllerData
= (NVME_ADMIN_CONTROLLER_DATA
*)AllocateZeroPool (sizeof(NVME_ADMIN_CONTROLLER_DATA
));
935 if (Private
->ControllerData
== NULL
) {
936 return EFI_OUT_OF_RESOURCES
;
940 // Get current Identify Controller Data
942 Status
= NvmeIdentifyController (Private
, Private
->ControllerData
);
944 if (EFI_ERROR(Status
)) {
945 FreePool(Private
->ControllerData
);
946 Private
->ControllerData
= NULL
;
947 return EFI_NOT_FOUND
;
951 // Dump NvmExpress Identify Controller Data
953 Private
->ControllerData
->Sn
[19] = 0;
954 Private
->ControllerData
->Mn
[39] = 0;
955 DEBUG ((EFI_D_INFO
, " == NVME IDENTIFY CONTROLLER DATA ==\n"));
956 DEBUG ((EFI_D_INFO
, " PCI VID : 0x%x\n", Private
->ControllerData
->Vid
));
957 DEBUG ((EFI_D_INFO
, " PCI SSVID : 0x%x\n", Private
->ControllerData
->Ssvid
));
958 DEBUG ((EFI_D_INFO
, " SN : %a\n", (CHAR8
*)(Private
->ControllerData
->Sn
)));
959 DEBUG ((EFI_D_INFO
, " MN : %a\n", (CHAR8
*)(Private
->ControllerData
->Mn
)));
960 DEBUG ((EFI_D_INFO
, " FR : 0x%x\n", *((UINT64
*)Private
->ControllerData
->Fr
)));
961 DEBUG ((EFI_D_INFO
, " RAB : 0x%x\n", Private
->ControllerData
->Rab
));
962 DEBUG ((EFI_D_INFO
, " IEEE : 0x%x\n", *(UINT32
*)Private
->ControllerData
->Ieee_oiu
));
963 DEBUG ((EFI_D_INFO
, " AERL : 0x%x\n", Private
->ControllerData
->Aerl
));
964 DEBUG ((EFI_D_INFO
, " SQES : 0x%x\n", Private
->ControllerData
->Sqes
));
965 DEBUG ((EFI_D_INFO
, " CQES : 0x%x\n", Private
->ControllerData
->Cqes
));
966 DEBUG ((EFI_D_INFO
, " NN : 0x%x\n", Private
->ControllerData
->Nn
));