2 NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows
3 NVM Express specification.
5 Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include "NvmExpress.h"
19 Read Nvm Express controller capability register.
21 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
22 @param Cap The buffer used to store capability register content.
24 @return EFI_SUCCESS Successfully read the controller capability register content.
25 @return EFI_DEVICE_ERROR Fail to read the controller capability register.
29 ReadNvmeControllerCapabilities (
30 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
34 EFI_PCI_IO_PROTOCOL
*PciIo
;
38 PciIo
= Private
->PciIo
;
39 Status
= PciIo
->Mem
.Read (
48 if (EFI_ERROR(Status
)) {
52 WriteUnaligned64 ((UINT64
*)Cap
, Data
);
57 Read Nvm Express controller configuration register.
59 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
60 @param Cc The buffer used to store configuration register content.
62 @return EFI_SUCCESS Successfully read the controller configuration register content.
63 @return EFI_DEVICE_ERROR Fail to read the controller configuration register.
67 ReadNvmeControllerConfiguration (
68 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
72 EFI_PCI_IO_PROTOCOL
*PciIo
;
76 PciIo
= Private
->PciIo
;
77 Status
= PciIo
->Mem
.Read (
86 if (EFI_ERROR(Status
)) {
90 WriteUnaligned32 ((UINT32
*)Cc
, Data
);
95 Write Nvm Express controller configuration register.
97 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
98 @param Cc The buffer used to store the content to be written into configuration register.
100 @return EFI_SUCCESS Successfully write data into the controller configuration register.
101 @return EFI_DEVICE_ERROR Fail to write data into the controller configuration register.
105 WriteNvmeControllerConfiguration (
106 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
110 EFI_PCI_IO_PROTOCOL
*PciIo
;
114 PciIo
= Private
->PciIo
;
115 Data
= ReadUnaligned32 ((UINT32
*)Cc
);
116 Status
= PciIo
->Mem
.Write (
125 if (EFI_ERROR(Status
)) {
129 DEBUG ((EFI_D_INFO
, "Cc.En: %d\n", Cc
->En
));
130 DEBUG ((EFI_D_INFO
, "Cc.Css: %d\n", Cc
->Css
));
131 DEBUG ((EFI_D_INFO
, "Cc.Mps: %d\n", Cc
->Mps
));
132 DEBUG ((EFI_D_INFO
, "Cc.Ams: %d\n", Cc
->Ams
));
133 DEBUG ((EFI_D_INFO
, "Cc.Shn: %d\n", Cc
->Shn
));
134 DEBUG ((EFI_D_INFO
, "Cc.Iosqes: %d\n", Cc
->Iosqes
));
135 DEBUG ((EFI_D_INFO
, "Cc.Iocqes: %d\n", Cc
->Iocqes
));
141 Read Nvm Express controller status register.
143 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
144 @param Csts The buffer used to store status register content.
146 @return EFI_SUCCESS Successfully read the controller status register content.
147 @return EFI_DEVICE_ERROR Fail to read the controller status register.
151 ReadNvmeControllerStatus (
152 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
156 EFI_PCI_IO_PROTOCOL
*PciIo
;
160 PciIo
= Private
->PciIo
;
161 Status
= PciIo
->Mem
.Read (
170 if (EFI_ERROR(Status
)) {
174 WriteUnaligned32 ((UINT32
*)Csts
, Data
);
179 Read Nvm Express admin queue attributes register.
181 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
182 @param Aqa The buffer used to store admin queue attributes register content.
184 @return EFI_SUCCESS Successfully read the admin queue attributes register content.
185 @return EFI_DEVICE_ERROR Fail to read the admin queue attributes register.
189 ReadNvmeAdminQueueAttributes (
190 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
194 EFI_PCI_IO_PROTOCOL
*PciIo
;
198 PciIo
= Private
->PciIo
;
199 Status
= PciIo
->Mem
.Read (
208 if (EFI_ERROR(Status
)) {
212 WriteUnaligned32 ((UINT32
*)Aqa
, Data
);
217 Write Nvm Express admin queue attributes register.
219 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
220 @param Aqa The buffer used to store the content to be written into admin queue attributes register.
222 @return EFI_SUCCESS Successfully write data into the admin queue attributes register.
223 @return EFI_DEVICE_ERROR Fail to write data into the admin queue attributes register.
227 WriteNvmeAdminQueueAttributes (
228 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
232 EFI_PCI_IO_PROTOCOL
*PciIo
;
236 PciIo
= Private
->PciIo
;
237 Data
= ReadUnaligned32 ((UINT32
*)Aqa
);
238 Status
= PciIo
->Mem
.Write (
247 if (EFI_ERROR(Status
)) {
251 DEBUG ((EFI_D_INFO
, "Aqa.Asqs: %d\n", Aqa
->Asqs
));
252 DEBUG ((EFI_D_INFO
, "Aqa.Acqs: %d\n", Aqa
->Acqs
));
258 Read Nvm Express admin submission queue base address register.
260 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
261 @param Asq The buffer used to store admin submission queue base address register content.
263 @return EFI_SUCCESS Successfully read the admin submission queue base address register content.
264 @return EFI_DEVICE_ERROR Fail to read the admin submission queue base address register.
268 ReadNvmeAdminSubmissionQueueBaseAddress (
269 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
273 EFI_PCI_IO_PROTOCOL
*PciIo
;
277 PciIo
= Private
->PciIo
;
278 Status
= PciIo
->Mem
.Read (
287 if (EFI_ERROR(Status
)) {
291 WriteUnaligned64 ((UINT64
*)Asq
, Data
);
296 Write Nvm Express admin submission queue base address register.
298 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
299 @param Asq The buffer used to store the content to be written into admin submission queue base address register.
301 @return EFI_SUCCESS Successfully write data into the admin submission queue base address register.
302 @return EFI_DEVICE_ERROR Fail to write data into the admin submission queue base address register.
306 WriteNvmeAdminSubmissionQueueBaseAddress (
307 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
311 EFI_PCI_IO_PROTOCOL
*PciIo
;
315 PciIo
= Private
->PciIo
;
316 Data
= ReadUnaligned64 ((UINT64
*)Asq
);
318 Status
= PciIo
->Mem
.Write (
327 if (EFI_ERROR(Status
)) {
331 DEBUG ((EFI_D_INFO
, "Asq.Asqb: %lx\n", Asq
->Asqb
));
337 Read Nvm Express admin completion queue base address register.
339 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
340 @param Acq The buffer used to store admin completion queue base address register content.
342 @return EFI_SUCCESS Successfully read the admin completion queue base address register content.
343 @return EFI_DEVICE_ERROR Fail to read the admin completion queue base address register.
347 ReadNvmeAdminCompletionQueueBaseAddress (
348 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
352 EFI_PCI_IO_PROTOCOL
*PciIo
;
356 PciIo
= Private
->PciIo
;
358 Status
= PciIo
->Mem
.Read (
367 if (EFI_ERROR(Status
)) {
371 WriteUnaligned64 ((UINT64
*)Acq
, Data
);
376 Write Nvm Express admin completion queue base address register.
378 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
379 @param Acq The buffer used to store the content to be written into admin completion queue base address register.
381 @return EFI_SUCCESS Successfully write data into the admin completion queue base address register.
382 @return EFI_DEVICE_ERROR Fail to write data into the admin completion queue base address register.
386 WriteNvmeAdminCompletionQueueBaseAddress (
387 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
391 EFI_PCI_IO_PROTOCOL
*PciIo
;
395 PciIo
= Private
->PciIo
;
396 Data
= ReadUnaligned64 ((UINT64
*)Acq
);
398 Status
= PciIo
->Mem
.Write (
407 if (EFI_ERROR(Status
)) {
411 DEBUG ((EFI_D_INFO
, "Acq.Acqb: %lxh\n", Acq
->Acqb
));
417 Disable the Nvm Express controller.
419 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
421 @return EFI_SUCCESS Successfully disable the controller.
422 @return EFI_DEVICE_ERROR Fail to disable the controller.
426 NvmeDisableController (
427 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
437 // Read Controller Configuration Register.
439 Status
= ReadNvmeControllerConfiguration (Private
, &Cc
);
440 if (EFI_ERROR(Status
)) {
447 // Disable the controller.
449 Status
= WriteNvmeControllerConfiguration (Private
, &Cc
);
451 if (EFI_ERROR(Status
)) {
456 // Cap.To specifies max delay time in 500ms increments for Csts.Rdy to transition from 1 to 0 after
457 // Cc.Enable transition from 1 to 0. Loop produces a 1 millisecond delay per itteration, up to 500 * Cap.To.
459 if (Private
->Cap
.To
== 0) {
462 Timeout
= Private
->Cap
.To
;
465 for(Index
= (Timeout
* 500); Index
!= 0; --Index
) {
469 // Check if the controller is initialized
471 Status
= ReadNvmeControllerStatus (Private
, &Csts
);
473 if (EFI_ERROR(Status
)) {
483 Status
= EFI_DEVICE_ERROR
;
486 DEBUG ((EFI_D_INFO
, "NVMe controller is disabled with status [%r].\n", Status
));
491 Enable the Nvm Express controller.
493 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
495 @return EFI_SUCCESS Successfully enable the controller.
496 @return EFI_DEVICE_ERROR Fail to enable the controller.
497 @return EFI_TIMEOUT Fail to enable the controller in given time slot.
501 NvmeEnableController (
502 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
512 // Enable the controller
514 ZeroMem (&Cc
, sizeof (NVME_CC
));
518 Status
= WriteNvmeControllerConfiguration (Private
, &Cc
);
520 if (EFI_ERROR(Status
)) {
525 // Cap.To specifies max delay time in 500ms increments for Csts.Rdy to set after
526 // Cc.Enable. Loop produces a 1 millisecond delay per itteration, up to 500 * Cap.To.
528 if (Private
->Cap
.To
== 0) {
531 Timeout
= Private
->Cap
.To
;
534 for(Index
= (Timeout
* 500); Index
!= 0; --Index
) {
538 // Check if the controller is initialized
540 Status
= ReadNvmeControllerStatus (Private
, &Csts
);
542 if (EFI_ERROR(Status
)) {
552 Status
= EFI_TIMEOUT
;
555 DEBUG ((EFI_D_INFO
, "NVMe controller is enabled with status [%r].\n", Status
));
560 Get identify controller data.
562 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
563 @param Buffer The buffer used to store the identify controller data.
565 @return EFI_SUCCESS Successfully get the identify controller data.
566 @return EFI_DEVICE_ERROR Fail to get the identify controller data.
570 NvmeIdentifyController (
571 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
575 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket
;
576 NVM_EXPRESS_COMMAND Command
;
577 NVM_EXPRESS_RESPONSE Response
;
580 ZeroMem (&CommandPacket
, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET
));
581 ZeroMem (&Command
, sizeof(NVM_EXPRESS_COMMAND
));
582 ZeroMem (&Response
, sizeof(NVM_EXPRESS_RESPONSE
));
584 Command
.Cdw0
.Opcode
= NVME_ADMIN_IDENTIFY_OPC
;
585 Command
.Cdw0
.Cid
= Private
->Cid
[0]++;
587 // According to Nvm Express 1.1 spec Figure 38, When not used, the field shall be cleared to 0h.
588 // For the Identify command, the Namespace Identifier is only used for the Namespace data structure.
592 CommandPacket
.NvmeCmd
= &Command
;
593 CommandPacket
.NvmeResponse
= &Response
;
594 CommandPacket
.TransferBuffer
= Buffer
;
595 CommandPacket
.TransferLength
= sizeof (NVME_ADMIN_CONTROLLER_DATA
);
596 CommandPacket
.CommandTimeout
= NVME_GENERIC_TIMEOUT
;
597 CommandPacket
.QueueId
= NVME_ADMIN_QUEUE
;
599 // Set bit 0 (Cns bit) to 1 to identify a controller
602 Command
.Flags
= CDW10_VALID
;
604 Status
= Private
->Passthru
.PassThru (
616 Get specified identify namespace data.
618 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
619 @param NamespaceId The specified namespace identifier.
620 @param Buffer The buffer used to store the identify namespace data.
622 @return EFI_SUCCESS Successfully get the identify namespace data.
623 @return EFI_DEVICE_ERROR Fail to get the identify namespace data.
627 NvmeIdentifyNamespace (
628 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
,
629 IN UINT32 NamespaceId
,
633 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket
;
634 NVM_EXPRESS_COMMAND Command
;
635 NVM_EXPRESS_RESPONSE Response
;
638 ZeroMem (&CommandPacket
, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET
));
639 ZeroMem (&Command
, sizeof(NVM_EXPRESS_COMMAND
));
640 ZeroMem (&Response
, sizeof(NVM_EXPRESS_RESPONSE
));
642 CommandPacket
.NvmeCmd
= &Command
;
643 CommandPacket
.NvmeResponse
= &Response
;
645 Command
.Cdw0
.Opcode
= NVME_ADMIN_IDENTIFY_OPC
;
646 Command
.Cdw0
.Cid
= Private
->Cid
[0]++;
647 Command
.Nsid
= NamespaceId
;
648 CommandPacket
.TransferBuffer
= Buffer
;
649 CommandPacket
.TransferLength
= sizeof (NVME_ADMIN_NAMESPACE_DATA
);
650 CommandPacket
.CommandTimeout
= NVME_GENERIC_TIMEOUT
;
651 CommandPacket
.QueueId
= NVME_ADMIN_QUEUE
;
653 // Set bit 0 (Cns bit) to 1 to identify a namespace
655 CommandPacket
.NvmeCmd
->Cdw10
= 0;
656 CommandPacket
.NvmeCmd
->Flags
= CDW10_VALID
;
658 Status
= Private
->Passthru
.PassThru (
670 Create io completion queue.
672 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
674 @return EFI_SUCCESS Successfully create io completion queue.
675 @return EFI_DEVICE_ERROR Fail to create io completion queue.
679 NvmeCreateIoCompletionQueue (
680 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
683 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket
;
684 NVM_EXPRESS_COMMAND Command
;
685 NVM_EXPRESS_RESPONSE Response
;
687 NVME_ADMIN_CRIOCQ CrIoCq
;
689 ZeroMem (&CommandPacket
, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET
));
690 ZeroMem (&Command
, sizeof(NVM_EXPRESS_COMMAND
));
691 ZeroMem (&Response
, sizeof(NVM_EXPRESS_RESPONSE
));
692 ZeroMem (&CrIoCq
, sizeof(NVME_ADMIN_CRIOCQ
));
694 CommandPacket
.NvmeCmd
= &Command
;
695 CommandPacket
.NvmeResponse
= &Response
;
697 Command
.Cdw0
.Opcode
= NVME_ADMIN_CRIOCQ_OPC
;
698 Command
.Cdw0
.Cid
= Private
->Cid
[0]++;
699 CommandPacket
.TransferBuffer
= Private
->CqBufferPciAddr
[1];
700 CommandPacket
.TransferLength
= EFI_PAGE_SIZE
;
701 CommandPacket
.CommandTimeout
= NVME_GENERIC_TIMEOUT
;
702 CommandPacket
.QueueId
= NVME_ADMIN_QUEUE
;
704 CrIoCq
.Qid
= NVME_IO_QUEUE
;
705 CrIoCq
.Qsize
= NVME_CCQ_SIZE
;
707 CopyMem (&CommandPacket
.NvmeCmd
->Cdw10
, &CrIoCq
, sizeof (NVME_ADMIN_CRIOCQ
));
708 CommandPacket
.NvmeCmd
->Flags
= CDW10_VALID
| CDW11_VALID
;
710 Status
= Private
->Passthru
.PassThru (
722 Create io submission queue.
724 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
726 @return EFI_SUCCESS Successfully create io submission queue.
727 @return EFI_DEVICE_ERROR Fail to create io submission queue.
731 NvmeCreateIoSubmissionQueue (
732 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
735 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket
;
736 NVM_EXPRESS_COMMAND Command
;
737 NVM_EXPRESS_RESPONSE Response
;
739 NVME_ADMIN_CRIOSQ CrIoSq
;
741 ZeroMem (&CommandPacket
, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET
));
742 ZeroMem (&Command
, sizeof(NVM_EXPRESS_COMMAND
));
743 ZeroMem (&Response
, sizeof(NVM_EXPRESS_RESPONSE
));
744 ZeroMem (&CrIoSq
, sizeof(NVME_ADMIN_CRIOSQ
));
746 CommandPacket
.NvmeCmd
= &Command
;
747 CommandPacket
.NvmeResponse
= &Response
;
749 Command
.Cdw0
.Opcode
= NVME_ADMIN_CRIOSQ_OPC
;
750 Command
.Cdw0
.Cid
= Private
->Cid
[0]++;
751 CommandPacket
.TransferBuffer
= Private
->SqBufferPciAddr
[1];
752 CommandPacket
.TransferLength
= EFI_PAGE_SIZE
;
753 CommandPacket
.CommandTimeout
= NVME_GENERIC_TIMEOUT
;
754 CommandPacket
.QueueId
= NVME_ADMIN_QUEUE
;
756 CrIoSq
.Qid
= NVME_IO_QUEUE
;
757 CrIoSq
.Qsize
= NVME_CSQ_SIZE
;
759 CrIoSq
.Cqid
= NVME_IO_QUEUE
;
761 CopyMem (&CommandPacket
.NvmeCmd
->Cdw10
, &CrIoSq
, sizeof (NVME_ADMIN_CRIOSQ
));
762 CommandPacket
.NvmeCmd
->Flags
= CDW10_VALID
| CDW11_VALID
;
764 Status
= Private
->Passthru
.PassThru (
776 Initialize the Nvm Express controller.
778 @param[in] Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
780 @retval EFI_SUCCESS The NVM Express Controller is initialized successfully.
781 @retval Others A device error occurred while initializing the controller.
786 IN NVME_CONTROLLER_PRIVATE_DATA
*Private
790 EFI_PCI_IO_PROTOCOL
*PciIo
;
797 // Save original PCI attributes and enable this controller.
799 PciIo
= Private
->PciIo
;
800 Status
= PciIo
->Attributes (
802 EfiPciIoAttributeOperationGet
,
804 &Private
->PciAttributes
807 if (EFI_ERROR (Status
)) {
811 Status
= PciIo
->Attributes (
813 EfiPciIoAttributeOperationSupported
,
818 if (!EFI_ERROR (Status
)) {
819 Supports
&= (UINT64
)EFI_PCI_DEVICE_ENABLE
;
820 Status
= PciIo
->Attributes (
822 EfiPciIoAttributeOperationEnable
,
828 if (EFI_ERROR (Status
)) {
829 DEBUG ((EFI_D_INFO
, "NvmeControllerInit: failed to enable controller\n"));
834 // Read the Controller Capabilities register and verify that the NVM command set is supported
836 Status
= ReadNvmeControllerCapabilities (Private
, &Private
->Cap
);
837 if (EFI_ERROR (Status
)) {
841 if (Private
->Cap
.Css
!= 0x01) {
842 DEBUG ((EFI_D_INFO
, "NvmeControllerInit: the controller doesn't support NVMe command set\n"));
843 return EFI_UNSUPPORTED
;
847 // Currently the driver only supports 4k page size.
849 ASSERT ((Private
->Cap
.Mpsmin
+ 12) <= EFI_PAGE_SHIFT
);
854 Status
= NvmeDisableController (Private
);
856 if (EFI_ERROR(Status
)) {
861 // set number of entries admin submission & completion queues.
863 Aqa
.Asqs
= NVME_ASQ_SIZE
;
865 Aqa
.Acqs
= NVME_ACQ_SIZE
;
869 // Address of admin submission queue.
872 Asq
.Asqb
= (UINT64
)(UINTN
)(Private
->BufferPciAddr
) >> 12;
875 // Address of admin completion queue.
878 Acq
.Acqb
= (UINT64
)(UINTN
)(Private
->BufferPciAddr
+ EFI_PAGE_SIZE
) >> 12;
881 // Address of I/O submission & completion queue.
883 Private
->SqBuffer
[0] = (NVME_SQ
*)(UINTN
)(Private
->Buffer
);
884 Private
->SqBufferPciAddr
[0] = (NVME_SQ
*)(UINTN
)(Private
->BufferPciAddr
);
885 Private
->CqBuffer
[0] = (NVME_CQ
*)(UINTN
)(Private
->Buffer
+ 1 * EFI_PAGE_SIZE
);
886 Private
->CqBufferPciAddr
[0] = (NVME_CQ
*)(UINTN
)(Private
->BufferPciAddr
+ 1 * EFI_PAGE_SIZE
);
887 Private
->SqBuffer
[1] = (NVME_SQ
*)(UINTN
)(Private
->Buffer
+ 2 * EFI_PAGE_SIZE
);
888 Private
->SqBufferPciAddr
[1] = (NVME_SQ
*)(UINTN
)(Private
->BufferPciAddr
+ 2 * EFI_PAGE_SIZE
);
889 Private
->CqBuffer
[1] = (NVME_CQ
*)(UINTN
)(Private
->Buffer
+ 3 * EFI_PAGE_SIZE
);
890 Private
->CqBufferPciAddr
[1] = (NVME_CQ
*)(UINTN
)(Private
->BufferPciAddr
+ 3 * EFI_PAGE_SIZE
);
892 DEBUG ((EFI_D_INFO
, "Private->Buffer = [%016X]\n", (UINT64
)(UINTN
)Private
->Buffer
));
893 DEBUG ((EFI_D_INFO
, "Admin Submission Queue size (Aqa.Asqs) = [%08X]\n", Aqa
.Asqs
));
894 DEBUG ((EFI_D_INFO
, "Admin Completion Queue size (Aqa.Acqs) = [%08X]\n", Aqa
.Acqs
));
895 DEBUG ((EFI_D_INFO
, "Admin Submission Queue (SqBuffer[0]) = [%016X]\n", Private
->SqBuffer
[0]));
896 DEBUG ((EFI_D_INFO
, "Admin Completion Queue (CqBuffer[0]) = [%016X]\n", Private
->CqBuffer
[0]));
897 DEBUG ((EFI_D_INFO
, "I/O Submission Queue (SqBuffer[1]) = [%016X]\n", Private
->SqBuffer
[1]));
898 DEBUG ((EFI_D_INFO
, "I/O Completion Queue (CqBuffer[1]) = [%016X]\n", Private
->CqBuffer
[1]));
901 // Program admin queue attributes.
903 Status
= WriteNvmeAdminQueueAttributes (Private
, &Aqa
);
905 if (EFI_ERROR(Status
)) {
910 // Program admin submission queue address.
912 Status
= WriteNvmeAdminSubmissionQueueBaseAddress (Private
, &Asq
);
914 if (EFI_ERROR(Status
)) {
919 // Program admin completion queue address.
921 Status
= WriteNvmeAdminCompletionQueueBaseAddress (Private
, &Acq
);
923 if (EFI_ERROR(Status
)) {
927 Status
= NvmeEnableController (Private
);
928 if (EFI_ERROR(Status
)) {
933 // Create one I/O completion queue.
935 Status
= NvmeCreateIoCompletionQueue (Private
);
936 if (EFI_ERROR(Status
)) {
941 // Create one I/O Submission queue.
943 Status
= NvmeCreateIoSubmissionQueue (Private
);
944 if (EFI_ERROR(Status
)) {
949 // Allocate buffer for Identify Controller data
951 Private
->ControllerData
= (NVME_ADMIN_CONTROLLER_DATA
*)AllocateZeroPool (sizeof(NVME_ADMIN_CONTROLLER_DATA
));
953 if (Private
->ControllerData
== NULL
) {
954 return EFI_OUT_OF_RESOURCES
;
958 // Get current Identify Controller Data
960 Status
= NvmeIdentifyController (Private
, Private
->ControllerData
);
962 if (EFI_ERROR(Status
)) {
963 FreePool(Private
->ControllerData
);
964 Private
->ControllerData
= NULL
;
965 return EFI_NOT_FOUND
;
969 // Dump NvmExpress Identify Controller Data
971 Private
->ControllerData
->Sn
[19] = 0;
972 Private
->ControllerData
->Mn
[39] = 0;
973 DEBUG ((EFI_D_INFO
, " == NVME IDENTIFY CONTROLLER DATA ==\n"));
974 DEBUG ((EFI_D_INFO
, " PCI VID : 0x%x\n", Private
->ControllerData
->Vid
));
975 DEBUG ((EFI_D_INFO
, " PCI SSVID : 0x%x\n", Private
->ControllerData
->Ssvid
));
976 DEBUG ((EFI_D_INFO
, " SN : %a\n", (CHAR8
*)(Private
->ControllerData
->Sn
)));
977 DEBUG ((EFI_D_INFO
, " MN : %a\n", (CHAR8
*)(Private
->ControllerData
->Mn
)));
978 DEBUG ((EFI_D_INFO
, " FR : 0x%x\n", *((UINT64
*)Private
->ControllerData
->Fr
)));
979 DEBUG ((EFI_D_INFO
, " RAB : 0x%x\n", Private
->ControllerData
->Rab
));
980 DEBUG ((EFI_D_INFO
, " IEEE : 0x%x\n", *(UINT32
*)Private
->ControllerData
->Ieee_oui
));
981 DEBUG ((EFI_D_INFO
, " AERL : 0x%x\n", Private
->ControllerData
->Aerl
));
982 DEBUG ((EFI_D_INFO
, " SQES : 0x%x\n", Private
->ControllerData
->Sqes
));
983 DEBUG ((EFI_D_INFO
, " CQES : 0x%x\n", Private
->ControllerData
->Cqes
));
984 DEBUG ((EFI_D_INFO
, " NN : 0x%x\n", Private
->ControllerData
->Nn
));