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[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressPassthru.c
1 /** @file
2 NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows
3 NVM Express specification.
4
5 (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
6 Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php.
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #include "NvmExpress.h"
18
19 /**
20 Dump the execution status from a given completion queue entry.
21
22 @param[in] Cq A pointer to the NVME_CQ item.
23
24 **/
25 VOID
26 NvmeDumpStatus (
27 IN NVME_CQ *Cq
28 )
29 {
30 DEBUG ((EFI_D_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));
31
32 DEBUG ((EFI_D_VERBOSE, " SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));
33
34 DEBUG ((EFI_D_VERBOSE, " NVMe Cmd Execution Result - "));
35
36 switch (Cq->Sct) {
37 case 0x0:
38 switch (Cq->Sc) {
39 case 0x0:
40 DEBUG ((EFI_D_VERBOSE, "Successful Completion\n"));
41 break;
42 case 0x1:
43 DEBUG ((EFI_D_VERBOSE, "Invalid Command Opcode\n"));
44 break;
45 case 0x2:
46 DEBUG ((EFI_D_VERBOSE, "Invalid Field in Command\n"));
47 break;
48 case 0x3:
49 DEBUG ((EFI_D_VERBOSE, "Command ID Conflict\n"));
50 break;
51 case 0x4:
52 DEBUG ((EFI_D_VERBOSE, "Data Transfer Error\n"));
53 break;
54 case 0x5:
55 DEBUG ((EFI_D_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));
56 break;
57 case 0x6:
58 DEBUG ((EFI_D_VERBOSE, "Internal Device Error\n"));
59 break;
60 case 0x7:
61 DEBUG ((EFI_D_VERBOSE, "Command Abort Requested\n"));
62 break;
63 case 0x8:
64 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to SQ Deletion\n"));
65 break;
66 case 0x9:
67 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Failed Fused Command\n"));
68 break;
69 case 0xA:
70 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Missing Fused Command\n"));
71 break;
72 case 0xB:
73 DEBUG ((EFI_D_VERBOSE, "Invalid Namespace or Format\n"));
74 break;
75 case 0xC:
76 DEBUG ((EFI_D_VERBOSE, "Command Sequence Error\n"));
77 break;
78 case 0xD:
79 DEBUG ((EFI_D_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));
80 break;
81 case 0xE:
82 DEBUG ((EFI_D_VERBOSE, "Invalid Number of SGL Descriptors\n"));
83 break;
84 case 0xF:
85 DEBUG ((EFI_D_VERBOSE, "Data SGL Length Invalid\n"));
86 break;
87 case 0x10:
88 DEBUG ((EFI_D_VERBOSE, "Metadata SGL Length Invalid\n"));
89 break;
90 case 0x11:
91 DEBUG ((EFI_D_VERBOSE, "SGL Descriptor Type Invalid\n"));
92 break;
93 case 0x80:
94 DEBUG ((EFI_D_VERBOSE, "LBA Out of Range\n"));
95 break;
96 case 0x81:
97 DEBUG ((EFI_D_VERBOSE, "Capacity Exceeded\n"));
98 break;
99 case 0x82:
100 DEBUG ((EFI_D_VERBOSE, "Namespace Not Ready\n"));
101 break;
102 case 0x83:
103 DEBUG ((EFI_D_VERBOSE, "Reservation Conflict\n"));
104 break;
105 }
106 break;
107
108 case 0x1:
109 switch (Cq->Sc) {
110 case 0x0:
111 DEBUG ((EFI_D_VERBOSE, "Completion Queue Invalid\n"));
112 break;
113 case 0x1:
114 DEBUG ((EFI_D_VERBOSE, "Invalid Queue Identifier\n"));
115 break;
116 case 0x2:
117 DEBUG ((EFI_D_VERBOSE, "Maximum Queue Size Exceeded\n"));
118 break;
119 case 0x3:
120 DEBUG ((EFI_D_VERBOSE, "Abort Command Limit Exceeded\n"));
121 break;
122 case 0x5:
123 DEBUG ((EFI_D_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));
124 break;
125 case 0x6:
126 DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Slot\n"));
127 break;
128 case 0x7:
129 DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Image\n"));
130 break;
131 case 0x8:
132 DEBUG ((EFI_D_VERBOSE, "Invalid Interrupt Vector\n"));
133 break;
134 case 0x9:
135 DEBUG ((EFI_D_VERBOSE, "Invalid Log Page\n"));
136 break;
137 case 0xA:
138 DEBUG ((EFI_D_VERBOSE, "Invalid Format\n"));
139 break;
140 case 0xB:
141 DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires Conventional Reset\n"));
142 break;
143 case 0xC:
144 DEBUG ((EFI_D_VERBOSE, "Invalid Queue Deletion\n"));
145 break;
146 case 0xD:
147 DEBUG ((EFI_D_VERBOSE, "Feature Identifier Not Saveable\n"));
148 break;
149 case 0xE:
150 DEBUG ((EFI_D_VERBOSE, "Feature Not Changeable\n"));
151 break;
152 case 0xF:
153 DEBUG ((EFI_D_VERBOSE, "Feature Not Namespace Specific\n"));
154 break;
155 case 0x10:
156 DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));
157 break;
158 case 0x80:
159 DEBUG ((EFI_D_VERBOSE, "Conflicting Attributes\n"));
160 break;
161 case 0x81:
162 DEBUG ((EFI_D_VERBOSE, "Invalid Protection Information\n"));
163 break;
164 case 0x82:
165 DEBUG ((EFI_D_VERBOSE, "Attempted Write to Read Only Range\n"));
166 break;
167 }
168 break;
169
170 case 0x2:
171 switch (Cq->Sc) {
172 case 0x80:
173 DEBUG ((EFI_D_VERBOSE, "Write Fault\n"));
174 break;
175 case 0x81:
176 DEBUG ((EFI_D_VERBOSE, "Unrecovered Read Error\n"));
177 break;
178 case 0x82:
179 DEBUG ((EFI_D_VERBOSE, "End-to-end Guard Check Error\n"));
180 break;
181 case 0x83:
182 DEBUG ((EFI_D_VERBOSE, "End-to-end Application Tag Check Error\n"));
183 break;
184 case 0x84:
185 DEBUG ((EFI_D_VERBOSE, "End-to-end Reference Tag Check Error\n"));
186 break;
187 case 0x85:
188 DEBUG ((EFI_D_VERBOSE, "Compare Failure\n"));
189 break;
190 case 0x86:
191 DEBUG ((EFI_D_VERBOSE, "Access Denied\n"));
192 break;
193 }
194 break;
195
196 default:
197 break;
198 }
199 }
200
201 /**
202 Create PRP lists for data transfer which is larger than 2 memory pages.
203 Note here we calcuate the number of required PRP lists and allocate them at one time.
204
205 @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.
206 @param[in] PhysicalAddr The physical base address of data buffer.
207 @param[in] Pages The number of pages to be transfered.
208 @param[out] PrpListHost The host base address of PRP lists.
209 @param[in,out] PrpListNo The number of PRP List.
210 @param[out] Mapping The mapping value returned from PciIo.Map().
211
212 @retval The pointer to the first PRP List of the PRP lists.
213
214 **/
215 VOID*
216 NvmeCreatePrpList (
217 IN EFI_PCI_IO_PROTOCOL *PciIo,
218 IN EFI_PHYSICAL_ADDRESS PhysicalAddr,
219 IN UINTN Pages,
220 OUT VOID **PrpListHost,
221 IN OUT UINTN *PrpListNo,
222 OUT VOID **Mapping
223 )
224 {
225 UINTN PrpEntryNo;
226 UINT64 PrpListBase;
227 UINTN PrpListIndex;
228 UINTN PrpEntryIndex;
229 UINT64 Remainder;
230 EFI_PHYSICAL_ADDRESS PrpListPhyAddr;
231 UINTN Bytes;
232 EFI_STATUS Status;
233
234 //
235 // The number of Prp Entry in a memory page.
236 //
237 PrpEntryNo = EFI_PAGE_SIZE / sizeof (UINT64);
238
239 //
240 // Calculate total PrpList number.
241 //
242 *PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo - 1, &Remainder);
243 if (*PrpListNo == 0) {
244 *PrpListNo = 1;
245 } else if ((Remainder != 0) && (Remainder != 1)) {
246 *PrpListNo += 1;
247 } else if (Remainder == 1) {
248 Remainder = PrpEntryNo;
249 } else if (Remainder == 0) {
250 Remainder = PrpEntryNo - 1;
251 }
252
253 Status = PciIo->AllocateBuffer (
254 PciIo,
255 AllocateAnyPages,
256 EfiBootServicesData,
257 *PrpListNo,
258 PrpListHost,
259 0
260 );
261
262 if (EFI_ERROR (Status)) {
263 return NULL;
264 }
265
266 Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);
267 Status = PciIo->Map (
268 PciIo,
269 EfiPciIoOperationBusMasterCommonBuffer,
270 *PrpListHost,
271 &Bytes,
272 &PrpListPhyAddr,
273 Mapping
274 );
275
276 if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (*PrpListNo))) {
277 DEBUG ((EFI_D_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));
278 goto EXIT;
279 }
280 //
281 // Fill all PRP lists except of last one.
282 //
283 ZeroMem (*PrpListHost, Bytes);
284 for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {
285 PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
286
287 for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {
288 if (PrpEntryIndex != PrpEntryNo - 1) {
289 //
290 // Fill all PRP entries except of last one.
291 //
292 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
293 PhysicalAddr += EFI_PAGE_SIZE;
294 } else {
295 //
296 // Fill last PRP entries with next PRP List pointer.
297 //
298 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;
299 }
300 }
301 }
302 //
303 // Fill last PRP list.
304 //
305 PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
306 for (PrpEntryIndex = 0; PrpEntryIndex < Remainder; ++PrpEntryIndex) {
307 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
308 PhysicalAddr += EFI_PAGE_SIZE;
309 }
310
311 return (VOID*)(UINTN)PrpListPhyAddr;
312
313 EXIT:
314 PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);
315 return NULL;
316 }
317
318
319 /**
320 Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports
321 both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking
322 I/O functionality is optional.
323
324
325 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
326 @param[in] NamespaceId A 32 bit namespace ID as defined in the NVMe specification to which the NVM Express Command
327 Packet will be sent. A value of 0 denotes the NVM Express controller, a value of all 0xFF's
328 (all bytes are 0xFF) in the namespace ID specifies that the command packet should be sent to
329 all valid namespaces.
330 @param[in,out] Packet A pointer to the NVM Express Command Packet.
331 @param[in] Event If non-blocking I/O is not supported then Event is ignored, and blocking I/O is performed.
332 If Event is NULL, then blocking I/O is performed. If Event is not NULL and non-blocking I/O
333 is supported, then non-blocking I/O is performed, and Event will be signaled when the NVM
334 Express Command Packet completes.
335
336 @retval EFI_SUCCESS The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred
337 to, or from DataBuffer.
338 @retval EFI_BAD_BUFFER_SIZE The NVM Express Command Packet was not executed. The number of bytes that could be transferred
339 is returned in TransferLength.
340 @retval EFI_NOT_READY The NVM Express Command Packet could not be sent because the controller is not ready. The caller
341 may retry again later.
342 @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the NVM Express Command Packet.
343 @retval EFI_INVALID_PARAMETER NamespaceId or the contents of EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM
344 Express Command Packet was not sent, so no additional status information is available.
345 @retval EFI_UNSUPPORTED The command described by the NVM Express Command Packet is not supported by the NVM Express
346 controller. The NVM Express Command Packet was not sent so no additional status information
347 is available.
348 @retval EFI_TIMEOUT A timeout occurred while waiting for the NVM Express Command Packet to execute.
349
350 **/
351 EFI_STATUS
352 EFIAPI
353 NvmExpressPassThru (
354 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
355 IN UINT32 NamespaceId,
356 IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,
357 IN EFI_EVENT Event OPTIONAL
358 )
359 {
360 NVME_CONTROLLER_PRIVATE_DATA *Private;
361 EFI_STATUS Status;
362 EFI_PCI_IO_PROTOCOL *PciIo;
363 NVME_SQ *Sq;
364 NVME_CQ *Cq;
365 UINT16 QueueId;
366 UINT32 Bytes;
367 UINT16 Offset;
368 EFI_EVENT TimerEvent;
369 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
370 EFI_PHYSICAL_ADDRESS PhyAddr;
371 VOID *MapData;
372 VOID *MapMeta;
373 VOID *MapPrpList;
374 UINTN MapLength;
375 UINT64 *Prp;
376 VOID *PrpListHost;
377 UINTN PrpListNo;
378 UINT32 IoAlign;
379 UINT32 Data;
380 NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;
381 EFI_TPL OldTpl;
382
383 //
384 // check the data fields in Packet parameter.
385 //
386 if ((This == NULL) || (Packet == NULL)) {
387 return EFI_INVALID_PARAMETER;
388 }
389
390 if ((Packet->NvmeCmd == NULL) || (Packet->NvmeCompletion == NULL)) {
391 return EFI_INVALID_PARAMETER;
392 }
393
394 if (Packet->QueueType != NVME_ADMIN_QUEUE && Packet->QueueType != NVME_IO_QUEUE) {
395 return EFI_INVALID_PARAMETER;
396 }
397
398 //
399 // Buffer alignment check for TransferBuffer & MetadataBuffer.
400 //
401 IoAlign = This->Mode->IoAlign;
402 if (IoAlign > 0 && (((UINTN) Packet->TransferBuffer & (IoAlign - 1)) != 0)) {
403 return EFI_INVALID_PARAMETER;
404 }
405
406 if (IoAlign > 0 && (((UINTN) Packet->MetadataBuffer & (IoAlign - 1)) != 0)) {
407 return EFI_INVALID_PARAMETER;
408 }
409
410 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
411 PciIo = Private->PciIo;
412 MapData = NULL;
413 MapMeta = NULL;
414 MapPrpList = NULL;
415 PrpListHost = NULL;
416 PrpListNo = 0;
417 Prp = NULL;
418 TimerEvent = NULL;
419 Status = EFI_SUCCESS;
420
421 if (Packet->QueueType == NVME_ADMIN_QUEUE) {
422 QueueId = 0;
423 } else {
424 if (Event == NULL) {
425 QueueId = 1;
426 } else {
427 QueueId = 2;
428
429 //
430 // Submission queue full check.
431 //
432 if ((Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1) ==
433 Private->AsyncSqHead) {
434 return EFI_NOT_READY;
435 }
436 }
437 }
438 Sq = Private->SqBuffer[QueueId] + Private->SqTdbl[QueueId].Sqt;
439 Cq = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;
440
441 if (Packet->NvmeCmd->Nsid != NamespaceId) {
442 return EFI_INVALID_PARAMETER;
443 }
444
445 ZeroMem (Sq, sizeof (NVME_SQ));
446 Sq->Opc = (UINT8)Packet->NvmeCmd->Cdw0.Opcode;
447 Sq->Fuse = (UINT8)Packet->NvmeCmd->Cdw0.FusedOperation;
448 Sq->Cid = Private->Cid[QueueId]++;
449 Sq->Nsid = Packet->NvmeCmd->Nsid;
450
451 //
452 // Currently we only support PRP for data transfer, SGL is NOT supported.
453 //
454 ASSERT (Sq->Psdt == 0);
455 if (Sq->Psdt != 0) {
456 DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));
457 return EFI_UNSUPPORTED;
458 }
459
460 Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;
461 //
462 // If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.
463 // Note here we don't handle data buffer for CreateIOSubmitionQueue and CreateIOCompletionQueue cmds because
464 // these two cmds are special which requires their data buffer must support simultaneous access by both the
465 // processor and a PCI Bus Master. It's caller's responsbility to ensure this.
466 //
467 if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_CMD) && (Sq->Opc != NVME_ADMIN_CRIOSQ_CMD)) {
468 if ((Sq->Opc & BIT0) != 0) {
469 Flag = EfiPciIoOperationBusMasterRead;
470 } else {
471 Flag = EfiPciIoOperationBusMasterWrite;
472 }
473
474 MapLength = Packet->TransferLength;
475 Status = PciIo->Map (
476 PciIo,
477 Flag,
478 Packet->TransferBuffer,
479 &MapLength,
480 &PhyAddr,
481 &MapData
482 );
483 if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {
484 return EFI_OUT_OF_RESOURCES;
485 }
486
487 Sq->Prp[0] = PhyAddr;
488 Sq->Prp[1] = 0;
489
490 MapLength = Packet->MetadataLength;
491 if(Packet->MetadataBuffer != NULL) {
492 MapLength = Packet->MetadataLength;
493 Status = PciIo->Map (
494 PciIo,
495 Flag,
496 Packet->MetadataBuffer,
497 &MapLength,
498 &PhyAddr,
499 &MapMeta
500 );
501 if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {
502 PciIo->Unmap (
503 PciIo,
504 MapData
505 );
506
507 return EFI_OUT_OF_RESOURCES;
508 }
509 Sq->Mptr = PhyAddr;
510 }
511 }
512 //
513 // If the buffer size spans more than two memory pages (page size as defined in CC.Mps),
514 // then build a PRP list in the second PRP submission queue entry.
515 //
516 Offset = ((UINT16)Sq->Prp[0]) & (EFI_PAGE_SIZE - 1);
517 Bytes = Packet->TransferLength;
518
519 if ((Offset + Bytes) > (EFI_PAGE_SIZE * 2)) {
520 //
521 // Create PrpList for remaining data buffer.
522 //
523 PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
524 Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);
525 if (Prp == NULL) {
526 goto EXIT;
527 }
528
529 Sq->Prp[1] = (UINT64)(UINTN)Prp;
530 } else if ((Offset + Bytes) > EFI_PAGE_SIZE) {
531 Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
532 }
533
534 if(Packet->NvmeCmd->Flags & CDW2_VALID) {
535 Sq->Rsvd2 = (UINT64)Packet->NvmeCmd->Cdw2;
536 }
537 if(Packet->NvmeCmd->Flags & CDW3_VALID) {
538 Sq->Rsvd2 |= LShiftU64 ((UINT64)Packet->NvmeCmd->Cdw3, 32);
539 }
540 if(Packet->NvmeCmd->Flags & CDW10_VALID) {
541 Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;
542 }
543 if(Packet->NvmeCmd->Flags & CDW11_VALID) {
544 Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;
545 }
546 if(Packet->NvmeCmd->Flags & CDW12_VALID) {
547 Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;
548 }
549 if(Packet->NvmeCmd->Flags & CDW13_VALID) {
550 Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;
551 }
552 if(Packet->NvmeCmd->Flags & CDW14_VALID) {
553 Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;
554 }
555 if(Packet->NvmeCmd->Flags & CDW15_VALID) {
556 Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;
557 }
558
559 //
560 // Ring the submission queue doorbell.
561 //
562 if (Event != NULL) {
563 Private->SqTdbl[QueueId].Sqt =
564 (Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1);
565 } else {
566 Private->SqTdbl[QueueId].Sqt ^= 1;
567 }
568 Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[QueueId]);
569 PciIo->Mem.Write (
570 PciIo,
571 EfiPciIoWidthUint32,
572 NVME_BAR,
573 NVME_SQTDBL_OFFSET(QueueId, Private->Cap.Dstrd),
574 1,
575 &Data
576 );
577
578 //
579 // For non-blocking requests, return directly if the command is placed
580 // in the submission queue.
581 //
582 if (Event != NULL) {
583 AsyncRequest = AllocateZeroPool (sizeof (NVME_PASS_THRU_ASYNC_REQ));
584 if (AsyncRequest == NULL) {
585 Status = EFI_DEVICE_ERROR;
586 goto EXIT;
587 }
588
589 AsyncRequest->Signature = NVME_PASS_THRU_ASYNC_REQ_SIG;
590 AsyncRequest->Packet = Packet;
591 AsyncRequest->CommandId = Sq->Cid;
592 AsyncRequest->CallerEvent = Event;
593
594 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
595 InsertTailList (&Private->AsyncPassThruQueue, &AsyncRequest->Link);
596 gBS->RestoreTPL (OldTpl);
597
598 return EFI_SUCCESS;
599 }
600
601 Status = gBS->CreateEvent (
602 EVT_TIMER,
603 TPL_CALLBACK,
604 NULL,
605 NULL,
606 &TimerEvent
607 );
608 if (EFI_ERROR (Status)) {
609 goto EXIT;
610 }
611
612 Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);
613
614 if (EFI_ERROR(Status)) {
615 goto EXIT;
616 }
617
618 //
619 // Wait for completion queue to get filled in.
620 //
621 Status = EFI_TIMEOUT;
622 while (EFI_ERROR (gBS->CheckEvent (TimerEvent))) {
623 if (Cq->Pt != Private->Pt[QueueId]) {
624 Status = EFI_SUCCESS;
625 break;
626 }
627 }
628
629 //
630 // Check the NVMe cmd execution result
631 //
632 if (Status != EFI_TIMEOUT) {
633 if ((Cq->Sct == 0) && (Cq->Sc == 0)) {
634 Status = EFI_SUCCESS;
635 } else {
636 Status = EFI_DEVICE_ERROR;
637 //
638 // Copy the Respose Queue entry for this command to the callers response buffer
639 //
640 CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));
641
642 //
643 // Dump every completion entry status for debugging.
644 //
645 DEBUG_CODE_BEGIN();
646 NvmeDumpStatus(Cq);
647 DEBUG_CODE_END();
648 }
649 }
650
651 if ((Private->CqHdbl[QueueId].Cqh ^= 1) == 0) {
652 Private->Pt[QueueId] ^= 1;
653 }
654
655 Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]);
656 PciIo->Mem.Write (
657 PciIo,
658 EfiPciIoWidthUint32,
659 NVME_BAR,
660 NVME_CQHDBL_OFFSET(QueueId, Private->Cap.Dstrd),
661 1,
662 &Data
663 );
664
665 EXIT:
666 if (MapData != NULL) {
667 PciIo->Unmap (
668 PciIo,
669 MapData
670 );
671 }
672
673 if (MapMeta != NULL) {
674 PciIo->Unmap (
675 PciIo,
676 MapMeta
677 );
678 }
679
680 if (MapPrpList != NULL) {
681 PciIo->Unmap (
682 PciIo,
683 MapPrpList
684 );
685 }
686
687 if (Prp != NULL) {
688 PciIo->FreeBuffer (PciIo, PrpListNo, PrpListHost);
689 }
690
691 if (TimerEvent != NULL) {
692 gBS->CloseEvent (TimerEvent);
693 }
694 return Status;
695 }
696
697 /**
698 Used to retrieve the next namespace ID for this NVM Express controller.
699
700 The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves the next valid
701 namespace ID on this NVM Express controller.
702
703 If on input the value pointed to by NamespaceId is 0xFFFFFFFF, then the first valid namespace
704 ID defined on the NVM Express controller is returned in the location pointed to by NamespaceId
705 and a status of EFI_SUCCESS is returned.
706
707 If on input the value pointed to by NamespaceId is an invalid namespace ID other than 0xFFFFFFFF,
708 then EFI_INVALID_PARAMETER is returned.
709
710 If on input the value pointed to by NamespaceId is a valid namespace ID, then the next valid
711 namespace ID on the NVM Express controller is returned in the location pointed to by NamespaceId,
712 and EFI_SUCCESS is returned.
713
714 If the value pointed to by NamespaceId is the namespace ID of the last namespace on the NVM
715 Express controller, then EFI_NOT_FOUND is returned.
716
717 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
718 @param[in,out] NamespaceId On input, a pointer to a legal NamespaceId for an NVM Express
719 namespace present on the NVM Express controller. On output, a
720 pointer to the next NamespaceId of an NVM Express namespace on
721 an NVM Express controller. An input value of 0xFFFFFFFF retrieves
722 the first NamespaceId for an NVM Express namespace present on an
723 NVM Express controller.
724
725 @retval EFI_SUCCESS The Namespace ID of the next Namespace was returned.
726 @retval EFI_NOT_FOUND There are no more namespaces defined on this controller.
727 @retval EFI_INVALID_PARAMETER NamespaceId is an invalid value other than 0xFFFFFFFF.
728
729 **/
730 EFI_STATUS
731 EFIAPI
732 NvmExpressGetNextNamespace (
733 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
734 IN OUT UINT32 *NamespaceId
735 )
736 {
737 NVME_CONTROLLER_PRIVATE_DATA *Private;
738 NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
739 UINT32 NextNamespaceId;
740 EFI_STATUS Status;
741
742 if ((This == NULL) || (NamespaceId == NULL)) {
743 return EFI_INVALID_PARAMETER;
744 }
745
746 NamespaceData = NULL;
747 Status = EFI_NOT_FOUND;
748
749 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
750 //
751 // If the NamespaceId input value is 0xFFFFFFFF, then get the first valid namespace ID
752 //
753 if (*NamespaceId == 0xFFFFFFFF) {
754 //
755 // Start with the first namespace ID
756 //
757 NextNamespaceId = 1;
758 //
759 // Allocate buffer for Identify Namespace data.
760 //
761 NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
762
763 if (NamespaceData == NULL) {
764 return EFI_NOT_FOUND;
765 }
766
767 Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
768 if (EFI_ERROR(Status)) {
769 goto Done;
770 }
771
772 *NamespaceId = NextNamespaceId;
773 } else {
774 if (*NamespaceId > Private->ControllerData->Nn) {
775 return EFI_INVALID_PARAMETER;
776 }
777
778 NextNamespaceId = *NamespaceId + 1;
779 if (NextNamespaceId > Private->ControllerData->Nn) {
780 return EFI_NOT_FOUND;
781 }
782
783 //
784 // Allocate buffer for Identify Namespace data.
785 //
786 NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
787 if (NamespaceData == NULL) {
788 return EFI_NOT_FOUND;
789 }
790
791 Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
792 if (EFI_ERROR(Status)) {
793 goto Done;
794 }
795
796 *NamespaceId = NextNamespaceId;
797 }
798
799 Done:
800 if (NamespaceData != NULL) {
801 FreePool(NamespaceData);
802 }
803
804 return Status;
805 }
806
807 /**
808 Used to translate a device path node to a namespace ID.
809
810 The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() function determines the namespace ID associated with the
811 namespace described by DevicePath.
812
813 If DevicePath is a device path node type that the NVM Express Pass Thru driver supports, then the NVM Express
814 Pass Thru driver will attempt to translate the contents DevicePath into a namespace ID.
815
816 If this translation is successful, then that namespace ID is returned in NamespaceId, and EFI_SUCCESS is returned
817
818 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
819 @param[in] DevicePath A pointer to the device path node that describes an NVM Express namespace on
820 the NVM Express controller.
821 @param[out] NamespaceId The NVM Express namespace ID contained in the device path node.
822
823 @retval EFI_SUCCESS DevicePath was successfully translated to NamespaceId.
824 @retval EFI_INVALID_PARAMETER If DevicePath or NamespaceId are NULL, then EFI_INVALID_PARAMETER is returned.
825 @retval EFI_UNSUPPORTED If DevicePath is not a device path node type that the NVM Express Pass Thru driver
826 supports, then EFI_UNSUPPORTED is returned.
827 @retval EFI_NOT_FOUND If DevicePath is a device path node type that the NVM Express Pass Thru driver
828 supports, but there is not a valid translation from DevicePath to a namespace ID,
829 then EFI_NOT_FOUND is returned.
830 **/
831 EFI_STATUS
832 EFIAPI
833 NvmExpressGetNamespace (
834 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
835 IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
836 OUT UINT32 *NamespaceId
837 )
838 {
839 NVME_NAMESPACE_DEVICE_PATH *Node;
840 NVME_CONTROLLER_PRIVATE_DATA *Private;
841
842 if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL)) {
843 return EFI_INVALID_PARAMETER;
844 }
845
846 if (DevicePath->Type != MESSAGING_DEVICE_PATH) {
847 return EFI_UNSUPPORTED;
848 }
849
850 Node = (NVME_NAMESPACE_DEVICE_PATH *)DevicePath;
851 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
852
853 if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {
854 if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {
855 return EFI_NOT_FOUND;
856 }
857
858 //
859 // Check NamespaceId in the device path node is valid or not.
860 //
861 if ((Node->NamespaceId == 0) ||
862 (Node->NamespaceId > Private->ControllerData->Nn)) {
863 return EFI_NOT_FOUND;
864 }
865
866 *NamespaceId = Node->NamespaceId;
867
868 return EFI_SUCCESS;
869 } else {
870 return EFI_UNSUPPORTED;
871 }
872 }
873
874 /**
875 Used to allocate and build a device path node for an NVM Express namespace on an NVM Express controller.
876
877 The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device
878 path node for the NVM Express namespace specified by NamespaceId.
879
880 If the NamespaceId is not valid, then EFI_NOT_FOUND is returned.
881
882 If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.
883
884 If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.
885
886 Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are
887 initialized to describe the NVM Express namespace specified by NamespaceId, and EFI_SUCCESS is returned.
888
889 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
890 @param[in] NamespaceId The NVM Express namespace ID for which a device path node is to be
891 allocated and built. Caller must set the NamespaceId to zero if the
892 device path node will contain a valid UUID.
893 @param[in,out] DevicePath A pointer to a single device path node that describes the NVM Express
894 namespace specified by NamespaceId. This function is responsible for
895 allocating the buffer DevicePath with the boot service AllocatePool().
896 It is the caller's responsibility to free DevicePath when the caller
897 is finished with DevicePath.
898 @retval EFI_SUCCESS The device path node that describes the NVM Express namespace specified
899 by NamespaceId was allocated and returned in DevicePath.
900 @retval EFI_NOT_FOUND The NamespaceId is not valid.
901 @retval EFI_INVALID_PARAMETER DevicePath is NULL.
902 @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate the DevicePath node.
903
904 **/
905 EFI_STATUS
906 EFIAPI
907 NvmExpressBuildDevicePath (
908 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
909 IN UINT32 NamespaceId,
910 IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
911 )
912 {
913 NVME_NAMESPACE_DEVICE_PATH *Node;
914 NVME_CONTROLLER_PRIVATE_DATA *Private;
915 EFI_STATUS Status;
916 NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
917
918 //
919 // Validate parameters
920 //
921 if ((This == NULL) || (DevicePath == NULL)) {
922 return EFI_INVALID_PARAMETER;
923 }
924
925 Status = EFI_SUCCESS;
926 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
927
928 //
929 // Check NamespaceId is valid or not.
930 //
931 if ((NamespaceId == 0) ||
932 (NamespaceId > Private->ControllerData->Nn)) {
933 return EFI_NOT_FOUND;
934 }
935
936 Node = (NVME_NAMESPACE_DEVICE_PATH *)AllocateZeroPool (sizeof (NVME_NAMESPACE_DEVICE_PATH));
937 if (Node == NULL) {
938 return EFI_OUT_OF_RESOURCES;
939 }
940
941 Node->Header.Type = MESSAGING_DEVICE_PATH;
942 Node->Header.SubType = MSG_NVME_NAMESPACE_DP;
943 SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));
944 Node->NamespaceId = NamespaceId;
945
946 //
947 // Allocate a buffer for Identify Namespace data.
948 //
949 NamespaceData = NULL;
950 NamespaceData = AllocateZeroPool(sizeof (NVME_ADMIN_NAMESPACE_DATA));
951 if(NamespaceData == NULL) {
952 Status = EFI_OUT_OF_RESOURCES;
953 goto Exit;
954 }
955
956 //
957 // Get UUID from specified Identify Namespace data.
958 //
959 Status = NvmeIdentifyNamespace (
960 Private,
961 NamespaceId,
962 (VOID *)NamespaceData
963 );
964
965 if (EFI_ERROR(Status)) {
966 goto Exit;
967 }
968
969 Node->NamespaceUuid = NamespaceData->Eui64;
970
971 *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;
972
973 Exit:
974 if(NamespaceData != NULL) {
975 FreePool (NamespaceData);
976 }
977
978 if (EFI_ERROR (Status)) {
979 FreePool (Node);
980 }
981
982 return Status;
983 }
984
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