2 The NvmExpressPei driver is used to manage non-volatile memory subsystem
3 which follows NVM Express specification at PEI phase.
5 Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions
9 of the BSD License which accompanies this distribution. The
10 full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #ifndef _NVM_EXPRESS_PEI_HCI_H_
19 #define _NVM_EXPRESS_PEI_HCI_H_
22 // NVME host controller registers operation definitions
24 #define NVME_GET_CAP(Private, Cap) NvmeMmioRead (Cap, Private->MmioBase + NVME_CAP_OFFSET, sizeof (NVME_CAP))
25 #define NVME_GET_CC(Private, Cc) NvmeMmioRead (Cc, Private->MmioBase + NVME_CC_OFFSET, sizeof (NVME_CC))
26 #define NVME_SET_CC(Private, Cc) NvmeMmioWrite (Private->MmioBase + NVME_CC_OFFSET, Cc, sizeof (NVME_CC))
27 #define NVME_GET_CSTS(Private, Csts) NvmeMmioRead (Csts, Private->MmioBase + NVME_CSTS_OFFSET, sizeof (NVME_CSTS))
28 #define NVME_GET_AQA(Private, Aqa) NvmeMmioRead (Aqa, Private->MmioBase + NVME_AQA_OFFSET, sizeof (NVME_AQA))
29 #define NVME_SET_AQA(Private, Aqa) NvmeMmioWrite (Private->MmioBase + NVME_AQA_OFFSET, Aqa, sizeof (NVME_AQA))
30 #define NVME_GET_ASQ(Private, Asq) NvmeMmioRead (Asq, Private->MmioBase + NVME_ASQ_OFFSET, sizeof (NVME_ASQ))
31 #define NVME_SET_ASQ(Private, Asq) NvmeMmioWrite (Private->MmioBase + NVME_ASQ_OFFSET, Asq, sizeof (NVME_ASQ))
32 #define NVME_GET_ACQ(Private, Acq) NvmeMmioRead (Acq, Private->MmioBase + NVME_ACQ_OFFSET, sizeof (NVME_ACQ))
33 #define NVME_SET_ACQ(Private, Acq) NvmeMmioWrite (Private->MmioBase + NVME_ACQ_OFFSET, Acq, sizeof (NVME_ACQ))
34 #define NVME_GET_VER(Private, Ver) NvmeMmioRead (Ver, Private->MmioBase + NVME_VER_OFFSET, sizeof (NVME_VER))
35 #define NVME_SET_SQTDBL(Private, Qid, Sqtdbl) NvmeMmioWrite (Private->MmioBase + NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd), Sqtdbl, sizeof (NVME_SQTDBL))
36 #define NVME_SET_CQHDBL(Private, Qid, Cqhdbl) NvmeMmioWrite (Private->MmioBase + NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd), Cqhdbl, sizeof (NVME_CQHDBL))
39 // Base memory address enum types
51 // All of base memories are 4K(0x1000) alignment
53 #define ALIGN(v, a) (UINTN)((((v) - 1) | ((a) - 1)) + 1)
54 #define NVME_MEM_BASE(Private) ((UINTN)(Private->Buffer))
55 #define NVME_ASQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
56 #define NVME_ACQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
57 #define NVME_SQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
58 #define NVME_CQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
59 #define NVME_PRP_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
63 Transfer MMIO Data to memory.
65 @param[in,out] MemBuffer Destination: Memory address.
66 @param[in] MmioAddr Source: MMIO address.
67 @param[in] Size Size for read.
69 @retval EFI_SUCCESS MMIO read sucessfully.
74 IN OUT VOID
*MemBuffer
,
80 Transfer memory data to MMIO.
82 @param[in,out] MmioAddr Destination: MMIO address.
83 @param[in] MemBuffer Source: Memory address.
84 @param[in] Size Size for write.
86 @retval EFI_SUCCESS MMIO write sucessfully.
91 IN OUT UINTN MmioAddr
,
97 Get the page offset for specific NVME based memory.
99 @param[in] BaseMemIndex The Index of BaseMem (0-based).
101 @retval - The page count for specific BaseMem Index
105 NvmeBaseMemPageOffset (
106 IN UINTN BaseMemIndex
110 Disable the Nvm Express controller.
112 @param[in] Private The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
114 @return EFI_SUCCESS Successfully disable the controller.
115 @return others Fail to disable the controller.
119 NvmeDisableController (
120 IN PEI_NVME_CONTROLLER_PRIVATE_DATA
*Private
124 Initialize the Nvm Express controller.
126 @param[in] Private The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
128 @retval EFI_SUCCESS The NVM Express Controller is initialized successfully.
129 @retval Others A device error occurred while initializing the controller.
134 IN PEI_NVME_CONTROLLER_PRIVATE_DATA
*Private
138 Get specified identify namespace data.
140 @param[in] Private The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
141 @param[in] NamespaceId The specified namespace identifier.
142 @param[in] Buffer The buffer used to store the identify namespace data.
144 @return EFI_SUCCESS Successfully get the identify namespace data.
145 @return EFI_DEVICE_ERROR Fail to get the identify namespace data.
149 NvmeIdentifyNamespace (
150 IN PEI_NVME_CONTROLLER_PRIVATE_DATA
*Private
,
151 IN UINT32 NamespaceId
,
156 Free the resources allocated by an NVME controller.
158 @param[in] Private The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
162 NvmeFreeControllerResource (
163 IN PEI_NVME_CONTROLLER_PRIVATE_DATA
*Private