MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.h

   1 /** @file
   2   PCI command register operations supporting functions declaration for PCI Bus module.
   3
   4 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
   5 SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #ifndef _EFI_PCI_COMMAND_H_
  10 #define _EFI_PCI_COMMAND_H_
  11
  12 //
  13 // The PCI Command register bits owned by PCI Bus driver.
  14 //
  15 // They should be cleared at the beginning. The other registers
  16 // are owned by chipset, we should not touch them.
  17 //
  18 #define EFI_PCI_COMMAND_BITS_OWNED  (                         \
  19                 EFI_PCI_COMMAND_IO_SPACE                    | \
  20                 EFI_PCI_COMMAND_MEMORY_SPACE                | \
  21                 EFI_PCI_COMMAND_BUS_MASTER                  | \
  22                 EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE | \
  23                 EFI_PCI_COMMAND_VGA_PALETTE_SNOOP           | \
  24                 EFI_PCI_COMMAND_FAST_BACK_TO_BACK             \
  25                 )
  26
  27 //
  28 // The PCI Bridge Control register bits owned by PCI Bus driver.
  29 //
  30 // They should be cleared at the beginning. The other registers
  31 // are owned by chipset, we should not touch them.
  32 //
  33 #define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED  (                  \
  34                 EFI_PCI_BRIDGE_CONTROL_ISA                  | \
  35                 EFI_PCI_BRIDGE_CONTROL_VGA                  | \
  36                 EFI_PCI_BRIDGE_CONTROL_VGA_16               | \
  37                 EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK      \
  38                 )
  39
  40 //
  41 // The PCCard Bridge Control register bits owned by PCI Bus driver.
  42 //
  43 // They should be cleared at the beginning. The other registers
  44 // are owned by chipset, we should not touch them.
  45 //
  46 #define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED  (               \
  47                 EFI_PCI_BRIDGE_CONTROL_ISA                  | \
  48                 EFI_PCI_BRIDGE_CONTROL_VGA                  | \
  49                 EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK      \
  50                 )
  51
  52 #define EFI_GET_REGISTER      1
  53 #define EFI_SET_REGISTER      2
  54 #define EFI_ENABLE_REGISTER   3
  55 #define EFI_DISABLE_REGISTER  4
  56
  57 /**
  58   Operate the PCI register via PciIo function interface.
  59
  60   @param PciIoDevice    Pointer to instance of PCI_IO_DEVICE.
  61   @param Command        Operator command.
  62   @param Offset         The address within the PCI configuration space for the PCI controller.
  63   @param Operation      Type of Operation.
  64   @param PtrCommand     Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER.
  65
  66   @return Status of PciIo operation.
  67
  68 **/
  69 EFI_STATUS
  70 PciOperateRegister (
  71   IN  PCI_IO_DEVICE  *PciIoDevice,
  72   IN  UINT16         Command,
  73   IN  UINT8          Offset,
  74   IN  UINT8          Operation,
  75   OUT UINT16         *PtrCommand
  76   );
  77
  78 /**
  79   Check the capability supporting by given device.
  80
  81   @param PciIoDevice   Pointer to instance of PCI_IO_DEVICE.
  82
  83   @retval TRUE         Capability supported.
  84   @retval FALSE        Capability not supported.
  85
  86 **/
  87 BOOLEAN
  88 PciCapabilitySupport (
  89   IN PCI_IO_DEVICE  *PciIoDevice
  90   );
  91
  92 /**
  93   Locate capability register block per capability ID.
  94
  95   @param PciIoDevice       A pointer to the PCI_IO_DEVICE.
  96   @param CapId             The capability ID.
  97   @param Offset            A pointer to the offset returned.
  98   @param NextRegBlock      A pointer to the next block returned.
  99
 100   @retval EFI_SUCCESS      Successfully located capability register block.
 101   @retval EFI_UNSUPPORTED  Pci device does not support capability.
 102   @retval EFI_NOT_FOUND    Pci device support but can not find register block.
 103
 104 **/
 105 EFI_STATUS
 106 LocateCapabilityRegBlock (
 107   IN PCI_IO_DEVICE  *PciIoDevice,
 108   IN UINT8          CapId,
 109   IN OUT UINT8      *Offset,
 110   OUT UINT8         *NextRegBlock OPTIONAL
 111   );
 112
 113 /**
 114   Locate PciExpress capability register block per capability ID.
 115
 116   @param PciIoDevice       A pointer to the PCI_IO_DEVICE.
 117   @param CapId             The capability ID.
 118   @param Offset            A pointer to the offset returned.
 119   @param NextRegBlock      A pointer to the next block returned.
 120
 121   @retval EFI_SUCCESS      Successfully located capability register block.
 122   @retval EFI_UNSUPPORTED  Pci device does not support capability.
 123   @retval EFI_NOT_FOUND    Pci device support but can not find register block.
 124
 125 **/
 126 EFI_STATUS
 127 LocatePciExpressCapabilityRegBlock (
 128   IN     PCI_IO_DEVICE  *PciIoDevice,
 129   IN     UINT16         CapId,
 130   IN OUT UINT32         *Offset,
 131   OUT UINT32            *NextRegBlock OPTIONAL
 132   );
 133
 134 /**
 135   Macro that reads command register.
 136
 137   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 138   @param b[out]           Pointer to the 16-bit value read from command register.
 139
 140   @return status of PciIo operation
 141
 142 **/
 143 #define PCI_READ_COMMAND_REGISTER(a, b) \
 144         PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)
 145
 146 /**
 147   Macro that writes command register.
 148
 149   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 150   @param b[in]            The 16-bit value written into command register.
 151
 152   @return status of PciIo operation
 153
 154 **/
 155 #define PCI_SET_COMMAND_REGISTER(a, b) \
 156         PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)
 157
 158 /**
 159   Macro that enables command register.
 160
 161   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 162   @param b[in]            The enabled value written into command register.
 163
 164   @return status of PciIo operation
 165
 166 **/
 167 #define PCI_ENABLE_COMMAND_REGISTER(a, b) \
 168         PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)
 169
 170 /**
 171   Macro that disables command register.
 172
 173   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 174   @param b[in]            The disabled value written into command register.
 175
 176   @return status of PciIo operation
 177
 178 **/
 179 #define PCI_DISABLE_COMMAND_REGISTER(a, b) \
 180         PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)
 181
 182 /**
 183   Macro that reads PCI bridge control register.
 184
 185   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 186   @param b[out]           The 16-bit value read from control register.
 187
 188   @return status of PciIo operation
 189
 190 **/
 191 #define PCI_READ_BRIDGE_CONTROL_REGISTER(a, b) \
 192         PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)
 193
 194 /**
 195   Macro that writes PCI bridge control register.
 196
 197   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 198   @param b[in]            The 16-bit value written into control register.
 199
 200   @return status of PciIo operation
 201
 202 **/
 203 #define PCI_SET_BRIDGE_CONTROL_REGISTER(a, b) \
 204         PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)
 205
 206 /**
 207   Macro that enables PCI bridge control register.
 208
 209   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 210   @param b[in]            The enabled value written into command register.
 211
 212   @return status of PciIo operation
 213
 214 **/
 215 #define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a, b) \
 216         PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)
 217
 218 /**
 219  Macro that disables PCI bridge control register.
 220
 221   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 222   @param b[in]            The disabled value written into command register.
 223
 224   @return status of PciIo operation
 225
 226 **/
 227 #define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a, b) \
 228         PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)
 229
 230 #endif