2 PCI emumeration support functions implementation for PCI Bus module.
4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 extern CHAR16
*mBarTypeStr
[];
21 This routine is used to check whether the pci device is present.
23 @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
24 @param Pci Output buffer for PCI device configuration space.
25 @param Bus PCI bus NO.
26 @param Device PCI device NO.
27 @param Func PCI Func NO.
29 @retval EFI_NOT_FOUND PCI device not present.
30 @retval EFI_SUCCESS PCI device is found.
35 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
,
46 // Create PCI address map in terms of Bus, Device and Func
48 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
51 // Read the Vendor ID register
53 Status
= PciRootBridgeIo
->Pci
.Read (
61 if (!EFI_ERROR (Status
) && (Pci
->Hdr
).VendorId
!= 0xffff) {
63 // Read the entire config header for the device
65 Status
= PciRootBridgeIo
->Pci
.Read (
69 sizeof (PCI_TYPE00
) / sizeof (UINT32
),
80 Collect all the resource information under this root bridge.
82 A database that records all the information about pci device subject to this
83 root bridge will then be created.
85 @param Bridge Parent bridge instance.
86 @param StartBusNumber Bus number of begining.
88 @retval EFI_SUCCESS PCI device is found.
89 @retval other Some error occurred when reading PCI bridge information.
93 PciPciDeviceInfoCollector (
94 IN PCI_IO_DEVICE
*Bridge
,
95 IN UINT8 StartBusNumber
103 PCI_IO_DEVICE
*PciIoDevice
;
104 EFI_PCI_IO_PROTOCOL
*PciIo
;
106 Status
= EFI_SUCCESS
;
109 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
111 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
114 // Check to see whether PCI device is present
116 Status
= PciDevicePresent (
117 Bridge
->PciRootBridgeIo
,
119 (UINT8
) StartBusNumber
,
124 if (EFI_ERROR (Status
) && Func
== 0) {
126 // go to next device if there is no Function 0
131 if (!EFI_ERROR (Status
)) {
134 // Call back to host bridge function
136 PreprocessController (Bridge
, (UINT8
) StartBusNumber
, Device
, Func
, EfiPciBeforeResourceCollection
);
139 // Collect all the information about the PCI device discovered
141 Status
= PciSearchDevice (
144 (UINT8
) StartBusNumber
,
151 // Recursively scan PCI busses on the other side of PCI-PCI bridges
154 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
) || IS_CARDBUS_BRIDGE (&Pci
))) {
157 // If it is PPB, we need to get the secondary bus to continue the enumeration
159 PciIo
= &(PciIoDevice
->PciIo
);
161 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
, 1, &SecBus
);
163 if (EFI_ERROR (Status
)) {
168 // Ensure secondary bus number is greater than the primary bus number to avoid
169 // any potential dead loop when PcdPciDisableBusEnumeration is set to TRUE
171 if (SecBus
<= StartBusNumber
) {
176 // Get resource padding for PPB
178 GetResourcePaddingPpb (PciIoDevice
);
181 // Deep enumerate the next level bus
183 Status
= PciPciDeviceInfoCollector (
190 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
193 // Skip sub functions, this is not a multi function device
206 Seach required device and create PCI device instance.
208 @param Bridge Parent bridge instance.
209 @param Pci Input PCI device information block.
210 @param Bus PCI bus NO.
211 @param Device PCI device NO.
212 @param Func PCI func NO.
213 @param PciDevice Output of searched PCI device instance.
215 @retval EFI_SUCCESS Successfully created PCI device instance.
216 @retval EFI_OUT_OF_RESOURCES Cannot get PCI device information.
221 IN PCI_IO_DEVICE
*Bridge
,
226 OUT PCI_IO_DEVICE
**PciDevice
229 PCI_IO_DEVICE
*PciIoDevice
;
235 "PciBus: Discovered %s @ [%02x|%02x|%02x]\n",
236 IS_PCI_BRIDGE (Pci
) ? L
"PPB" :
237 IS_CARDBUS_BRIDGE (Pci
) ? L
"P2C" :
242 if (!IS_PCI_BRIDGE (Pci
)) {
244 if (IS_CARDBUS_BRIDGE (Pci
)) {
245 PciIoDevice
= GatherP2CInfo (
252 if ((PciIoDevice
!= NULL
) && gFullEnumeration
) {
253 InitializeP2C (PciIoDevice
);
258 // Create private data for Pci Device
260 PciIoDevice
= GatherDeviceInfo (
273 // Create private data for PPB
275 PciIoDevice
= GatherPpbInfo (
284 // Special initialization for PPB including making the PPB quiet
286 if ((PciIoDevice
!= NULL
) && gFullEnumeration
) {
287 InitializePpb (PciIoDevice
);
291 if (PciIoDevice
== NULL
) {
292 return EFI_OUT_OF_RESOURCES
;
296 // Update the bar information for this PCI device so as to support some specific device
298 UpdatePciInfo (PciIoDevice
);
300 if (PciIoDevice
->DevicePath
== NULL
) {
301 return EFI_OUT_OF_RESOURCES
;
305 // Detect this function has option rom
307 if (gFullEnumeration
) {
309 if (!IS_CARDBUS_BRIDGE (Pci
)) {
311 GetOpRomInfo (PciIoDevice
);
315 ResetPowerManagementFeature (PciIoDevice
);
320 // Insert it into a global tree for future reference
322 InsertPciDevice (Bridge
, PciIoDevice
);
325 // Determine PCI device attributes
328 if (PciDevice
!= NULL
) {
329 *PciDevice
= PciIoDevice
;
336 Dump the PPB padding resource information.
338 @param PciIoDevice PCI IO instance.
339 @param ResourceType The desired resource type to dump.
340 PciBarTypeUnknown means to dump all types of resources.
343 DumpPpbPaddingResource (
344 IN PCI_IO_DEVICE
*PciIoDevice
,
345 IN PCI_BAR_TYPE ResourceType
348 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptor
;
351 if (PciIoDevice
->ResourcePaddingDescriptors
== NULL
) {
355 if (ResourceType
== PciBarTypeIo16
|| ResourceType
== PciBarTypeIo32
) {
356 ResourceType
= PciBarTypeIo
;
359 for (Descriptor
= PciIoDevice
->ResourcePaddingDescriptors
; Descriptor
->Desc
!= ACPI_END_TAG_DESCRIPTOR
; Descriptor
++) {
361 Type
= PciBarTypeUnknown
;
362 if (Descriptor
->Desc
== ACPI_ADDRESS_SPACE_DESCRIPTOR
&& Descriptor
->ResType
== ACPI_ADDRESS_SPACE_TYPE_IO
) {
364 } else if (Descriptor
->Desc
== ACPI_ADDRESS_SPACE_DESCRIPTOR
&& Descriptor
->ResType
== ACPI_ADDRESS_SPACE_TYPE_MEM
) {
366 if (Descriptor
->AddrSpaceGranularity
== 32) {
370 if (Descriptor
->SpecificFlag
== EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
) {
371 Type
= PciBarTypePMem32
;
377 if (Descriptor
->SpecificFlag
== 0) {
378 Type
= PciBarTypeMem32
;
382 if (Descriptor
->AddrSpaceGranularity
== 64) {
386 if (Descriptor
->SpecificFlag
== EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
) {
387 Type
= PciBarTypePMem64
;
393 if (Descriptor
->SpecificFlag
== 0) {
394 Type
= PciBarTypeMem64
;
399 if ((Type
!= PciBarTypeUnknown
) && ((ResourceType
== PciBarTypeUnknown
) || (ResourceType
== Type
))) {
402 " Padding: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx\n",
403 mBarTypeStr
[Type
], Descriptor
->AddrRangeMax
, Descriptor
->AddrLen
411 Dump the PCI BAR information.
413 @param PciIoDevice PCI IO instance.
417 IN PCI_IO_DEVICE
*PciIoDevice
422 for (Index
= 0; Index
< PCI_MAX_BAR
; Index
++) {
423 if (PciIoDevice
->PciBar
[Index
].BarType
== PciBarTypeUnknown
) {
429 " BAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
430 Index
, mBarTypeStr
[MIN (PciIoDevice
->PciBar
[Index
].BarType
, PciBarTypeMaxType
)],
431 PciIoDevice
->PciBar
[Index
].Alignment
, PciIoDevice
->PciBar
[Index
].Length
, PciIoDevice
->PciBar
[Index
].Offset
435 for (Index
= 0; Index
< PCI_MAX_BAR
; Index
++) {
436 if ((PciIoDevice
->VfPciBar
[Index
].BarType
== PciBarTypeUnknown
) && (PciIoDevice
->VfPciBar
[Index
].Length
== 0)) {
442 " VFBAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
443 Index
, mBarTypeStr
[MIN (PciIoDevice
->VfPciBar
[Index
].BarType
, PciBarTypeMaxType
)],
444 PciIoDevice
->VfPciBar
[Index
].Alignment
, PciIoDevice
->VfPciBar
[Index
].Length
, PciIoDevice
->VfPciBar
[Index
].Offset
447 DEBUG ((EFI_D_INFO
, "\n"));
451 Create PCI device instance for PCI device.
453 @param Bridge Parent bridge instance.
454 @param Pci Input PCI device information block.
455 @param Bus PCI device Bus NO.
456 @param Device PCI device Device NO.
457 @param Func PCI device's func NO.
459 @return Created PCI device instance.
464 IN PCI_IO_DEVICE
*Bridge
,
473 PCI_IO_DEVICE
*PciIoDevice
;
475 PciIoDevice
= CreatePciIoDevice (
483 if (PciIoDevice
== NULL
) {
488 // If it is a full enumeration, disconnect the device in advance
490 if (gFullEnumeration
) {
492 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
497 // Start to parse the bars
499 for (Offset
= 0x10, BarIndex
= 0; Offset
<= 0x24 && BarIndex
< PCI_MAX_BAR
; BarIndex
++) {
500 Offset
= PciParseBar (PciIoDevice
, Offset
, BarIndex
);
504 // Parse the SR-IOV VF bars
506 if (PcdGetBool (PcdSrIovSupport
) && PciIoDevice
->SrIovCapabilityOffset
!= 0) {
507 for (Offset
= PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0
, BarIndex
= 0;
508 Offset
<= PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5
;
511 ASSERT (BarIndex
< PCI_MAX_BAR
);
512 Offset
= PciIovParseVfBar (PciIoDevice
, Offset
, BarIndex
);
516 DEBUG_CODE (DumpPciBars (PciIoDevice
););
521 Create PCI device instance for PCI-PCI bridge.
523 @param Bridge Parent bridge instance.
524 @param Pci Input PCI device information block.
525 @param Bus PCI device Bus NO.
526 @param Device PCI device Device NO.
527 @param Func PCI device's func NO.
529 @return Created PCI device instance.
534 IN PCI_IO_DEVICE
*Bridge
,
541 PCI_IO_DEVICE
*PciIoDevice
;
544 EFI_PCI_IO_PROTOCOL
*PciIo
;
546 UINT32 PMemBaseLimit
;
547 UINT16 PrefetchableMemoryBase
;
548 UINT16 PrefetchableMemoryLimit
;
550 PciIoDevice
= CreatePciIoDevice (
558 if (PciIoDevice
== NULL
) {
562 if (gFullEnumeration
) {
563 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
566 // Initalize the bridge control register
568 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED
);
573 // PPB can have two BARs
575 if (PciParseBar (PciIoDevice
, 0x10, PPB_BAR_0
) == 0x14) {
579 PciParseBar (PciIoDevice
, 0x14, PPB_BAR_1
);
582 PciIo
= &PciIoDevice
->PciIo
;
585 // Test whether it support 32 decode or not
587 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
588 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
589 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
590 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
593 if ((Value
& 0x01) != 0) {
594 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
596 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO16_DECODE_SUPPORTED
;
601 // if PcdPciBridgeIoAlignmentProbe is TRUE, PCI bus driver probes
602 // PCI bridge supporting non-stardard I/O window alignment less than 4K.
605 PciIoDevice
->BridgeIoAlignment
= 0xFFF;
606 if (FeaturePcdGet (PcdPciBridgeIoAlignmentProbe
)) {
608 // Check any bits of bit 3-1 of I/O Base Register are writable.
609 // if so, it is assumed non-stardard I/O window alignment is supported by this bridge.
610 // Per spec, bit 3-1 of I/O Base Register are reserved bits, so its content can't be assumed.
612 Value
= (UINT8
)(Temp
^ (BIT3
| BIT2
| BIT1
));
613 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
614 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
615 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
616 Value
= (UINT8
)((Value
^ Temp
) & (BIT3
| BIT2
| BIT1
));
619 PciIoDevice
->BridgeIoAlignment
= 0x7FF;
622 PciIoDevice
->BridgeIoAlignment
= 0x3FF;
624 case BIT3
| BIT2
| BIT1
:
625 PciIoDevice
->BridgeIoAlignment
= 0x1FF;
630 Status
= BarExisted (
638 // Test if it supports 64 memory or not
640 // The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory Limit
642 // 0 - the bridge supports only 32 bit addresses.
643 // 1 - the bridge supports 64-bit addresses.
645 PrefetchableMemoryBase
= (UINT16
)(PMemBaseLimit
& 0xffff);
646 PrefetchableMemoryLimit
= (UINT16
)(PMemBaseLimit
>> 16);
647 if (!EFI_ERROR (Status
) &&
648 (PrefetchableMemoryBase
& 0x000f) == 0x0001 &&
649 (PrefetchableMemoryLimit
& 0x000f) == 0x0001) {
650 Status
= BarExisted (
657 if (!EFI_ERROR (Status
)) {
658 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
659 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED
;
661 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
666 // Memory 32 code is required for ppb
668 PciIoDevice
->Decodes
|= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
;
670 GetResourcePaddingPpb (PciIoDevice
);
673 DumpPpbPaddingResource (PciIoDevice
, PciBarTypeUnknown
);
674 DumpPciBars (PciIoDevice
);
682 Create PCI device instance for PCI Card bridge device.
684 @param Bridge Parent bridge instance.
685 @param Pci Input PCI device information block.
686 @param Bus PCI device Bus NO.
687 @param Device PCI device Device NO.
688 @param Func PCI device's func NO.
690 @return Created PCI device instance.
695 IN PCI_IO_DEVICE
*Bridge
,
702 PCI_IO_DEVICE
*PciIoDevice
;
704 PciIoDevice
= CreatePciIoDevice (
712 if (PciIoDevice
== NULL
) {
716 if (gFullEnumeration
) {
717 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
720 // Initalize the bridge control register
722 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED
);
726 // P2C only has one bar that is in 0x10
728 PciParseBar (PciIoDevice
, 0x10, P2C_BAR_0
);
731 // Read PciBar information from the bar register
733 GetBackPcCardBar (PciIoDevice
);
734 PciIoDevice
->Decodes
= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
|
735 EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
|
736 EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
738 DEBUG_CODE (DumpPciBars (PciIoDevice
););
744 Create device path for pci deivce.
746 @param ParentDevicePath Parent bridge's path.
747 @param PciIoDevice Pci device instance.
749 @return Device path protocol instance for specific pci device.
752 EFI_DEVICE_PATH_PROTOCOL
*
753 CreatePciDevicePath (
754 IN EFI_DEVICE_PATH_PROTOCOL
*ParentDevicePath
,
755 IN PCI_IO_DEVICE
*PciIoDevice
759 PCI_DEVICE_PATH PciNode
;
762 // Create PCI device path
764 PciNode
.Header
.Type
= HARDWARE_DEVICE_PATH
;
765 PciNode
.Header
.SubType
= HW_PCI_DP
;
766 SetDevicePathNodeLength (&PciNode
.Header
, sizeof (PciNode
));
768 PciNode
.Device
= PciIoDevice
->DeviceNumber
;
769 PciNode
.Function
= PciIoDevice
->FunctionNumber
;
770 PciIoDevice
->DevicePath
= AppendDevicePathNode (ParentDevicePath
, &PciNode
.Header
);
772 return PciIoDevice
->DevicePath
;
776 Check whether the PCI IOV VF bar is existed or not.
778 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
779 @param Offset The offset.
780 @param BarLengthValue The bar length value returned.
781 @param OriginalBarValue The original bar value returned.
783 @retval EFI_NOT_FOUND The bar doesn't exist.
784 @retval EFI_SUCCESS The bar exist.
789 IN PCI_IO_DEVICE
*PciIoDevice
,
791 OUT UINT32
*BarLengthValue
,
792 OUT UINT32
*OriginalBarValue
795 EFI_PCI_IO_PROTOCOL
*PciIo
;
796 UINT32 OriginalValue
;
801 // Ensure it is called properly
803 ASSERT (PciIoDevice
->SrIovCapabilityOffset
!= 0);
804 if (PciIoDevice
->SrIovCapabilityOffset
== 0) {
805 return EFI_NOT_FOUND
;
808 PciIo
= &PciIoDevice
->PciIo
;
811 // Preserve the original value
814 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &OriginalValue
);
817 // Raise TPL to high level to disable timer interrupt while the BAR is probed
819 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
821 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &gAllOne
);
822 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &Value
);
825 // Write back the original value
827 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &OriginalValue
);
830 // Restore TPL to its original level
832 gBS
->RestoreTPL (OldTpl
);
834 if (BarLengthValue
!= NULL
) {
835 *BarLengthValue
= Value
;
838 if (OriginalBarValue
!= NULL
) {
839 *OriginalBarValue
= OriginalValue
;
843 return EFI_NOT_FOUND
;
850 Check whether the bar is existed or not.
852 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
853 @param Offset The offset.
854 @param BarLengthValue The bar length value returned.
855 @param OriginalBarValue The original bar value returned.
857 @retval EFI_NOT_FOUND The bar doesn't exist.
858 @retval EFI_SUCCESS The bar exist.
863 IN PCI_IO_DEVICE
*PciIoDevice
,
865 OUT UINT32
*BarLengthValue
,
866 OUT UINT32
*OriginalBarValue
869 EFI_PCI_IO_PROTOCOL
*PciIo
;
870 UINT32 OriginalValue
;
874 PciIo
= &PciIoDevice
->PciIo
;
877 // Preserve the original value
879 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &OriginalValue
);
882 // Raise TPL to high level to disable timer interrupt while the BAR is probed
884 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
886 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &gAllOne
);
887 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &Value
);
890 // Write back the original value
892 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &OriginalValue
);
895 // Restore TPL to its original level
897 gBS
->RestoreTPL (OldTpl
);
899 if (BarLengthValue
!= NULL
) {
900 *BarLengthValue
= Value
;
903 if (OriginalBarValue
!= NULL
) {
904 *OriginalBarValue
= OriginalValue
;
908 return EFI_NOT_FOUND
;
915 Test whether the device can support given attributes.
917 @param PciIoDevice Pci device instance.
918 @param Command Input command register value, and
919 returned supported register value.
920 @param BridgeControl Inout bridge control value for PPB or P2C, and
921 returned supported bridge control value.
922 @param OldCommand Returned and stored old command register offset.
923 @param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.
927 PciTestSupportedAttribute (
928 IN PCI_IO_DEVICE
*PciIoDevice
,
929 IN OUT UINT16
*Command
,
930 IN OUT UINT16
*BridgeControl
,
931 OUT UINT16
*OldCommand
,
932 OUT UINT16
*OldBridgeControl
938 // Preserve the original value
940 PCI_READ_COMMAND_REGISTER (PciIoDevice
, OldCommand
);
943 // Raise TPL to high level to disable timer interrupt while the BAR is probed
945 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
947 PCI_SET_COMMAND_REGISTER (PciIoDevice
, *Command
);
948 PCI_READ_COMMAND_REGISTER (PciIoDevice
, Command
);
951 // Write back the original value
953 PCI_SET_COMMAND_REGISTER (PciIoDevice
, *OldCommand
);
956 // Restore TPL to its original level
958 gBS
->RestoreTPL (OldTpl
);
960 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
963 // Preserve the original value
965 PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice
, OldBridgeControl
);
968 // Raise TPL to high level to disable timer interrupt while the BAR is probed
970 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
972 PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice
, *BridgeControl
);
973 PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice
, BridgeControl
);
976 // Write back the original value
978 PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice
, *OldBridgeControl
);
981 // Restore TPL to its original level
983 gBS
->RestoreTPL (OldTpl
);
986 *OldBridgeControl
= 0;
992 Set the supported or current attributes of a PCI device.
994 @param PciIoDevice Structure pointer for PCI device.
995 @param Command Command register value.
996 @param BridgeControl Bridge control value for PPB or P2C.
997 @param Option Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.
1001 PciSetDeviceAttribute (
1002 IN PCI_IO_DEVICE
*PciIoDevice
,
1004 IN UINT16 BridgeControl
,
1012 if ((Command
& EFI_PCI_COMMAND_IO_SPACE
) != 0) {
1013 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IO
;
1016 if ((Command
& EFI_PCI_COMMAND_MEMORY_SPACE
) != 0) {
1017 Attributes
|= EFI_PCI_IO_ATTRIBUTE_MEMORY
;
1020 if ((Command
& EFI_PCI_COMMAND_BUS_MASTER
) != 0) {
1021 Attributes
|= EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
;
1024 if ((Command
& EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
) != 0) {
1025 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
1028 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_ISA
) != 0) {
1029 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_IO
;
1032 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA
) != 0) {
1033 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO
;
1034 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
1035 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
1038 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA_16
) != 0) {
1039 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
;
1040 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16
;
1043 if (Option
== EFI_SET_SUPPORTS
) {
1045 Attributes
|= (UINT64
) (EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE
|
1046 EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED
|
1047 EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE
|
1048 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE
|
1049 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
|
1050 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
);
1052 if (IS_PCI_LPC (&PciIoDevice
->Pci
)) {
1053 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO
;
1054 Attributes
|= (mReserveIsaAliases
? (UINT64
) EFI_PCI_IO_ATTRIBUTE_ISA_IO
: \
1055 (UINT64
) EFI_PCI_IO_ATTRIBUTE_ISA_IO_16
);
1058 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
1060 // For bridge, it should support IDE attributes
1062 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
1063 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
1065 if (mReserveVgaAliases
) {
1066 Attributes
&= ~(UINT64
)(EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
| \
1067 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16
);
1069 Attributes
&= ~(UINT64
)(EFI_PCI_IO_ATTRIBUTE_VGA_IO
| \
1070 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
);
1074 if (IS_PCI_IDE (&PciIoDevice
->Pci
)) {
1075 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
1076 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
1079 if (IS_PCI_VGA (&PciIoDevice
->Pci
)) {
1080 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
1081 Attributes
|= (mReserveVgaAliases
? (UINT64
) EFI_PCI_IO_ATTRIBUTE_VGA_IO
: \
1082 (UINT64
) EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
);
1086 PciIoDevice
->Supports
= Attributes
;
1087 PciIoDevice
->Supports
&= ( (PciIoDevice
->Parent
->Supports
) | \
1088 EFI_PCI_IO_ATTRIBUTE_IO
| EFI_PCI_IO_ATTRIBUTE_MEMORY
| \
1089 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
);
1093 // When this attribute is clear, the RomImage and RomSize fields in the PCI IO were
1094 // initialized based on the PCI option ROM found through the ROM BAR of the PCI controller.
1095 // When this attribute is set, the PCI option ROM described by the RomImage and RomSize
1096 // fields is not from the the ROM BAR of the PCI controller.
1098 if (!PciIoDevice
->EmbeddedRom
) {
1099 Attributes
|= EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
;
1101 PciIoDevice
->Attributes
= Attributes
;
1106 Determine if the device can support Fast Back to Back attribute.
1108 @param PciIoDevice Pci device instance.
1109 @param StatusIndex Status register value.
1111 @retval EFI_SUCCESS This device support Fast Back to Back attribute.
1112 @retval EFI_UNSUPPORTED This device doesn't support Fast Back to Back attribute.
1116 GetFastBackToBackSupport (
1117 IN PCI_IO_DEVICE
*PciIoDevice
,
1118 IN UINT8 StatusIndex
1121 EFI_PCI_IO_PROTOCOL
*PciIo
;
1123 UINT32 StatusRegister
;
1126 // Read the status register
1128 PciIo
= &PciIoDevice
->PciIo
;
1129 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint16
, StatusIndex
, 1, &StatusRegister
);
1130 if (EFI_ERROR (Status
)) {
1131 return EFI_UNSUPPORTED
;
1135 // Check the Fast B2B bit
1137 if ((StatusRegister
& EFI_PCI_FAST_BACK_TO_BACK_CAPABLE
) != 0) {
1140 return EFI_UNSUPPORTED
;
1145 Process the option ROM for all the children of the specified parent PCI device.
1146 It can only be used after the first full Option ROM process.
1148 @param PciIoDevice Pci device instance.
1152 ProcessOptionRomLight (
1153 IN PCI_IO_DEVICE
*PciIoDevice
1156 PCI_IO_DEVICE
*Temp
;
1157 LIST_ENTRY
*CurrentLink
;
1160 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1162 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1163 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1165 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1167 if (!IsListEmpty (&Temp
->ChildList
)) {
1168 ProcessOptionRomLight (Temp
);
1171 PciRomGetImageMapping (Temp
);
1174 // The OpRom has already been processed in the first round
1176 Temp
->AllOpRomProcessed
= TRUE
;
1178 CurrentLink
= CurrentLink
->ForwardLink
;
1183 Determine the related attributes of all devices under a Root Bridge.
1185 @param PciIoDevice PCI device instance.
1189 DetermineDeviceAttribute (
1190 IN PCI_IO_DEVICE
*PciIoDevice
1194 UINT16 BridgeControl
;
1196 UINT16 OldBridgeControl
;
1197 BOOLEAN FastB2BSupport
;
1198 PCI_IO_DEVICE
*Temp
;
1199 LIST_ENTRY
*CurrentLink
;
1203 // For Root Bridge, just copy it by RootBridgeIo proctocol
1204 // so as to keep consistent with the actual attribute
1206 if (PciIoDevice
->Parent
== NULL
) {
1207 Status
= PciIoDevice
->PciRootBridgeIo
->GetAttributes (
1208 PciIoDevice
->PciRootBridgeIo
,
1209 &PciIoDevice
->Supports
,
1210 &PciIoDevice
->Attributes
1212 if (EFI_ERROR (Status
)) {
1216 // Assume the PCI Root Bridge supports DAC
1218 PciIoDevice
->Supports
|= (UINT64
)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE
|
1219 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
|
1220 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
);
1225 // Set the attributes to be checked for common PCI devices and PPB or P2C
1226 // Since some devices only support part of them, it is better to set the
1227 // attribute according to its command or bridge control register
1229 Command
= EFI_PCI_COMMAND_IO_SPACE
|
1230 EFI_PCI_COMMAND_MEMORY_SPACE
|
1231 EFI_PCI_COMMAND_BUS_MASTER
|
1232 EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
;
1234 BridgeControl
= EFI_PCI_BRIDGE_CONTROL_ISA
| EFI_PCI_BRIDGE_CONTROL_VGA
| EFI_PCI_BRIDGE_CONTROL_VGA_16
;
1237 // Test whether the device can support attributes above
1239 PciTestSupportedAttribute (PciIoDevice
, &Command
, &BridgeControl
, &OldCommand
, &OldBridgeControl
);
1242 // Set the supported attributes for specified PCI device
1244 PciSetDeviceAttribute (PciIoDevice
, Command
, BridgeControl
, EFI_SET_SUPPORTS
);
1247 // Set the current attributes for specified PCI device
1249 PciSetDeviceAttribute (PciIoDevice
, OldCommand
, OldBridgeControl
, EFI_SET_ATTRIBUTES
);
1252 // Enable other supported attributes but not defined in PCI_IO_PROTOCOL
1254 PCI_ENABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE
);
1257 FastB2BSupport
= TRUE
;
1260 // P2C can not support FB2B on the secondary side
1262 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
1263 FastB2BSupport
= FALSE
;
1267 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1269 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1270 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1272 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1273 Status
= DetermineDeviceAttribute (Temp
);
1274 if (EFI_ERROR (Status
)) {
1278 // Detect Fast Bact to Bact support for the device under the bridge
1280 Status
= GetFastBackToBackSupport (Temp
, PCI_PRIMARY_STATUS_OFFSET
);
1281 if (FastB2BSupport
&& EFI_ERROR (Status
)) {
1282 FastB2BSupport
= FALSE
;
1285 CurrentLink
= CurrentLink
->ForwardLink
;
1288 // Set or clear Fast Back to Back bit for the whole bridge
1290 if (!IsListEmpty (&PciIoDevice
->ChildList
)) {
1292 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
1294 Status
= GetFastBackToBackSupport (PciIoDevice
, PCI_BRIDGE_STATUS_REGISTER_OFFSET
);
1296 if (EFI_ERROR (Status
) || (!FastB2BSupport
)) {
1297 FastB2BSupport
= FALSE
;
1298 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1300 PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1304 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1305 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1306 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1307 if (FastB2BSupport
) {
1308 PCI_ENABLE_COMMAND_REGISTER (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1310 PCI_DISABLE_COMMAND_REGISTER (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1313 CurrentLink
= CurrentLink
->ForwardLink
;
1317 // End for IsListEmpty
1323 This routine is used to update the bar information for those incompatible PCI device.
1325 @param PciIoDevice Input Pci device instance. Output Pci device instance with updated
1328 @retval EFI_SUCCESS Successfully updated bar information.
1329 @retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.
1334 IN OUT PCI_IO_DEVICE
*PciIoDevice
1341 VOID
*Configuration
;
1342 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Ptr
;
1344 Configuration
= NULL
;
1345 Status
= EFI_SUCCESS
;
1347 if (gIncompatiblePciDeviceSupport
== NULL
) {
1349 // It can only be supported after the Incompatible PCI Device
1350 // Support Protocol has been installed
1352 Status
= gBS
->LocateProtocol (
1353 &gEfiIncompatiblePciDeviceSupportProtocolGuid
,
1355 (VOID
**) &gIncompatiblePciDeviceSupport
1358 if (Status
== EFI_SUCCESS
) {
1360 // Check whether the device belongs to incompatible devices from protocol or not
1361 // If it is , then get its special requirement in the ACPI table
1363 Status
= gIncompatiblePciDeviceSupport
->CheckDevice (
1364 gIncompatiblePciDeviceSupport
,
1365 PciIoDevice
->Pci
.Hdr
.VendorId
,
1366 PciIoDevice
->Pci
.Hdr
.DeviceId
,
1367 PciIoDevice
->Pci
.Hdr
.RevisionID
,
1368 PciIoDevice
->Pci
.Device
.SubsystemVendorID
,
1369 PciIoDevice
->Pci
.Device
.SubsystemID
,
1375 if (EFI_ERROR (Status
) || Configuration
== NULL
) {
1376 return EFI_UNSUPPORTED
;
1380 // Update PCI device information from the ACPI table
1382 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Configuration
;
1384 while (Ptr
->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
1386 if (Ptr
->Desc
!= ACPI_ADDRESS_SPACE_DESCRIPTOR
) {
1388 // The format is not support
1393 BarIndex
= (UINTN
) Ptr
->AddrTranslationOffset
;
1394 BarEndIndex
= BarIndex
;
1397 // Update all the bars in the device
1399 if (BarIndex
== PCI_BAR_ALL
) {
1401 BarEndIndex
= PCI_MAX_BAR
- 1;
1404 if (BarIndex
> PCI_MAX_BAR
) {
1409 for (; BarIndex
<= BarEndIndex
; BarIndex
++) {
1411 switch (Ptr
->ResType
) {
1412 case ACPI_ADDRESS_SPACE_TYPE_MEM
:
1415 // Make sure the bar is memory type
1417 if (CheckBarType (PciIoDevice
, (UINT8
) BarIndex
, PciBarTypeMem
)) {
1421 // Ignored if granularity is 0.
1422 // Ignored if PCI BAR is I/O or 32-bit memory.
1423 // If PCI BAR is 64-bit memory and granularity is 32, then
1424 // the PCI BAR resource is allocated below 4GB.
1425 // If PCI BAR is 64-bit memory and granularity is 64, then
1426 // the PCI BAR resource is allocated above 4GB.
1428 if (PciIoDevice
->PciBar
[BarIndex
].BarType
== PciBarTypeMem64
) {
1429 switch (Ptr
->AddrSpaceGranularity
) {
1431 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1433 PciIoDevice
->PciBar
[BarIndex
].BarTypeFixed
= TRUE
;
1440 if (PciIoDevice
->PciBar
[BarIndex
].BarType
== PciBarTypePMem64
) {
1441 switch (Ptr
->AddrSpaceGranularity
) {
1443 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1445 PciIoDevice
->PciBar
[BarIndex
].BarTypeFixed
= TRUE
;
1454 case ACPI_ADDRESS_SPACE_TYPE_IO
:
1457 // Make sure the bar is IO type
1459 if (CheckBarType (PciIoDevice
, (UINT8
) BarIndex
, PciBarTypeIo
)) {
1468 // Update the new alignment for the device
1470 SetNewAlign (&(PciIoDevice
->PciBar
[BarIndex
].Alignment
), Ptr
->AddrRangeMax
);
1473 // Update the new length for the device
1475 if (Ptr
->AddrLen
!= PCI_BAR_NOCHANGE
) {
1476 PciIoDevice
->PciBar
[BarIndex
].Length
= Ptr
->AddrLen
;
1484 FreePool (Configuration
);
1490 This routine will update the alignment with the new alignment.
1492 @param Alignment Input Old alignment. Output updated alignment.
1493 @param NewAlignment New alignment.
1498 IN OUT UINT64
*Alignment
,
1499 IN UINT64 NewAlignment
1502 UINT64 OldAlignment
;
1506 // The new alignment is the same as the original,
1509 if (NewAlignment
== PCI_BAR_OLD_ALIGN
) {
1513 // Check the validity of the parameter
1515 if (NewAlignment
!= PCI_BAR_EVEN_ALIGN
&&
1516 NewAlignment
!= PCI_BAR_SQUAD_ALIGN
&&
1517 NewAlignment
!= PCI_BAR_DQUAD_ALIGN
) {
1518 *Alignment
= NewAlignment
;
1522 OldAlignment
= (*Alignment
) + 1;
1526 // Get the first non-zero hex value of the length
1528 while ((OldAlignment
& 0x0F) == 0x00) {
1529 OldAlignment
= RShiftU64 (OldAlignment
, 4);
1534 // Adjust the alignment to even, quad or double quad boundary
1536 if (NewAlignment
== PCI_BAR_EVEN_ALIGN
) {
1537 if ((OldAlignment
& 0x01) != 0) {
1538 OldAlignment
= OldAlignment
+ 2 - (OldAlignment
& 0x01);
1540 } else if (NewAlignment
== PCI_BAR_SQUAD_ALIGN
) {
1541 if ((OldAlignment
& 0x03) != 0) {
1542 OldAlignment
= OldAlignment
+ 4 - (OldAlignment
& 0x03);
1544 } else if (NewAlignment
== PCI_BAR_DQUAD_ALIGN
) {
1545 if ((OldAlignment
& 0x07) != 0) {
1546 OldAlignment
= OldAlignment
+ 8 - (OldAlignment
& 0x07);
1551 // Update the old value
1553 NewAlignment
= LShiftU64 (OldAlignment
, ShiftBit
) - 1;
1554 *Alignment
= NewAlignment
;
1560 Parse PCI IOV VF bar information and fill them into PCI device instance.
1562 @param PciIoDevice Pci device instance.
1563 @param Offset Bar offset.
1564 @param BarIndex Bar index.
1566 @return Next bar offset.
1571 IN PCI_IO_DEVICE
*PciIoDevice
,
1577 UINT32 OriginalValue
;
1582 // Ensure it is called properly
1584 ASSERT (PciIoDevice
->SrIovCapabilityOffset
!= 0);
1585 if (PciIoDevice
->SrIovCapabilityOffset
== 0) {
1592 Status
= VfBarExisted (
1599 if (EFI_ERROR (Status
)) {
1600 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= 0;
1601 PciIoDevice
->VfPciBar
[BarIndex
].Length
= 0;
1602 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= 0;
1605 // Scan all the BARs anyway
1607 PciIoDevice
->VfPciBar
[BarIndex
].Offset
= (UINT16
) Offset
;
1611 PciIoDevice
->VfPciBar
[BarIndex
].Offset
= (UINT16
) Offset
;
1612 if ((Value
& 0x01) != 0) {
1614 // Device I/Os. Impossible
1623 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1625 switch (Value
& 0x07) {
1628 //memory space; anywhere in 32 bit address space
1631 if ((Value
& 0x08) != 0) {
1632 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1634 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1637 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1638 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1643 PciIoDevice
->VfPciBar
[BarIndex
].Length
= MultU64x32 (PciIoDevice
->VfPciBar
[BarIndex
].Length
, PciIoDevice
->InitialVFs
);
1647 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1648 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1654 // memory space; anywhere in 64 bit address space
1657 if ((Value
& 0x08) != 0) {
1658 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypePMem64
;
1660 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeMem64
;
1664 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1665 // is regarded as an extension for the first bar. As a result
1666 // the sizing will be conducted on combined 64 bit value
1667 // Here just store the masked first 32bit value for future size
1670 PciIoDevice
->VfPciBar
[BarIndex
].Length
= Value
& Mask
;
1671 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1673 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1674 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1678 // Increment the offset to point to next DWORD
1682 Status
= VfBarExisted (
1689 if (EFI_ERROR (Status
)) {
1694 // Fix the length to support some spefic 64 bit BAR
1696 Value
|= ((UINT32
) -1 << HighBitSet32 (Value
));
1699 // Calculate the size of 64bit bar
1701 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
|= LShiftU64 ((UINT64
) OriginalValue
, 32);
1703 PciIoDevice
->VfPciBar
[BarIndex
].Length
= PciIoDevice
->VfPciBar
[BarIndex
].Length
| LShiftU64 ((UINT64
) Value
, 32);
1704 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(PciIoDevice
->VfPciBar
[BarIndex
].Length
)) + 1;
1705 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1710 PciIoDevice
->VfPciBar
[BarIndex
].Length
= MultU64x32 (PciIoDevice
->VfPciBar
[BarIndex
].Length
, PciIoDevice
->InitialVFs
);
1714 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1715 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1724 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1725 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1726 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1728 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1729 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1737 // Check the length again so as to keep compatible with some special bars
1739 if (PciIoDevice
->VfPciBar
[BarIndex
].Length
== 0) {
1740 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1741 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= 0;
1742 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= 0;
1746 // Increment number of bar
1752 Parse PCI bar information and fill them into PCI device instance.
1754 @param PciIoDevice Pci device instance.
1755 @param Offset Bar offset.
1756 @param BarIndex Bar index.
1758 @return Next bar offset.
1763 IN PCI_IO_DEVICE
*PciIoDevice
,
1769 UINT32 OriginalValue
;
1776 Status
= BarExisted (
1783 if (EFI_ERROR (Status
)) {
1784 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1785 PciIoDevice
->PciBar
[BarIndex
].Length
= 0;
1786 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1789 // Some devices don't fully comply to PCI spec 2.2. So be to scan all the BARs anyway
1791 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
) Offset
;
1795 PciIoDevice
->PciBar
[BarIndex
].BarTypeFixed
= FALSE
;
1796 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
) Offset
;
1797 if ((Value
& 0x01) != 0) {
1803 if ((Value
& 0xFFFF0000) != 0) {
1807 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo32
;
1808 PciIoDevice
->PciBar
[BarIndex
].Length
= ((~(Value
& Mask
)) + 1);
1809 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1815 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo16
;
1816 PciIoDevice
->PciBar
[BarIndex
].Length
= 0x0000FFFF & ((~(Value
& Mask
)) + 1);
1817 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1821 // Workaround. Some platforms inplement IO bar with 0 length
1822 // Need to treat it as no-bar
1824 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1825 PciIoDevice
->PciBar
[BarIndex
].BarType
= (PCI_BAR_TYPE
) 0;
1828 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1834 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1836 switch (Value
& 0x07) {
1839 //memory space; anywhere in 32 bit address space
1842 if ((Value
& 0x08) != 0) {
1843 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1845 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1848 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1849 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1851 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1853 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1855 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1860 // memory space; anywhere in 64 bit address space
1863 if ((Value
& 0x08) != 0) {
1864 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem64
;
1866 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem64
;
1870 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1871 // is regarded as an extension for the first bar. As a result
1872 // the sizing will be conducted on combined 64 bit value
1873 // Here just store the masked first 32bit value for future size
1876 PciIoDevice
->PciBar
[BarIndex
].Length
= Value
& Mask
;
1877 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1880 // Increment the offset to point to next DWORD
1884 Status
= BarExisted (
1891 if (EFI_ERROR (Status
)) {
1893 // the high 32 bit does not claim any BAR, we need to re-check the low 32 bit BAR again
1895 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1897 // some device implement MMIO bar with 0 length, need to treat it as no-bar
1899 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1905 // Fix the length to support some spefic 64 bit BAR
1908 DEBUG ((EFI_D_INFO
, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
1909 Value
= (UINT32
) -1;
1911 Value
|= ((UINT32
)(-1) << HighBitSet32 (Value
));
1915 // Calculate the size of 64bit bar
1917 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
|= LShiftU64 ((UINT64
) OriginalValue
, 32);
1919 PciIoDevice
->PciBar
[BarIndex
].Length
= PciIoDevice
->PciBar
[BarIndex
].Length
| LShiftU64 ((UINT64
) Value
, 32);
1920 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(PciIoDevice
->PciBar
[BarIndex
].Length
)) + 1;
1921 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1923 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1925 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1927 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1936 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1937 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1938 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1940 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1942 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1944 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1951 // Check the length again so as to keep compatible with some special bars
1953 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1954 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1955 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1956 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1960 // Increment number of bar
1966 This routine is used to initialize the bar of a PCI device.
1968 @param PciIoDevice Pci device instance.
1970 @note It can be called typically when a device is going to be rejected.
1974 InitializePciDevice (
1975 IN PCI_IO_DEVICE
*PciIoDevice
1978 EFI_PCI_IO_PROTOCOL
*PciIo
;
1981 PciIo
= &(PciIoDevice
->PciIo
);
1984 // Put all the resource apertures
1985 // Resource base is set to all ones so as to indicate its resource
1986 // has not been alloacted
1988 for (Offset
= 0x10; Offset
<= 0x24; Offset
+= sizeof (UINT32
)) {
1989 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, Offset
, 1, &gAllOne
);
1994 This routine is used to initialize the bar of a PCI-PCI Bridge device.
1996 @param PciIoDevice PCI-PCI bridge device instance.
2001 IN PCI_IO_DEVICE
*PciIoDevice
2004 EFI_PCI_IO_PROTOCOL
*PciIo
;
2006 PciIo
= &(PciIoDevice
->PciIo
);
2009 // Put all the resource apertures including IO16
2010 // Io32, pMem32, pMem64 to quiescent state
2011 // Resource base all ones, Resource limit all zeros
2013 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
2014 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1D, 1, &gAllZero
);
2016 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x20, 1, &gAllOne
);
2017 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x22, 1, &gAllZero
);
2019 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x24, 1, &gAllOne
);
2020 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x26, 1, &gAllZero
);
2022 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllOne
);
2023 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2C, 1, &gAllZero
);
2026 // Don't support use io32 as for now
2028 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x30, 1, &gAllOne
);
2029 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x32, 1, &gAllZero
);
2032 // Force Interrupt line to zero for cards that come up randomly
2034 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
2038 This routine is used to initialize the bar of a PCI Card Bridge device.
2040 @param PciIoDevice PCI Card bridge device.
2045 IN PCI_IO_DEVICE
*PciIoDevice
2048 EFI_PCI_IO_PROTOCOL
*PciIo
;
2050 PciIo
= &(PciIoDevice
->PciIo
);
2053 // Put all the resource apertures including IO16
2054 // Io32, pMem32, pMem64 to quiescent state(
2055 // Resource base all ones, Resource limit all zeros
2057 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x1c, 1, &gAllOne
);
2058 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x20, 1, &gAllZero
);
2060 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x24, 1, &gAllOne
);
2061 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllZero
);
2063 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2c, 1, &gAllOne
);
2064 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x30, 1, &gAllZero
);
2066 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x34, 1, &gAllOne
);
2067 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x38, 1, &gAllZero
);
2070 // Force Interrupt line to zero for cards that come up randomly
2072 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
2076 Create and initiliaze general PCI I/O device instance for
2077 PCI device/bridge device/hotplug bridge device.
2079 @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
2080 @param Pci Input Pci information block.
2081 @param Bus Device Bus NO.
2082 @param Device Device device NO.
2083 @param Func Device func NO.
2085 @return Instance of PCI device. NULL means no instance created.
2090 IN PCI_IO_DEVICE
*Bridge
,
2097 PCI_IO_DEVICE
*PciIoDevice
;
2098 EFI_PCI_IO_PROTOCOL
*PciIo
;
2101 PciIoDevice
= AllocateZeroPool (sizeof (PCI_IO_DEVICE
));
2102 if (PciIoDevice
== NULL
) {
2106 PciIoDevice
->Signature
= PCI_IO_DEVICE_SIGNATURE
;
2107 PciIoDevice
->Handle
= NULL
;
2108 PciIoDevice
->PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
2109 PciIoDevice
->DevicePath
= NULL
;
2110 PciIoDevice
->BusNumber
= Bus
;
2111 PciIoDevice
->DeviceNumber
= Device
;
2112 PciIoDevice
->FunctionNumber
= Func
;
2113 PciIoDevice
->Decodes
= 0;
2115 if (gFullEnumeration
) {
2116 PciIoDevice
->Allocated
= FALSE
;
2118 PciIoDevice
->Allocated
= TRUE
;
2121 PciIoDevice
->Registered
= FALSE
;
2122 PciIoDevice
->Attributes
= 0;
2123 PciIoDevice
->Supports
= 0;
2124 PciIoDevice
->BusOverride
= FALSE
;
2125 PciIoDevice
->AllOpRomProcessed
= FALSE
;
2127 PciIoDevice
->IsPciExp
= FALSE
;
2129 CopyMem (&(PciIoDevice
->Pci
), Pci
, sizeof (PCI_TYPE01
));
2132 // Initialize the PCI I/O instance structure
2134 InitializePciIoInstance (PciIoDevice
);
2135 InitializePciDriverOverrideInstance (PciIoDevice
);
2136 InitializePciLoadFile2 (PciIoDevice
);
2137 PciIo
= &PciIoDevice
->PciIo
;
2140 // Create a device path for this PCI device and store it into its private data
2142 CreatePciDevicePath (
2148 // Detect if PCI Express Device
2150 PciIoDevice
->PciExpressCapabilityOffset
= 0;
2151 Status
= LocateCapabilityRegBlock (
2153 EFI_PCI_CAPABILITY_ID_PCIEXP
,
2154 &PciIoDevice
->PciExpressCapabilityOffset
,
2157 if (!EFI_ERROR (Status
)) {
2158 PciIoDevice
->IsPciExp
= TRUE
;
2161 if (PcdGetBool (PcdAriSupport
)) {
2163 // Check if the device is an ARI device.
2165 Status
= LocatePciExpressCapabilityRegBlock (
2167 EFI_PCIE_CAPABILITY_ID_ARI
,
2168 &PciIoDevice
->AriCapabilityOffset
,
2171 if (!EFI_ERROR (Status
)) {
2173 // We need to enable ARI feature before calculate BusReservation,
2174 // because FirstVFOffset and VFStride may change after that.
2176 EFI_PCI_IO_PROTOCOL
*ParentPciIo
;
2180 // Check if its parent supports ARI forwarding.
2182 ParentPciIo
= &Bridge
->PciIo
;
2183 ParentPciIo
->Pci
.Read (
2185 EfiPciIoWidthUint32
,
2186 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET
,
2190 if ((Data32
& EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING
) != 0) {
2192 // ARI forward support in bridge, so enable it.
2194 ParentPciIo
->Pci
.Read (
2196 EfiPciIoWidthUint32
,
2197 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET
,
2201 if ((Data32
& EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING
) == 0) {
2202 Data32
|= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING
;
2203 ParentPciIo
->Pci
.Write (
2205 EfiPciIoWidthUint32
,
2206 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET
,
2212 " ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n",
2214 Bridge
->DeviceNumber
,
2215 Bridge
->FunctionNumber
2220 DEBUG ((EFI_D_INFO
, " ARI: CapOffset = 0x%x\n", PciIoDevice
->AriCapabilityOffset
));
2225 // Initialization for SR-IOV
2228 if (PcdGetBool (PcdSrIovSupport
)) {
2229 Status
= LocatePciExpressCapabilityRegBlock (
2231 EFI_PCIE_CAPABILITY_ID_SRIOV
,
2232 &PciIoDevice
->SrIovCapabilityOffset
,
2235 if (!EFI_ERROR (Status
)) {
2236 UINT32 SupportedPageSize
;
2238 UINT16 FirstVFOffset
;
2244 // If the SR-IOV device is an ARI device, then Set ARI Capable Hierarchy for the device.
2246 if (PcdGetBool (PcdAriSupport
) && PciIoDevice
->AriCapabilityOffset
!= 0) {
2249 EfiPciIoWidthUint16
,
2250 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL
,
2254 Data16
|= EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY
;
2257 EfiPciIoWidthUint16
,
2258 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL
,
2265 // Calculate SystemPageSize
2270 EfiPciIoWidthUint32
,
2271 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE
,
2275 PciIoDevice
->SystemPageSize
= (PcdGet32 (PcdSrIovSystemPageSize
) & SupportedPageSize
);
2276 ASSERT (PciIoDevice
->SystemPageSize
!= 0);
2280 EfiPciIoWidthUint32
,
2281 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE
,
2283 &PciIoDevice
->SystemPageSize
2286 // Adjust SystemPageSize for Alignment usage later
2288 PciIoDevice
->SystemPageSize
<<= 12;
2291 // Calculate BusReservation for PCI IOV
2295 // Read First FirstVFOffset, InitialVFs, and VFStride
2299 EfiPciIoWidthUint16
,
2300 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF
,
2306 EfiPciIoWidthUint16
,
2307 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS
,
2309 &PciIoDevice
->InitialVFs
2313 EfiPciIoWidthUint16
,
2314 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE
,
2321 PFRid
= EFI_PCI_RID(Bus
, Device
, Func
);
2322 LastVF
= PFRid
+ FirstVFOffset
+ (PciIoDevice
->InitialVFs
- 1) * VFStride
;
2325 // Calculate ReservedBusNum for this PF
2327 PciIoDevice
->ReservedBusNum
= (UINT16
)(EFI_PCI_BUS_OF_RID (LastVF
) - Bus
+ 1);
2331 " SR-IOV: SupportedPageSize = 0x%x; SystemPageSize = 0x%x; FirstVFOffset = 0x%x;\n",
2332 SupportedPageSize
, PciIoDevice
->SystemPageSize
>> 12, FirstVFOffset
2336 " InitialVFs = 0x%x; ReservedBusNum = 0x%x; CapOffset = 0x%x\n",
2337 PciIoDevice
->InitialVFs
, PciIoDevice
->ReservedBusNum
, PciIoDevice
->SrIovCapabilityOffset
2342 if (PcdGetBool (PcdMrIovSupport
)) {
2343 Status
= LocatePciExpressCapabilityRegBlock (
2345 EFI_PCIE_CAPABILITY_ID_MRIOV
,
2346 &PciIoDevice
->MrIovCapabilityOffset
,
2349 if (!EFI_ERROR (Status
)) {
2350 DEBUG ((EFI_D_INFO
, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice
->MrIovCapabilityOffset
));
2355 // Initialize the reserved resource list
2357 InitializeListHead (&PciIoDevice
->ReservedResourceList
);
2360 // Initialize the driver list
2362 InitializeListHead (&PciIoDevice
->OptionRomDriverList
);
2365 // Initialize the child list
2367 InitializeListHead (&PciIoDevice
->ChildList
);
2373 This routine is used to enumerate entire pci bus system
2374 in a given platform.
2376 It is only called on the second start on the same Root Bridge.
2378 @param Controller Parent bridge handler.
2380 @retval EFI_SUCCESS PCI enumeration finished successfully.
2381 @retval other Some error occurred when enumerating the pci bus system.
2385 PciEnumeratorLight (
2386 IN EFI_HANDLE Controller
2391 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2392 PCI_IO_DEVICE
*RootBridgeDev
;
2395 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2398 MaxBus
= PCI_MAX_BUS
;
2402 // If this root bridge has been already enumerated, then return successfully
2404 if (GetRootBridgeByHandle (Controller
) != NULL
) {
2409 // Open pci root bridge io protocol
2411 Status
= gBS
->OpenProtocol (
2413 &gEfiPciRootBridgeIoProtocolGuid
,
2414 (VOID
**) &PciRootBridgeIo
,
2415 gPciBusDriverBinding
.DriverBindingHandle
,
2417 EFI_OPEN_PROTOCOL_BY_DRIVER
2419 if (EFI_ERROR (Status
) && Status
!= EFI_ALREADY_STARTED
) {
2423 Status
= PciRootBridgeIo
->Configuration (PciRootBridgeIo
, (VOID
**) &Descriptors
);
2425 if (EFI_ERROR (Status
)) {
2429 while (PciGetBusRange (&Descriptors
, &MinBus
, &MaxBus
, NULL
) == EFI_SUCCESS
) {
2432 // Create a device node for root bridge device with a NULL host bridge controller handle
2434 RootBridgeDev
= CreateRootBridge (Controller
);
2436 if (RootBridgeDev
== NULL
) {
2442 // Record the root bridgeio protocol
2444 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
2446 Status
= PciPciDeviceInfoCollector (
2451 if (!EFI_ERROR (Status
)) {
2454 // Remove those PCI devices which are rejected when full enumeration
2456 RemoveRejectedPciDevices (RootBridgeDev
->Handle
, RootBridgeDev
);
2459 // Process option rom light
2461 ProcessOptionRomLight (RootBridgeDev
);
2464 // Determine attributes for all devices under this root bridge
2466 DetermineDeviceAttribute (RootBridgeDev
);
2469 // If successfully, insert the node into device pool
2471 InsertRootBridge (RootBridgeDev
);
2475 // If unsuccessly, destroy the entire node
2477 DestroyRootBridge (RootBridgeDev
);
2487 Get bus range from PCI resource descriptor list.
2489 @param Descriptors A pointer to the address space descriptor.
2490 @param MinBus The min bus returned.
2491 @param MaxBus The max bus returned.
2492 @param BusRange The bus range returned.
2494 @retval EFI_SUCCESS Successfully got bus range.
2495 @retval EFI_NOT_FOUND Can not find the specific bus.
2500 IN EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
2503 OUT UINT16
*BusRange
2506 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
2507 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
2508 if (MinBus
!= NULL
) {
2509 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
2512 if (MaxBus
!= NULL
) {
2513 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
2516 if (BusRange
!= NULL
) {
2517 *BusRange
= (UINT16
) (*Descriptors
)->AddrLen
;
2526 return EFI_NOT_FOUND
;
2530 This routine can be used to start the root bridge.
2532 @param RootBridgeDev Pci device instance.
2534 @retval EFI_SUCCESS This device started.
2535 @retval other Failed to get PCI Root Bridge I/O protocol.
2539 StartManagingRootBridge (
2540 IN PCI_IO_DEVICE
*RootBridgeDev
2543 EFI_HANDLE RootBridgeHandle
;
2545 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2548 // Get the root bridge handle
2550 RootBridgeHandle
= RootBridgeDev
->Handle
;
2551 PciRootBridgeIo
= NULL
;
2554 // Get the pci root bridge io protocol
2556 Status
= gBS
->OpenProtocol (
2558 &gEfiPciRootBridgeIoProtocolGuid
,
2559 (VOID
**) &PciRootBridgeIo
,
2560 gPciBusDriverBinding
.DriverBindingHandle
,
2562 EFI_OPEN_PROTOCOL_BY_DRIVER
2565 if (EFI_ERROR (Status
) && Status
!= EFI_ALREADY_STARTED
) {
2570 // Store the PciRootBridgeIo protocol into root bridge private data
2572 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
2579 This routine can be used to check whether a PCI device should be rejected when light enumeration.
2581 @param PciIoDevice Pci device instance.
2583 @retval TRUE This device should be rejected.
2584 @retval FALSE This device shouldn't be rejected.
2588 IsPciDeviceRejected (
2589 IN PCI_IO_DEVICE
*PciIoDevice
2599 // PPB should be skip!
2601 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
2605 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
2607 // Only test base registers for P2C
2609 for (BarOffset
= 0x1C; BarOffset
<= 0x38; BarOffset
+= 2 * sizeof (UINT32
)) {
2611 Mask
= (BarOffset
< 0x2C) ? 0xFFFFF000 : 0xFFFFFFFC;
2612 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2613 if (EFI_ERROR (Status
)) {
2617 TestValue
= TestValue
& Mask
;
2618 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2620 // The bar isn't programed, so it should be rejected
2629 for (BarOffset
= 0x14; BarOffset
<= 0x24; BarOffset
+= sizeof (UINT32
)) {
2633 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2634 if (EFI_ERROR (Status
)) {
2638 if ((TestValue
& 0x01) != 0) {
2644 TestValue
= TestValue
& Mask
;
2645 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2655 TestValue
= TestValue
& Mask
;
2657 if ((TestValue
& 0x07) == 0x04) {
2662 BarOffset
+= sizeof (UINT32
);
2663 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2666 // Test its high 32-Bit BAR
2668 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2669 if (TestValue
== OldValue
) {
2679 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2690 Reset all bus number from specific bridge.
2692 @param Bridge Parent specific bridge.
2693 @param StartBusNumber Start bus number.
2697 ResetAllPpbBusNumber (
2698 IN PCI_IO_DEVICE
*Bridge
,
2699 IN UINT8 StartBusNumber
2709 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2711 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
2713 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2714 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2717 // Check to see whether a pci device is present
2719 Status
= PciDevicePresent (
2727 if (EFI_ERROR (Status
) && Func
== 0) {
2729 // go to next device if there is no Function 0
2734 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
))) {
2737 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x18);
2738 Status
= PciRootBridgeIo
->Pci
.Read (
2745 SecondaryBus
= (UINT8
)(Register
>> 8);
2747 if (SecondaryBus
!= 0) {
2748 ResetAllPpbBusNumber (Bridge
, SecondaryBus
);
2752 // Reset register 18h, 19h, 1Ah on PCI Bridge
2754 Register
&= 0xFF000000;
2755 Status
= PciRootBridgeIo
->Pci
.Write (
2764 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
2766 // Skip sub functions, this is not a multi function device
2768 Func
= PCI_MAX_FUNC
;