MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h

   1 /** @file
   2
   3   Provides some data structure definitions used by the SD/MMC host controller driver.
   4
   5 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
   6 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
   7 SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 #ifndef _SD_MMC_PCI_HCI_H_
  12 #define _SD_MMC_PCI_HCI_H_
  13
  14 //
  15 // SD Host Controller SlotInfo Register Offset
  16 //
  17 #define SD_MMC_HC_SLOT_OFFSET         0x40
  18
  19 #define SD_MMC_HC_MAX_SLOT            6
  20
  21 //
  22 // SD Host Controller MMIO Register Offset
  23 //
  24 #define SD_MMC_HC_SDMA_ADDR           0x00
  25 #define SD_MMC_HC_ARG2                0x00
  26 #define SD_MMC_HC_BLK_SIZE            0x04
  27 #define SD_MMC_HC_BLK_COUNT           0x06
  28 #define SD_MMC_HC_ARG1                0x08
  29 #define SD_MMC_HC_TRANS_MOD           0x0C
  30 #define SD_MMC_HC_COMMAND             0x0E
  31 #define SD_MMC_HC_RESPONSE            0x10
  32 #define SD_MMC_HC_BUF_DAT_PORT        0x20
  33 #define SD_MMC_HC_PRESENT_STATE       0x24
  34 #define SD_MMC_HC_HOST_CTRL1          0x28
  35 #define SD_MMC_HC_POWER_CTRL          0x29
  36 #define SD_MMC_HC_BLK_GAP_CTRL        0x2A
  37 #define SD_MMC_HC_WAKEUP_CTRL         0x2B
  38 #define SD_MMC_HC_CLOCK_CTRL          0x2C
  39 #define SD_MMC_HC_TIMEOUT_CTRL        0x2E
  40 #define SD_MMC_HC_SW_RST              0x2F
  41 #define SD_MMC_HC_NOR_INT_STS         0x30
  42 #define SD_MMC_HC_ERR_INT_STS         0x32
  43 #define SD_MMC_HC_NOR_INT_STS_EN      0x34
  44 #define SD_MMC_HC_ERR_INT_STS_EN      0x36
  45 #define SD_MMC_HC_NOR_INT_SIG_EN      0x38
  46 #define SD_MMC_HC_ERR_INT_SIG_EN      0x3A
  47 #define SD_MMC_HC_AUTO_CMD_ERR_STS    0x3C
  48 #define SD_MMC_HC_HOST_CTRL2          0x3E
  49 #define SD_MMC_HC_CAP                 0x40
  50 #define SD_MMC_HC_MAX_CURRENT_CAP     0x48
  51 #define SD_MMC_HC_FORCE_EVT_AUTO_CMD  0x50
  52 #define SD_MMC_HC_FORCE_EVT_ERR_INT   0x52
  53 #define SD_MMC_HC_ADMA_ERR_STS        0x54
  54 #define SD_MMC_HC_ADMA_SYS_ADDR       0x58
  55 #define SD_MMC_HC_PRESET_VAL          0x60
  56 #define SD_MMC_HC_SHARED_BUS_CTRL     0xE0
  57 #define SD_MMC_HC_SLOT_INT_STS        0xFC
  58 #define SD_MMC_HC_CTRL_VER            0xFE
  59
  60 //
  61 // SD Host Controller bits to HOST_CTRL2 register
  62 //
  63 #define SD_MMC_HC_CTRL_UHS_MASK       0x0007
  64 #define SD_MMC_HC_CTRL_UHS_SDR12      0x0000
  65 #define SD_MMC_HC_CTRL_UHS_SDR25      0x0001
  66 #define SD_MMC_HC_CTRL_UHS_SDR50      0x0002
  67 #define SD_MMC_HC_CTRL_UHS_SDR104     0x0003
  68 #define SD_MMC_HC_CTRL_UHS_DDR50      0x0004
  69 #define SD_MMC_HC_CTRL_MMC_LEGACY     0x0000
  70 #define SD_MMC_HC_CTRL_MMC_HS_SDR     0x0001
  71 #define SD_MMC_HC_CTRL_MMC_HS_DDR     0x0004
  72 #define SD_MMC_HC_CTRL_MMC_HS200      0x0003
  73 #define SD_MMC_HC_CTRL_MMC_HS400      0x0005
  74
  75 //
  76 // The transfer modes supported by SD Host Controller
  77 //
  78 typedef enum {
  79   SdMmcNoData,
  80   SdMmcPioMode,
  81   SdMmcSdmaMode,
  82   SdMmcAdma32bMode,
  83   SdMmcAdma64bV3Mode,
  84   SdMmcAdma64bV4Mode
  85 } SD_MMC_HC_TRANSFER_MODE;
  86
  87 //
  88 // The ADMA transfer lengths supported by SD Host Controller
  89 //
  90 typedef enum {
  91   SdMmcAdmaLen16b,
  92   SdMmcAdmaLen26b
  93 } SD_MMC_HC_ADMA_LENGTH_MODE;
  94
  95 //
  96 // The maximum data length of each descriptor line
  97 //
  98 #define ADMA_MAX_DATA_PER_LINE_16B     SIZE_64KB
  99 #define ADMA_MAX_DATA_PER_LINE_26B     SIZE_64MB
 100
 101 //
 102 // ADMA descriptor for 32b addressing.
 103 //
 104 typedef struct {
 105   UINT32 Valid:1;
 106   UINT32 End:1;
 107   UINT32 Int:1;
 108   UINT32 Reserved:1;
 109   UINT32 Act:2;
 110   UINT32 UpperLength:10;
 111   UINT32 LowerLength:16;
 112   UINT32 Address;
 113 } SD_MMC_HC_ADMA_32_DESC_LINE;
 114
 115 //
 116 // ADMA descriptor for 64b addressing.
 117 //
 118 typedef struct {
 119   UINT32 Valid:1;
 120   UINT32 End:1;
 121   UINT32 Int:1;
 122   UINT32 Reserved:1;
 123   UINT32 Act:2;
 124   UINT32 UpperLength:10;
 125   UINT32 LowerLength:16;
 126   UINT32 LowerAddress;
 127   UINT32 UpperAddress;
 128 } SD_MMC_HC_ADMA_64_V3_DESC_LINE;
 129
 130 typedef struct {
 131   UINT32 Valid:1;
 132   UINT32 End:1;
 133   UINT32 Int:1;
 134   UINT32 Reserved:1;
 135   UINT32 Act:2;
 136   UINT32 UpperLength:10;
 137   UINT32 LowerLength:16;
 138   UINT32 LowerAddress;
 139   UINT32 UpperAddress;
 140   UINT32 Reserved1;
 141 } SD_MMC_HC_ADMA_64_V4_DESC_LINE;
 142
 143 #define SD_MMC_SDMA_BOUNDARY          512 * 1024
 144 #define SD_MMC_SDMA_ROUND_UP(x, n)    (((x) + n) & ~(n - 1))
 145
 146 typedef struct {
 147   UINT8    FirstBar:3;        // bit 0:2
 148   UINT8    Reserved:1;        // bit 3
 149   UINT8    SlotNum:3;         // bit 4:6
 150   UINT8    Reserved1:1;       // bit 7
 151 } SD_MMC_HC_SLOT_INFO;
 152
 153 typedef struct {
 154   UINT32   TimeoutFreq:6;     // bit 0:5
 155   UINT32   Reserved:1;        // bit 6
 156   UINT32   TimeoutUnit:1;     // bit 7
 157   UINT32   BaseClkFreq:8;     // bit 8:15
 158   UINT32   MaxBlkLen:2;       // bit 16:17
 159   UINT32   BusWidth8:1;       // bit 18
 160   UINT32   Adma2:1;           // bit 19
 161   UINT32   Reserved2:1;       // bit 20
 162   UINT32   HighSpeed:1;       // bit 21
 163   UINT32   Sdma:1;            // bit 22
 164   UINT32   SuspRes:1;         // bit 23
 165   UINT32   Voltage33:1;       // bit 24
 166   UINT32   Voltage30:1;       // bit 25
 167   UINT32   Voltage18:1;       // bit 26
 168   UINT32   SysBus64V4:1;      // bit 27
 169   UINT32   SysBus64V3:1;      // bit 28
 170   UINT32   AsyncInt:1;        // bit 29
 171   UINT32   SlotType:2;        // bit 30:31
 172   UINT32   Sdr50:1;           // bit 32
 173   UINT32   Sdr104:1;          // bit 33
 174   UINT32   Ddr50:1;           // bit 34
 175   UINT32   Reserved3:1;       // bit 35
 176   UINT32   DriverTypeA:1;     // bit 36
 177   UINT32   DriverTypeC:1;     // bit 37
 178   UINT32   DriverTypeD:1;     // bit 38
 179   UINT32   DriverType4:1;     // bit 39
 180   UINT32   TimerCount:4;      // bit 40:43
 181   UINT32   Reserved4:1;       // bit 44
 182   UINT32   TuningSDR50:1;     // bit 45
 183   UINT32   RetuningMod:2;     // bit 46:47
 184   UINT32   ClkMultiplier:8;   // bit 48:55
 185   UINT32   Reserved5:7;       // bit 56:62
 186   UINT32   Hs400:1;           // bit 63
 187 } SD_MMC_HC_SLOT_CAP;
 188
 189 //
 190 // SD Host controller version
 191 //
 192 #define SD_MMC_HC_CTRL_VER_100        0x00
 193 #define SD_MMC_HC_CTRL_VER_200        0x01
 194 #define SD_MMC_HC_CTRL_VER_300        0x02
 195 #define SD_MMC_HC_CTRL_VER_400        0x03
 196 #define SD_MMC_HC_CTRL_VER_410        0x04
 197 #define SD_MMC_HC_CTRL_VER_420        0x05
 198
 199 //
 200 // SD Host controller V4 enhancements
 201 //
 202 #define SD_MMC_HC_V4_EN               BIT12
 203 #define SD_MMC_HC_64_ADDR_EN          BIT13
 204 #define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10
 205
 206 /**
 207   Dump the content of SD/MMC host controller's Capability Register.
 208
 209   @param[in]  Slot            The slot number of the SD card to send the command to.
 210   @param[in]  Capability      The buffer to store the capability data.
 211
 212 **/
 213 VOID
 214 DumpCapabilityReg (
 215   IN UINT8                Slot,
 216   IN SD_MMC_HC_SLOT_CAP   *Capability
 217   );
 218
 219 /**
 220   Read SlotInfo register from SD/MMC host controller pci config space.
 221
 222   @param[in]  PciIo        The PCI IO protocol instance.
 223   @param[out] FirstBar     The buffer to store the first BAR value.
 224   @param[out] SlotNum      The buffer to store the supported slot number.
 225
 226   @retval EFI_SUCCESS      The operation succeeds.
 227   @retval Others           The operation fails.
 228
 229 **/
 230 EFI_STATUS
 231 EFIAPI
 232 SdMmcHcGetSlotInfo (
 233   IN     EFI_PCI_IO_PROTOCOL   *PciIo,
 234      OUT UINT8                 *FirstBar,
 235      OUT UINT8                 *SlotNum
 236   );
 237
 238 /**
 239   Read/Write specified SD/MMC host controller mmio register.
 240
 241   @param[in]      PciIo        The PCI IO protocol instance.
 242   @param[in]      BarIndex     The BAR index of the standard PCI Configuration
 243                                header to use as the base address for the memory
 244                                operation to perform.
 245   @param[in]      Offset       The offset within the selected BAR to start the
 246                                memory operation.
 247   @param[in]      Read         A boolean to indicate it's read or write operation.
 248   @param[in]      Count        The width of the mmio register in bytes.
 249                                Must be 1, 2 , 4 or 8 bytes.
 250   @param[in, out] Data         For read operations, the destination buffer to store
 251                                the results. For write operations, the source buffer
 252                                to write data from. The caller is responsible for
 253                                having ownership of the data buffer and ensuring its
 254                                size not less than Count bytes.
 255
 256   @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
 257   @retval EFI_SUCCESS           The read/write operation succeeds.
 258   @retval Others                The read/write operation fails.
 259
 260 **/
 261 EFI_STATUS
 262 EFIAPI
 263 SdMmcHcRwMmio (
 264   IN     EFI_PCI_IO_PROTOCOL   *PciIo,
 265   IN     UINT8                 BarIndex,
 266   IN     UINT32                Offset,
 267   IN     BOOLEAN               Read,
 268   IN     UINT8                 Count,
 269   IN OUT VOID                  *Data
 270   );
 271
 272 /**
 273   Do OR operation with the value of the specified SD/MMC host controller mmio register.
 274
 275   @param[in] PciIo             The PCI IO protocol instance.
 276   @param[in] BarIndex          The BAR index of the standard PCI Configuration
 277                                header to use as the base address for the memory
 278                                operation to perform.
 279   @param[in] Offset            The offset within the selected BAR to start the
 280                                memory operation.
 281   @param[in] Count             The width of the mmio register in bytes.
 282                                Must be 1, 2 , 4 or 8 bytes.
 283   @param[in] OrData            The pointer to the data used to do OR operation.
 284                                The caller is responsible for having ownership of
 285                                the data buffer and ensuring its size not less than
 286                                Count bytes.
 287
 288   @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
 289   @retval EFI_SUCCESS           The OR operation succeeds.
 290   @retval Others                The OR operation fails.
 291
 292 **/
 293 EFI_STATUS
 294 EFIAPI
 295 SdMmcHcOrMmio (
 296   IN  EFI_PCI_IO_PROTOCOL      *PciIo,
 297   IN  UINT8                    BarIndex,
 298   IN  UINT32                   Offset,
 299   IN  UINT8                    Count,
 300   IN  VOID                     *OrData
 301   );
 302
 303 /**
 304   Do AND operation with the value of the specified SD/MMC host controller mmio register.
 305
 306   @param[in] PciIo             The PCI IO protocol instance.
 307   @param[in] BarIndex          The BAR index of the standard PCI Configuration
 308                                header to use as the base address for the memory
 309                                operation to perform.
 310   @param[in] Offset            The offset within the selected BAR to start the
 311                                memory operation.
 312   @param[in] Count             The width of the mmio register in bytes.
 313                                Must be 1, 2 , 4 or 8 bytes.
 314   @param[in] AndData           The pointer to the data used to do AND operation.
 315                                The caller is responsible for having ownership of
 316                                the data buffer and ensuring its size not less than
 317                                Count bytes.
 318
 319   @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
 320   @retval EFI_SUCCESS           The AND operation succeeds.
 321   @retval Others                The AND operation fails.
 322
 323 **/
 324 EFI_STATUS
 325 EFIAPI
 326 SdMmcHcAndMmio (
 327   IN  EFI_PCI_IO_PROTOCOL      *PciIo,
 328   IN  UINT8                    BarIndex,
 329   IN  UINT32                   Offset,
 330   IN  UINT8                    Count,
 331   IN  VOID                     *AndData
 332   );
 333
 334 /**
 335   Wait for the value of the specified MMIO register set to the test value.
 336
 337   @param[in]  PciIo         The PCI IO protocol instance.
 338   @param[in]  BarIndex      The BAR index of the standard PCI Configuration
 339                             header to use as the base address for the memory
 340                             operation to perform.
 341   @param[in]  Offset        The offset within the selected BAR to start the
 342                             memory operation.
 343   @param[in]  Count         The width of the mmio register in bytes.
 344                             Must be 1, 2, 4 or 8 bytes.
 345   @param[in]  MaskValue     The mask value of memory.
 346   @param[in]  TestValue     The test value of memory.
 347   @param[in]  Timeout       The time out value for wait memory set, uses 1
 348                             microsecond as a unit.
 349
 350   @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout
 351                             range.
 352   @retval EFI_SUCCESS       The MMIO register has expected value.
 353   @retval Others            The MMIO operation fails.
 354
 355 **/
 356 EFI_STATUS
 357 EFIAPI
 358 SdMmcHcWaitMmioSet (
 359   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 360   IN  UINT8                     BarIndex,
 361   IN  UINT32                    Offset,
 362   IN  UINT8                     Count,
 363   IN  UINT64                    MaskValue,
 364   IN  UINT64                    TestValue,
 365   IN  UINT64                    Timeout
 366   );
 367
 368 /**
 369   Get the controller version information from the specified slot.
 370
 371   @param[in]  PciIo           The PCI IO protocol instance.
 372   @param[in]  Slot            The slot number of the SD card to send the command to.
 373   @param[out] Version         The buffer to store the version information.
 374
 375   @retval EFI_SUCCESS         The operation executes successfully.
 376   @retval Others              The operation fails.
 377
 378 **/
 379 EFI_STATUS
 380 SdMmcHcGetControllerVersion (
 381   IN  EFI_PCI_IO_PROTOCOL  *PciIo,
 382   IN  UINT8                Slot,
 383   OUT UINT16               *Version
 384   );
 385
 386 /**
 387   Set all interrupt status bits in Normal and Error Interrupt Status Enable
 388   register.
 389
 390   @param[in] PciIo          The PCI IO protocol instance.
 391   @param[in] Slot           The slot number of the SD card to send the command to.
 392
 393   @retval EFI_SUCCESS       The operation executes successfully.
 394   @retval Others            The operation fails.
 395
 396 **/
 397 EFI_STATUS
 398 SdMmcHcEnableInterrupt (
 399   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 400   IN UINT8                  Slot
 401   );
 402
 403 /**
 404   Get the capability data from the specified slot.
 405
 406   @param[in]  PciIo           The PCI IO protocol instance.
 407   @param[in]  Slot            The slot number of the SD card to send the command to.
 408   @param[out] Capability      The buffer to store the capability data.
 409
 410   @retval EFI_SUCCESS         The operation executes successfully.
 411   @retval Others              The operation fails.
 412
 413 **/
 414 EFI_STATUS
 415 SdMmcHcGetCapability (
 416   IN     EFI_PCI_IO_PROTOCOL  *PciIo,
 417   IN     UINT8                Slot,
 418      OUT SD_MMC_HC_SLOT_CAP   *Capability
 419   );
 420
 421 /**
 422   Get the maximum current capability data from the specified slot.
 423
 424   @param[in]  PciIo           The PCI IO protocol instance.
 425   @param[in]  Slot            The slot number of the SD card to send the command to.
 426   @param[out] MaxCurrent      The buffer to store the maximum current capability data.
 427
 428   @retval EFI_SUCCESS         The operation executes successfully.
 429   @retval Others              The operation fails.
 430
 431 **/
 432 EFI_STATUS
 433 SdMmcHcGetMaxCurrent (
 434   IN     EFI_PCI_IO_PROTOCOL  *PciIo,
 435   IN     UINT8                Slot,
 436      OUT UINT64               *MaxCurrent
 437   );
 438
 439 /**
 440   Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
 441   slot.
 442
 443   Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
 444
 445   @param[in]  PciIo         The PCI IO protocol instance.
 446   @param[in]  Slot          The slot number of the SD card to send the command to.
 447   @param[out] MediaPresent  The pointer to the media present boolean value.
 448
 449   @retval EFI_SUCCESS       There is no media change happened.
 450   @retval EFI_MEDIA_CHANGED There is media change happened.
 451   @retval Others            The detection fails.
 452
 453 **/
 454 EFI_STATUS
 455 SdMmcHcCardDetect (
 456   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 457   IN UINT8                  Slot,
 458      OUT BOOLEAN            *MediaPresent
 459   );
 460
 461 /**
 462   Stop SD/MMC card clock.
 463
 464   Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
 465
 466   @param[in] PciIo          The PCI IO protocol instance.
 467   @param[in] Slot           The slot number of the SD card to send the command to.
 468
 469   @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.
 470   @retval Others            Fail to stop SD/MMC clock.
 471
 472 **/
 473 EFI_STATUS
 474 SdMmcHcStopClock (
 475   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 476   IN UINT8                  Slot
 477   );
 478
 479 /**
 480   SD/MMC card clock supply.
 481
 482   Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
 483
 484   @param[in] PciIo          The PCI IO protocol instance.
 485   @param[in] Slot           The slot number of the SD card to send the command to.
 486   @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.
 487   @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.
 488   @param[in] ControllerVer  The version of host controller.
 489
 490   @retval EFI_SUCCESS       The clock is supplied successfully.
 491   @retval Others            The clock isn't supplied successfully.
 492
 493 **/
 494 EFI_STATUS
 495 SdMmcHcClockSupply (
 496   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 497   IN UINT8                  Slot,
 498   IN UINT64                 ClockFreq,
 499   IN UINT32                 BaseClkFreq,
 500   IN UINT16                 ControllerVer
 501   );
 502
 503 /**
 504   SD/MMC bus power control.
 505
 506   Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
 507
 508   @param[in] PciIo          The PCI IO protocol instance.
 509   @param[in] Slot           The slot number of the SD card to send the command to.
 510   @param[in] PowerCtrl      The value setting to the power control register.
 511
 512   @retval TRUE              There is a SD/MMC card attached.
 513   @retval FALSE             There is no a SD/MMC card attached.
 514
 515 **/
 516 EFI_STATUS
 517 SdMmcHcPowerControl (
 518   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 519   IN UINT8                  Slot,
 520   IN UINT8                  PowerCtrl
 521   );
 522
 523 /**
 524   Set the SD/MMC bus width.
 525
 526   Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
 527
 528   @param[in] PciIo          The PCI IO protocol instance.
 529   @param[in] Slot           The slot number of the SD card to send the command to.
 530   @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.
 531
 532   @retval EFI_SUCCESS       The bus width is set successfully.
 533   @retval Others            The bus width isn't set successfully.
 534
 535 **/
 536 EFI_STATUS
 537 SdMmcHcSetBusWidth (
 538   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 539   IN UINT8                  Slot,
 540   IN UINT16                 BusWidth
 541   );
 542
 543 /**
 544   Supply SD/MMC card with lowest clock frequency at initialization.
 545
 546   @param[in] PciIo          The PCI IO protocol instance.
 547   @param[in] Slot           The slot number of the SD card to send the command to.
 548   @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.
 549   @param[in] ControllerVer  The version of host controller.
 550
 551   @retval EFI_SUCCESS       The clock is supplied successfully.
 552   @retval Others            The clock isn't supplied successfully.
 553
 554 **/
 555 EFI_STATUS
 556 SdMmcHcInitClockFreq (
 557   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 558   IN UINT8                  Slot,
 559   IN UINT32                 BaseClkFreq,
 560   IN UINT16                 ControllerVer
 561   );
 562
 563 /**
 564   Supply SD/MMC card with maximum voltage at initialization.
 565
 566   Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
 567
 568   @param[in] PciIo          The PCI IO protocol instance.
 569   @param[in] Slot           The slot number of the SD card to send the command to.
 570   @param[in] Capability     The capability of the slot.
 571
 572   @retval EFI_SUCCESS       The voltage is supplied successfully.
 573   @retval Others            The voltage isn't supplied successfully.
 574
 575 **/
 576 EFI_STATUS
 577 SdMmcHcInitPowerVoltage (
 578   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 579   IN UINT8                  Slot,
 580   IN SD_MMC_HC_SLOT_CAP     Capability
 581   );
 582
 583 /**
 584   Initialize the Timeout Control register with most conservative value at initialization.
 585
 586   Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
 587
 588   @param[in] PciIo          The PCI IO protocol instance.
 589   @param[in] Slot           The slot number of the SD card to send the command to.
 590
 591   @retval EFI_SUCCESS       The timeout control register is configured successfully.
 592   @retval Others            The timeout control register isn't configured successfully.
 593
 594 **/
 595 EFI_STATUS
 596 SdMmcHcInitTimeoutCtrl (
 597   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 598   IN UINT8                  Slot
 599   );
 600
 601 /**
 602   Set SD Host Controller control 2 registry according to selected speed.
 603
 604   @param[in] ControllerHandle The handle of the controller.
 605   @param[in] PciIo            The PCI IO protocol instance.
 606   @param[in] Slot             The slot number of the SD card to send the command to.
 607   @param[in] Timing           The timing to select.
 608
 609   @retval EFI_SUCCESS         The timing is set successfully.
 610   @retval Others              The timing isn't set successfully.
 611 **/
 612 EFI_STATUS
 613 SdMmcHcUhsSignaling (
 614   IN EFI_HANDLE             ControllerHandle,
 615   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 616   IN UINT8                  Slot,
 617   IN SD_MMC_BUS_MODE        Timing
 618   );
 619
 620 #endif