MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h

   1 /** @file
   2
   3   Provides some data structure definitions used by the SD/MMC host controller driver.
   4
   5 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _SD_MMC_PCI_HCI_H_
  17 #define _SD_MMC_PCI_HCI_H_
  18
  19 //
  20 // SD Host Controller SlotInfo Register Offset
  21 //
  22 #define SD_MMC_HC_SLOT_OFFSET         0x40
  23
  24 #define SD_MMC_HC_MAX_SLOT            6
  25
  26 //
  27 // SD Host Controller MMIO Register Offset
  28 //
  29 #define SD_MMC_HC_SDMA_ADDR           0x00
  30 #define SD_MMC_HC_ARG2                0x00
  31 #define SD_MMC_HC_BLK_SIZE            0x04
  32 #define SD_MMC_HC_BLK_COUNT           0x06
  33 #define SD_MMC_HC_ARG1                0x08
  34 #define SD_MMC_HC_TRANS_MOD           0x0C
  35 #define SD_MMC_HC_COMMAND             0x0E
  36 #define SD_MMC_HC_RESPONSE            0x10
  37 #define SD_MMC_HC_BUF_DAT_PORT        0x20
  38 #define SD_MMC_HC_PRESENT_STATE       0x24
  39 #define SD_MMC_HC_HOST_CTRL1          0x28
  40 #define SD_MMC_HC_POWER_CTRL          0x29
  41 #define SD_MMC_HC_BLK_GAP_CTRL        0x2A
  42 #define SD_MMC_HC_WAKEUP_CTRL         0x2B
  43 #define SD_MMC_HC_CLOCK_CTRL          0x2C
  44 #define SD_MMC_HC_TIMEOUT_CTRL        0x2E
  45 #define SD_MMC_HC_SW_RST              0x2F
  46 #define SD_MMC_HC_NOR_INT_STS         0x30
  47 #define SD_MMC_HC_ERR_INT_STS         0x32
  48 #define SD_MMC_HC_NOR_INT_STS_EN      0x34
  49 #define SD_MMC_HC_ERR_INT_STS_EN      0x36
  50 #define SD_MMC_HC_NOR_INT_SIG_EN      0x38
  51 #define SD_MMC_HC_ERR_INT_SIG_EN      0x3A
  52 #define SD_MMC_HC_AUTO_CMD_ERR_STS    0x3C
  53 #define SD_MMC_HC_HOST_CTRL2          0x3E
  54 #define SD_MMC_HC_CAP                 0x40
  55 #define SD_MMC_HC_MAX_CURRENT_CAP     0x48
  56 #define SD_MMC_HC_FORCE_EVT_AUTO_CMD  0x50
  57 #define SD_MMC_HC_FORCE_EVT_ERR_INT   0x52
  58 #define SD_MMC_HC_ADMA_ERR_STS        0x54
  59 #define SD_MMC_HC_ADMA_SYS_ADDR       0x58
  60 #define SD_MMC_HC_PRESET_VAL          0x60
  61 #define SD_MMC_HC_SHARED_BUS_CTRL     0xE0
  62 #define SD_MMC_HC_SLOT_INT_STS        0xFC
  63 #define SD_MMC_HC_CTRL_VER            0xFE
  64
  65 //
  66 // SD Host Controller bits to HOST_CTRL2 register
  67 //
  68 #define SD_MMC_HC_CTRL_UHS_MASK       0x0007
  69 #define SD_MMC_HC_CTRL_UHS_SDR12      0x0000
  70 #define SD_MMC_HC_CTRL_UHS_SDR25      0x0001
  71 #define SD_MMC_HC_CTRL_UHS_SDR50      0x0002
  72 #define SD_MMC_HC_CTRL_UHS_SDR104     0x0003
  73 #define SD_MMC_HC_CTRL_UHS_DDR50      0x0004
  74 #define SD_MMC_HC_CTRL_MMC_LEGACY     0x0000
  75 #define SD_MMC_HC_CTRL_MMC_HS_SDR     0x0001
  76 #define SD_MMC_HC_CTRL_MMC_HS_DDR     0x0004
  77 #define SD_MMC_HC_CTRL_MMC_HS200      0x0003
  78 #define SD_MMC_HC_CTRL_MMC_HS400      0x0005
  79
  80 //
  81 // The transfer modes supported by SD Host Controller
  82 // Simplified Spec 3.0 Table 1-2
  83 //
  84 typedef enum {
  85   SdMmcNoData,
  86   SdMmcPioMode,
  87   SdMmcSdmaMode,
  88   SdMmcAdmaMode
  89 } SD_MMC_HC_TRANSFER_MODE;
  90
  91 //
  92 // The maximum data length of each descriptor line
  93 //
  94 #define ADMA_MAX_DATA_PER_LINE     0x10000
  95
  96 typedef struct {
  97   UINT32 Valid:1;
  98   UINT32 End:1;
  99   UINT32 Int:1;
 100   UINT32 Reserved:1;
 101   UINT32 Act:2;
 102   UINT32 Reserved1:10;
 103   UINT32 Length:16;
 104   UINT32 Address;
 105 } SD_MMC_HC_ADMA_DESC_LINE;
 106
 107 #define SD_MMC_SDMA_BOUNDARY          512 * 1024
 108 #define SD_MMC_SDMA_ROUND_UP(x, n)    (((x) + n) & ~(n - 1))
 109
 110 typedef struct {
 111   UINT8    FirstBar:3;        // bit 0:2
 112   UINT8    Reserved:1;        // bit 3
 113   UINT8    SlotNum:3;         // bit 4:6
 114   UINT8    Reserved1:1;       // bit 7
 115 } SD_MMC_HC_SLOT_INFO;
 116
 117 typedef struct {
 118   UINT32   TimeoutFreq:6;     // bit 0:5
 119   UINT32   Reserved:1;        // bit 6
 120   UINT32   TimeoutUnit:1;     // bit 7
 121   UINT32   BaseClkFreq:8;     // bit 8:15
 122   UINT32   MaxBlkLen:2;       // bit 16:17
 123   UINT32   BusWidth8:1;       // bit 18
 124   UINT32   Adma2:1;           // bit 19
 125   UINT32   Reserved2:1;       // bit 20
 126   UINT32   HighSpeed:1;       // bit 21
 127   UINT32   Sdma:1;            // bit 22
 128   UINT32   SuspRes:1;         // bit 23
 129   UINT32   Voltage33:1;       // bit 24
 130   UINT32   Voltage30:1;       // bit 25
 131   UINT32   Voltage18:1;       // bit 26
 132   UINT32   Reserved3:1;       // bit 27
 133   UINT32   SysBus64:1;        // bit 28
 134   UINT32   AsyncInt:1;        // bit 29
 135   UINT32   SlotType:2;        // bit 30:31
 136   UINT32   Sdr50:1;           // bit 32
 137   UINT32   Sdr104:1;          // bit 33
 138   UINT32   Ddr50:1;           // bit 34
 139   UINT32   Reserved4:1;       // bit 35
 140   UINT32   DriverTypeA:1;     // bit 36
 141   UINT32   DriverTypeC:1;     // bit 37
 142   UINT32   DriverTypeD:1;     // bit 38
 143   UINT32   DriverType4:1;     // bit 39
 144   UINT32   TimerCount:4;      // bit 40:43
 145   UINT32   Reserved5:1;       // bit 44
 146   UINT32   TuningSDR50:1;     // bit 45
 147   UINT32   RetuningMod:2;     // bit 46:47
 148   UINT32   ClkMultiplier:8;   // bit 48:55
 149   UINT32   Reserved6:7;       // bit 56:62
 150   UINT32   Hs400:1;           // bit 63
 151 } SD_MMC_HC_SLOT_CAP;
 152
 153 //
 154 // SD Host controller version
 155 //
 156 #define SD_MMC_HC_CTRL_VER_100      0x00
 157 #define SD_MMC_HC_CTRL_VER_200      0x01
 158 #define SD_MMC_HC_CTRL_VER_300      0x02
 159 #define SD_MMC_HC_CTRL_VER_400      0x03
 160 #define SD_MMC_HC_CTRL_VER_410      0x04
 161 #define SD_MMC_HC_CTRL_VER_420      0x05
 162
 163 /**
 164   Dump the content of SD/MMC host controller's Capability Register.
 165
 166   @param[in]  Slot            The slot number of the SD card to send the command to.
 167   @param[in]  Capability      The buffer to store the capability data.
 168
 169 **/
 170 VOID
 171 DumpCapabilityReg (
 172   IN UINT8                Slot,
 173   IN SD_MMC_HC_SLOT_CAP   *Capability
 174   );
 175
 176 /**
 177   Read SlotInfo register from SD/MMC host controller pci config space.
 178
 179   @param[in]  PciIo        The PCI IO protocol instance.
 180   @param[out] FirstBar     The buffer to store the first BAR value.
 181   @param[out] SlotNum      The buffer to store the supported slot number.
 182
 183   @retval EFI_SUCCESS      The operation succeeds.
 184   @retval Others           The operation fails.
 185
 186 **/
 187 EFI_STATUS
 188 EFIAPI
 189 SdMmcHcGetSlotInfo (
 190   IN     EFI_PCI_IO_PROTOCOL   *PciIo,
 191      OUT UINT8                 *FirstBar,
 192      OUT UINT8                 *SlotNum
 193   );
 194
 195 /**
 196   Read/Write specified SD/MMC host controller mmio register.
 197
 198   @param[in]      PciIo        The PCI IO protocol instance.
 199   @param[in]      BarIndex     The BAR index of the standard PCI Configuration
 200                                header to use as the base address for the memory
 201                                operation to perform.
 202   @param[in]      Offset       The offset within the selected BAR to start the
 203                                memory operation.
 204   @param[in]      Read         A boolean to indicate it's read or write operation.
 205   @param[in]      Count        The width of the mmio register in bytes.
 206                                Must be 1, 2 , 4 or 8 bytes.
 207   @param[in, out] Data         For read operations, the destination buffer to store
 208                                the results. For write operations, the source buffer
 209                                to write data from. The caller is responsible for
 210                                having ownership of the data buffer and ensuring its
 211                                size not less than Count bytes.
 212
 213   @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
 214   @retval EFI_SUCCESS           The read/write operation succeeds.
 215   @retval Others                The read/write operation fails.
 216
 217 **/
 218 EFI_STATUS
 219 EFIAPI
 220 SdMmcHcRwMmio (
 221   IN     EFI_PCI_IO_PROTOCOL   *PciIo,
 222   IN     UINT8                 BarIndex,
 223   IN     UINT32                Offset,
 224   IN     BOOLEAN               Read,
 225   IN     UINT8                 Count,
 226   IN OUT VOID                  *Data
 227   );
 228
 229 /**
 230   Do OR operation with the value of the specified SD/MMC host controller mmio register.
 231
 232   @param[in] PciIo             The PCI IO protocol instance.
 233   @param[in] BarIndex          The BAR index of the standard PCI Configuration
 234                                header to use as the base address for the memory
 235                                operation to perform.
 236   @param[in] Offset            The offset within the selected BAR to start the
 237                                memory operation.
 238   @param[in] Count             The width of the mmio register in bytes.
 239                                Must be 1, 2 , 4 or 8 bytes.
 240   @param[in] OrData            The pointer to the data used to do OR operation.
 241                                The caller is responsible for having ownership of
 242                                the data buffer and ensuring its size not less than
 243                                Count bytes.
 244
 245   @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
 246   @retval EFI_SUCCESS           The OR operation succeeds.
 247   @retval Others                The OR operation fails.
 248
 249 **/
 250 EFI_STATUS
 251 EFIAPI
 252 SdMmcHcOrMmio (
 253   IN  EFI_PCI_IO_PROTOCOL      *PciIo,
 254   IN  UINT8                    BarIndex,
 255   IN  UINT32                   Offset,
 256   IN  UINT8                    Count,
 257   IN  VOID                     *OrData
 258   );
 259
 260 /**
 261   Do AND operation with the value of the specified SD/MMC host controller mmio register.
 262
 263   @param[in] PciIo             The PCI IO protocol instance.
 264   @param[in] BarIndex          The BAR index of the standard PCI Configuration
 265                                header to use as the base address for the memory
 266                                operation to perform.
 267   @param[in] Offset            The offset within the selected BAR to start the
 268                                memory operation.
 269   @param[in] Count             The width of the mmio register in bytes.
 270                                Must be 1, 2 , 4 or 8 bytes.
 271   @param[in] AndData           The pointer to the data used to do AND operation.
 272                                The caller is responsible for having ownership of
 273                                the data buffer and ensuring its size not less than
 274                                Count bytes.
 275
 276   @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
 277   @retval EFI_SUCCESS           The AND operation succeeds.
 278   @retval Others                The AND operation fails.
 279
 280 **/
 281 EFI_STATUS
 282 EFIAPI
 283 SdMmcHcAndMmio (
 284   IN  EFI_PCI_IO_PROTOCOL      *PciIo,
 285   IN  UINT8                    BarIndex,
 286   IN  UINT32                   Offset,
 287   IN  UINT8                    Count,
 288   IN  VOID                     *AndData
 289   );
 290
 291 /**
 292   Wait for the value of the specified MMIO register set to the test value.
 293
 294   @param[in]  PciIo         The PCI IO protocol instance.
 295   @param[in]  BarIndex      The BAR index of the standard PCI Configuration
 296                             header to use as the base address for the memory
 297                             operation to perform.
 298   @param[in]  Offset        The offset within the selected BAR to start the
 299                             memory operation.
 300   @param[in]  Count         The width of the mmio register in bytes.
 301                             Must be 1, 2, 4 or 8 bytes.
 302   @param[in]  MaskValue     The mask value of memory.
 303   @param[in]  TestValue     The test value of memory.
 304   @param[in]  Timeout       The time out value for wait memory set, uses 1
 305                             microsecond as a unit.
 306
 307   @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout
 308                             range.
 309   @retval EFI_SUCCESS       The MMIO register has expected value.
 310   @retval Others            The MMIO operation fails.
 311
 312 **/
 313 EFI_STATUS
 314 EFIAPI
 315 SdMmcHcWaitMmioSet (
 316   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 317   IN  UINT8                     BarIndex,
 318   IN  UINT32                    Offset,
 319   IN  UINT8                     Count,
 320   IN  UINT64                    MaskValue,
 321   IN  UINT64                    TestValue,
 322   IN  UINT64                    Timeout
 323   );
 324
 325 /**
 326   Set all interrupt status bits in Normal and Error Interrupt Status Enable
 327   register.
 328
 329   @param[in] PciIo          The PCI IO protocol instance.
 330   @param[in] Slot           The slot number of the SD card to send the command to.
 331
 332   @retval EFI_SUCCESS       The operation executes successfully.
 333   @retval Others            The operation fails.
 334
 335 **/
 336 EFI_STATUS
 337 SdMmcHcEnableInterrupt (
 338   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 339   IN UINT8                  Slot
 340   );
 341
 342 /**
 343   Get the capability data from the specified slot.
 344
 345   @param[in]  PciIo           The PCI IO protocol instance.
 346   @param[in]  Slot            The slot number of the SD card to send the command to.
 347   @param[out] Capability      The buffer to store the capability data.
 348
 349   @retval EFI_SUCCESS         The operation executes successfully.
 350   @retval Others              The operation fails.
 351
 352 **/
 353 EFI_STATUS
 354 SdMmcHcGetCapability (
 355   IN     EFI_PCI_IO_PROTOCOL  *PciIo,
 356   IN     UINT8                Slot,
 357      OUT SD_MMC_HC_SLOT_CAP   *Capability
 358   );
 359
 360 /**
 361   Get the maximum current capability data from the specified slot.
 362
 363   @param[in]  PciIo           The PCI IO protocol instance.
 364   @param[in]  Slot            The slot number of the SD card to send the command to.
 365   @param[out] MaxCurrent      The buffer to store the maximum current capability data.
 366
 367   @retval EFI_SUCCESS         The operation executes successfully.
 368   @retval Others              The operation fails.
 369
 370 **/
 371 EFI_STATUS
 372 SdMmcHcGetMaxCurrent (
 373   IN     EFI_PCI_IO_PROTOCOL  *PciIo,
 374   IN     UINT8                Slot,
 375      OUT UINT64               *MaxCurrent
 376   );
 377
 378 /**
 379   Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
 380   slot.
 381
 382   Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
 383
 384   @param[in]  PciIo         The PCI IO protocol instance.
 385   @param[in]  Slot          The slot number of the SD card to send the command to.
 386   @param[out] MediaPresent  The pointer to the media present boolean value.
 387
 388   @retval EFI_SUCCESS       There is no media change happened.
 389   @retval EFI_MEDIA_CHANGED There is media change happened.
 390   @retval Others            The detection fails.
 391
 392 **/
 393 EFI_STATUS
 394 SdMmcHcCardDetect (
 395   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 396   IN UINT8                  Slot,
 397      OUT BOOLEAN            *MediaPresent
 398   );
 399
 400 /**
 401   Stop SD/MMC card clock.
 402
 403   Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
 404
 405   @param[in] PciIo          The PCI IO protocol instance.
 406   @param[in] Slot           The slot number of the SD card to send the command to.
 407
 408   @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.
 409   @retval Others            Fail to stop SD/MMC clock.
 410
 411 **/
 412 EFI_STATUS
 413 SdMmcHcStopClock (
 414   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 415   IN UINT8                  Slot
 416   );
 417
 418 /**
 419   SD/MMC card clock supply.
 420
 421   Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
 422
 423   @param[in] PciIo          The PCI IO protocol instance.
 424   @param[in] Slot           The slot number of the SD card to send the command to.
 425   @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.
 426   @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.
 427
 428   @retval EFI_SUCCESS       The clock is supplied successfully.
 429   @retval Others            The clock isn't supplied successfully.
 430
 431 **/
 432 EFI_STATUS
 433 SdMmcHcClockSupply (
 434   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 435   IN UINT8                  Slot,
 436   IN UINT64                 ClockFreq,
 437   IN UINT32                 BaseClkFreq
 438   );
 439
 440 /**
 441   SD/MMC bus power control.
 442
 443   Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
 444
 445   @param[in] PciIo          The PCI IO protocol instance.
 446   @param[in] Slot           The slot number of the SD card to send the command to.
 447   @param[in] PowerCtrl      The value setting to the power control register.
 448
 449   @retval TRUE              There is a SD/MMC card attached.
 450   @retval FALSE             There is no a SD/MMC card attached.
 451
 452 **/
 453 EFI_STATUS
 454 SdMmcHcPowerControl (
 455   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 456   IN UINT8                  Slot,
 457   IN UINT8                  PowerCtrl
 458   );
 459
 460 /**
 461   Set the SD/MMC bus width.
 462
 463   Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
 464
 465   @param[in] PciIo          The PCI IO protocol instance.
 466   @param[in] Slot           The slot number of the SD card to send the command to.
 467   @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.
 468
 469   @retval EFI_SUCCESS       The bus width is set successfully.
 470   @retval Others            The bus width isn't set successfully.
 471
 472 **/
 473 EFI_STATUS
 474 SdMmcHcSetBusWidth (
 475   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 476   IN UINT8                  Slot,
 477   IN UINT16                 BusWidth
 478   );
 479
 480 /**
 481   Supply SD/MMC card with lowest clock frequency at initialization.
 482
 483   @param[in] PciIo          The PCI IO protocol instance.
 484   @param[in] Slot           The slot number of the SD card to send the command to.
 485   @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.
 486
 487   @retval EFI_SUCCESS       The clock is supplied successfully.
 488   @retval Others            The clock isn't supplied successfully.
 489
 490 **/
 491 EFI_STATUS
 492 SdMmcHcInitClockFreq (
 493   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 494   IN UINT8                  Slot,
 495   IN UINT32                 BaseClkFreq
 496   );
 497
 498 /**
 499   Supply SD/MMC card with maximum voltage at initialization.
 500
 501   Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
 502
 503   @param[in] PciIo          The PCI IO protocol instance.
 504   @param[in] Slot           The slot number of the SD card to send the command to.
 505   @param[in] Capability     The capability of the slot.
 506
 507   @retval EFI_SUCCESS       The voltage is supplied successfully.
 508   @retval Others            The voltage isn't supplied successfully.
 509
 510 **/
 511 EFI_STATUS
 512 SdMmcHcInitPowerVoltage (
 513   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 514   IN UINT8                  Slot,
 515   IN SD_MMC_HC_SLOT_CAP     Capability
 516   );
 517
 518 /**
 519   Initialize the Timeout Control register with most conservative value at initialization.
 520
 521   Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
 522
 523   @param[in] PciIo          The PCI IO protocol instance.
 524   @param[in] Slot           The slot number of the SD card to send the command to.
 525
 526   @retval EFI_SUCCESS       The timeout control register is configured successfully.
 527   @retval Others            The timeout control register isn't configured successfully.
 528
 529 **/
 530 EFI_STATUS
 531 SdMmcHcInitTimeoutCtrl (
 532   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 533   IN UINT8                  Slot
 534   );
 535
 536 /**
 537   Set SD Host Controller control 2 registry according to selected speed.
 538
 539   @param[in] ControllerHandle The handle of the controller.
 540   @param[in] PciIo            The PCI IO protocol instance.
 541   @param[in] Slot             The slot number of the SD card to send the command to.
 542   @param[in] Timing           The timing to select.
 543
 544   @retval EFI_SUCCESS         The timing is set successfully.
 545   @retval Others              The timing isn't set successfully.
 546 **/
 547 EFI_STATUS
 548 SdMmcHcUhsSignaling (
 549   IN EFI_HANDLE             ControllerHandle,
 550   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 551   IN UINT8                  Slot,
 552   IN SD_MMC_BUS_MODE        Timing
 553   );
 554
 555 #endif