MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h

   1 /** @file
   2
   3   Provides some data structure definitions used by the SD/MMC host controller driver.
   4
   5 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
   6 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
   7 SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 #ifndef _SD_MMC_PCI_HCI_H_
  12 #define _SD_MMC_PCI_HCI_H_
  13
  14 //
  15 // SD Host Controller SlotInfo Register Offset
  16 //
  17 #define SD_MMC_HC_SLOT_OFFSET         0x40
  18
  19 #define SD_MMC_HC_MAX_SLOT            6
  20
  21 //
  22 // SD Host Controller MMIO Register Offset
  23 //
  24 #define SD_MMC_HC_SDMA_ADDR           0x00
  25 #define SD_MMC_HC_ARG2                0x00
  26 #define SD_MMC_HC_BLK_SIZE            0x04
  27 #define SD_MMC_HC_BLK_COUNT           0x06
  28 #define SD_MMC_HC_ARG1                0x08
  29 #define SD_MMC_HC_TRANS_MOD           0x0C
  30 #define SD_MMC_HC_COMMAND             0x0E
  31 #define SD_MMC_HC_RESPONSE            0x10
  32 #define SD_MMC_HC_BUF_DAT_PORT        0x20
  33 #define SD_MMC_HC_PRESENT_STATE       0x24
  34 #define SD_MMC_HC_HOST_CTRL1          0x28
  35 #define SD_MMC_HC_POWER_CTRL          0x29
  36 #define SD_MMC_HC_BLK_GAP_CTRL        0x2A
  37 #define SD_MMC_HC_WAKEUP_CTRL         0x2B
  38 #define SD_MMC_HC_CLOCK_CTRL          0x2C
  39 #define SD_MMC_HC_TIMEOUT_CTRL        0x2E
  40 #define SD_MMC_HC_SW_RST              0x2F
  41 #define SD_MMC_HC_NOR_INT_STS         0x30
  42 #define SD_MMC_HC_ERR_INT_STS         0x32
  43 #define SD_MMC_HC_NOR_INT_STS_EN      0x34
  44 #define SD_MMC_HC_ERR_INT_STS_EN      0x36
  45 #define SD_MMC_HC_NOR_INT_SIG_EN      0x38
  46 #define SD_MMC_HC_ERR_INT_SIG_EN      0x3A
  47 #define SD_MMC_HC_AUTO_CMD_ERR_STS    0x3C
  48 #define SD_MMC_HC_HOST_CTRL2          0x3E
  49 #define SD_MMC_HC_CAP                 0x40
  50 #define SD_MMC_HC_MAX_CURRENT_CAP     0x48
  51 #define SD_MMC_HC_FORCE_EVT_AUTO_CMD  0x50
  52 #define SD_MMC_HC_FORCE_EVT_ERR_INT   0x52
  53 #define SD_MMC_HC_ADMA_ERR_STS        0x54
  54 #define SD_MMC_HC_ADMA_SYS_ADDR       0x58
  55 #define SD_MMC_HC_PRESET_VAL          0x60
  56 #define SD_MMC_HC_SHARED_BUS_CTRL     0xE0
  57 #define SD_MMC_HC_SLOT_INT_STS        0xFC
  58 #define SD_MMC_HC_CTRL_VER            0xFE
  59
  60 //
  61 // SD Host Controller bits to HOST_CTRL2 register
  62 //
  63 #define SD_MMC_HC_CTRL_UHS_MASK       0x0007
  64 #define SD_MMC_HC_CTRL_UHS_SDR12      0x0000
  65 #define SD_MMC_HC_CTRL_UHS_SDR25      0x0001
  66 #define SD_MMC_HC_CTRL_UHS_SDR50      0x0002
  67 #define SD_MMC_HC_CTRL_UHS_SDR104     0x0003
  68 #define SD_MMC_HC_CTRL_UHS_DDR50      0x0004
  69 #define SD_MMC_HC_CTRL_MMC_LEGACY     0x0000
  70 #define SD_MMC_HC_CTRL_MMC_HS_SDR     0x0001
  71 #define SD_MMC_HC_CTRL_MMC_HS_DDR     0x0004
  72 #define SD_MMC_HC_CTRL_MMC_HS200      0x0003
  73 #define SD_MMC_HC_CTRL_MMC_HS400      0x0005
  74
  75 #define SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK  0x0030
  76
  77 //
  78 // The transfer modes supported by SD Host Controller
  79 //
  80 typedef enum {
  81   SdMmcNoData,
  82   SdMmcPioMode,
  83   SdMmcSdmaMode,
  84   SdMmcAdma32bMode,
  85   SdMmcAdma64bV3Mode,
  86   SdMmcAdma64bV4Mode
  87 } SD_MMC_HC_TRANSFER_MODE;
  88
  89 //
  90 // The ADMA transfer lengths supported by SD Host Controller
  91 //
  92 typedef enum {
  93   SdMmcAdmaLen16b,
  94   SdMmcAdmaLen26b
  95 } SD_MMC_HC_ADMA_LENGTH_MODE;
  96
  97 //
  98 // The maximum data length of each descriptor line
  99 //
 100 #define ADMA_MAX_DATA_PER_LINE_16B     SIZE_64KB
 101 #define ADMA_MAX_DATA_PER_LINE_26B     SIZE_64MB
 102
 103 //
 104 // ADMA descriptor for 32b addressing.
 105 //
 106 typedef struct {
 107   UINT32 Valid:1;
 108   UINT32 End:1;
 109   UINT32 Int:1;
 110   UINT32 Reserved:1;
 111   UINT32 Act:2;
 112   UINT32 UpperLength:10;
 113   UINT32 LowerLength:16;
 114   UINT32 Address;
 115 } SD_MMC_HC_ADMA_32_DESC_LINE;
 116
 117 //
 118 // ADMA descriptor for 64b addressing.
 119 //
 120 typedef struct {
 121   UINT32 Valid:1;
 122   UINT32 End:1;
 123   UINT32 Int:1;
 124   UINT32 Reserved:1;
 125   UINT32 Act:2;
 126   UINT32 UpperLength:10;
 127   UINT32 LowerLength:16;
 128   UINT32 LowerAddress;
 129   UINT32 UpperAddress;
 130 } SD_MMC_HC_ADMA_64_V3_DESC_LINE;
 131
 132 typedef struct {
 133   UINT32 Valid:1;
 134   UINT32 End:1;
 135   UINT32 Int:1;
 136   UINT32 Reserved:1;
 137   UINT32 Act:2;
 138   UINT32 UpperLength:10;
 139   UINT32 LowerLength:16;
 140   UINT32 LowerAddress;
 141   UINT32 UpperAddress;
 142   UINT32 Reserved1;
 143 } SD_MMC_HC_ADMA_64_V4_DESC_LINE;
 144
 145 #define SD_MMC_SDMA_BOUNDARY          512 * 1024
 146 #define SD_MMC_SDMA_ROUND_UP(x, n)    (((x) + n) & ~(n - 1))
 147
 148 typedef struct {
 149   UINT8    FirstBar:3;        // bit 0:2
 150   UINT8    Reserved:1;        // bit 3
 151   UINT8    SlotNum:3;         // bit 4:6
 152   UINT8    Reserved1:1;       // bit 7
 153 } SD_MMC_HC_SLOT_INFO;
 154
 155 typedef struct {
 156   UINT32   TimeoutFreq:6;     // bit 0:5
 157   UINT32   Reserved:1;        // bit 6
 158   UINT32   TimeoutUnit:1;     // bit 7
 159   UINT32   BaseClkFreq:8;     // bit 8:15
 160   UINT32   MaxBlkLen:2;       // bit 16:17
 161   UINT32   BusWidth8:1;       // bit 18
 162   UINT32   Adma2:1;           // bit 19
 163   UINT32   Reserved2:1;       // bit 20
 164   UINT32   HighSpeed:1;       // bit 21
 165   UINT32   Sdma:1;            // bit 22
 166   UINT32   SuspRes:1;         // bit 23
 167   UINT32   Voltage33:1;       // bit 24
 168   UINT32   Voltage30:1;       // bit 25
 169   UINT32   Voltage18:1;       // bit 26
 170   UINT32   SysBus64V4:1;      // bit 27
 171   UINT32   SysBus64V3:1;      // bit 28
 172   UINT32   AsyncInt:1;        // bit 29
 173   UINT32   SlotType:2;        // bit 30:31
 174   UINT32   Sdr50:1;           // bit 32
 175   UINT32   Sdr104:1;          // bit 33
 176   UINT32   Ddr50:1;           // bit 34
 177   UINT32   Reserved3:1;       // bit 35
 178   UINT32   DriverTypeA:1;     // bit 36
 179   UINT32   DriverTypeC:1;     // bit 37
 180   UINT32   DriverTypeD:1;     // bit 38
 181   UINT32   DriverType4:1;     // bit 39
 182   UINT32   TimerCount:4;      // bit 40:43
 183   UINT32   Reserved4:1;       // bit 44
 184   UINT32   TuningSDR50:1;     // bit 45
 185   UINT32   RetuningMod:2;     // bit 46:47
 186   UINT32   ClkMultiplier:8;   // bit 48:55
 187   UINT32   Reserved5:7;       // bit 56:62
 188   UINT32   Hs400:1;           // bit 63
 189 } SD_MMC_HC_SLOT_CAP;
 190
 191 //
 192 // SD Host controller version
 193 //
 194 #define SD_MMC_HC_CTRL_VER_100        0x00
 195 #define SD_MMC_HC_CTRL_VER_200        0x01
 196 #define SD_MMC_HC_CTRL_VER_300        0x02
 197 #define SD_MMC_HC_CTRL_VER_400        0x03
 198 #define SD_MMC_HC_CTRL_VER_410        0x04
 199 #define SD_MMC_HC_CTRL_VER_420        0x05
 200
 201 //
 202 // SD Host controller V4 enhancements
 203 //
 204 #define SD_MMC_HC_V4_EN               BIT12
 205 #define SD_MMC_HC_64_ADDR_EN          BIT13
 206 #define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10
 207
 208 /**
 209   Dump the content of SD/MMC host controller's Capability Register.
 210
 211   @param[in]  Slot            The slot number of the SD card to send the command to.
 212   @param[in]  Capability      The buffer to store the capability data.
 213
 214 **/
 215 VOID
 216 DumpCapabilityReg (
 217   IN UINT8                Slot,
 218   IN SD_MMC_HC_SLOT_CAP   *Capability
 219   );
 220
 221 /**
 222   Read SlotInfo register from SD/MMC host controller pci config space.
 223
 224   @param[in]  PciIo        The PCI IO protocol instance.
 225   @param[out] FirstBar     The buffer to store the first BAR value.
 226   @param[out] SlotNum      The buffer to store the supported slot number.
 227
 228   @retval EFI_SUCCESS      The operation succeeds.
 229   @retval Others           The operation fails.
 230
 231 **/
 232 EFI_STATUS
 233 EFIAPI
 234 SdMmcHcGetSlotInfo (
 235   IN     EFI_PCI_IO_PROTOCOL   *PciIo,
 236      OUT UINT8                 *FirstBar,
 237      OUT UINT8                 *SlotNum
 238   );
 239
 240 /**
 241   Read/Write specified SD/MMC host controller mmio register.
 242
 243   @param[in]      PciIo        The PCI IO protocol instance.
 244   @param[in]      BarIndex     The BAR index of the standard PCI Configuration
 245                                header to use as the base address for the memory
 246                                operation to perform.
 247   @param[in]      Offset       The offset within the selected BAR to start the
 248                                memory operation.
 249   @param[in]      Read         A boolean to indicate it's read or write operation.
 250   @param[in]      Count        The width of the mmio register in bytes.
 251                                Must be 1, 2 , 4 or 8 bytes.
 252   @param[in, out] Data         For read operations, the destination buffer to store
 253                                the results. For write operations, the source buffer
 254                                to write data from. The caller is responsible for
 255                                having ownership of the data buffer and ensuring its
 256                                size not less than Count bytes.
 257
 258   @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
 259   @retval EFI_SUCCESS           The read/write operation succeeds.
 260   @retval Others                The read/write operation fails.
 261
 262 **/
 263 EFI_STATUS
 264 EFIAPI
 265 SdMmcHcRwMmio (
 266   IN     EFI_PCI_IO_PROTOCOL   *PciIo,
 267   IN     UINT8                 BarIndex,
 268   IN     UINT32                Offset,
 269   IN     BOOLEAN               Read,
 270   IN     UINT8                 Count,
 271   IN OUT VOID                  *Data
 272   );
 273
 274 /**
 275   Do OR operation with the value of the specified SD/MMC host controller mmio register.
 276
 277   @param[in] PciIo             The PCI IO protocol instance.
 278   @param[in] BarIndex          The BAR index of the standard PCI Configuration
 279                                header to use as the base address for the memory
 280                                operation to perform.
 281   @param[in] Offset            The offset within the selected BAR to start the
 282                                memory operation.
 283   @param[in] Count             The width of the mmio register in bytes.
 284                                Must be 1, 2 , 4 or 8 bytes.
 285   @param[in] OrData            The pointer to the data used to do OR operation.
 286                                The caller is responsible for having ownership of
 287                                the data buffer and ensuring its size not less than
 288                                Count bytes.
 289
 290   @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
 291   @retval EFI_SUCCESS           The OR operation succeeds.
 292   @retval Others                The OR operation fails.
 293
 294 **/
 295 EFI_STATUS
 296 EFIAPI
 297 SdMmcHcOrMmio (
 298   IN  EFI_PCI_IO_PROTOCOL      *PciIo,
 299   IN  UINT8                    BarIndex,
 300   IN  UINT32                   Offset,
 301   IN  UINT8                    Count,
 302   IN  VOID                     *OrData
 303   );
 304
 305 /**
 306   Do AND operation with the value of the specified SD/MMC host controller mmio register.
 307
 308   @param[in] PciIo             The PCI IO protocol instance.
 309   @param[in] BarIndex          The BAR index of the standard PCI Configuration
 310                                header to use as the base address for the memory
 311                                operation to perform.
 312   @param[in] Offset            The offset within the selected BAR to start the
 313                                memory operation.
 314   @param[in] Count             The width of the mmio register in bytes.
 315                                Must be 1, 2 , 4 or 8 bytes.
 316   @param[in] AndData           The pointer to the data used to do AND operation.
 317                                The caller is responsible for having ownership of
 318                                the data buffer and ensuring its size not less than
 319                                Count bytes.
 320
 321   @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
 322   @retval EFI_SUCCESS           The AND operation succeeds.
 323   @retval Others                The AND operation fails.
 324
 325 **/
 326 EFI_STATUS
 327 EFIAPI
 328 SdMmcHcAndMmio (
 329   IN  EFI_PCI_IO_PROTOCOL      *PciIo,
 330   IN  UINT8                    BarIndex,
 331   IN  UINT32                   Offset,
 332   IN  UINT8                    Count,
 333   IN  VOID                     *AndData
 334   );
 335
 336 /**
 337   Wait for the value of the specified MMIO register set to the test value.
 338
 339   @param[in]  PciIo         The PCI IO protocol instance.
 340   @param[in]  BarIndex      The BAR index of the standard PCI Configuration
 341                             header to use as the base address for the memory
 342                             operation to perform.
 343   @param[in]  Offset        The offset within the selected BAR to start the
 344                             memory operation.
 345   @param[in]  Count         The width of the mmio register in bytes.
 346                             Must be 1, 2, 4 or 8 bytes.
 347   @param[in]  MaskValue     The mask value of memory.
 348   @param[in]  TestValue     The test value of memory.
 349   @param[in]  Timeout       The time out value for wait memory set, uses 1
 350                             microsecond as a unit.
 351
 352   @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout
 353                             range.
 354   @retval EFI_SUCCESS       The MMIO register has expected value.
 355   @retval Others            The MMIO operation fails.
 356
 357 **/
 358 EFI_STATUS
 359 EFIAPI
 360 SdMmcHcWaitMmioSet (
 361   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 362   IN  UINT8                     BarIndex,
 363   IN  UINT32                    Offset,
 364   IN  UINT8                     Count,
 365   IN  UINT64                    MaskValue,
 366   IN  UINT64                    TestValue,
 367   IN  UINT64                    Timeout
 368   );
 369
 370 /**
 371   Get the controller version information from the specified slot.
 372
 373   @param[in]  PciIo           The PCI IO protocol instance.
 374   @param[in]  Slot            The slot number of the SD card to send the command to.
 375   @param[out] Version         The buffer to store the version information.
 376
 377   @retval EFI_SUCCESS         The operation executes successfully.
 378   @retval Others              The operation fails.
 379
 380 **/
 381 EFI_STATUS
 382 SdMmcHcGetControllerVersion (
 383   IN  EFI_PCI_IO_PROTOCOL  *PciIo,
 384   IN  UINT8                Slot,
 385   OUT UINT16               *Version
 386   );
 387
 388 /**
 389   Set all interrupt status bits in Normal and Error Interrupt Status Enable
 390   register.
 391
 392   @param[in] PciIo          The PCI IO protocol instance.
 393   @param[in] Slot           The slot number of the SD card to send the command to.
 394
 395   @retval EFI_SUCCESS       The operation executes successfully.
 396   @retval Others            The operation fails.
 397
 398 **/
 399 EFI_STATUS
 400 SdMmcHcEnableInterrupt (
 401   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 402   IN UINT8                  Slot
 403   );
 404
 405 /**
 406   Get the capability data from the specified slot.
 407
 408   @param[in]  PciIo           The PCI IO protocol instance.
 409   @param[in]  Slot            The slot number of the SD card to send the command to.
 410   @param[out] Capability      The buffer to store the capability data.
 411
 412   @retval EFI_SUCCESS         The operation executes successfully.
 413   @retval Others              The operation fails.
 414
 415 **/
 416 EFI_STATUS
 417 SdMmcHcGetCapability (
 418   IN     EFI_PCI_IO_PROTOCOL  *PciIo,
 419   IN     UINT8                Slot,
 420      OUT SD_MMC_HC_SLOT_CAP   *Capability
 421   );
 422
 423 /**
 424   Get the maximum current capability data from the specified slot.
 425
 426   @param[in]  PciIo           The PCI IO protocol instance.
 427   @param[in]  Slot            The slot number of the SD card to send the command to.
 428   @param[out] MaxCurrent      The buffer to store the maximum current capability data.
 429
 430   @retval EFI_SUCCESS         The operation executes successfully.
 431   @retval Others              The operation fails.
 432
 433 **/
 434 EFI_STATUS
 435 SdMmcHcGetMaxCurrent (
 436   IN     EFI_PCI_IO_PROTOCOL  *PciIo,
 437   IN     UINT8                Slot,
 438      OUT UINT64               *MaxCurrent
 439   );
 440
 441 /**
 442   Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
 443   slot.
 444
 445   Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
 446
 447   @param[in]  PciIo         The PCI IO protocol instance.
 448   @param[in]  Slot          The slot number of the SD card to send the command to.
 449   @param[out] MediaPresent  The pointer to the media present boolean value.
 450
 451   @retval EFI_SUCCESS       There is no media change happened.
 452   @retval EFI_MEDIA_CHANGED There is media change happened.
 453   @retval Others            The detection fails.
 454
 455 **/
 456 EFI_STATUS
 457 SdMmcHcCardDetect (
 458   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 459   IN UINT8                  Slot,
 460      OUT BOOLEAN            *MediaPresent
 461   );
 462
 463 /**
 464   Stop SD/MMC card clock.
 465
 466   Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
 467
 468   @param[in] PciIo          The PCI IO protocol instance.
 469   @param[in] Slot           The slot number of the SD card to send the command to.
 470
 471   @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.
 472   @retval Others            Fail to stop SD/MMC clock.
 473
 474 **/
 475 EFI_STATUS
 476 SdMmcHcStopClock (
 477   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 478   IN UINT8                  Slot
 479   );
 480
 481 /**
 482   SD/MMC card clock supply.
 483
 484   Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
 485
 486   @param[in] PciIo          The PCI IO protocol instance.
 487   @param[in] Slot           The slot number of the SD card to send the command to.
 488   @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.
 489   @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.
 490   @param[in] ControllerVer  The version of host controller.
 491
 492   @retval EFI_SUCCESS       The clock is supplied successfully.
 493   @retval Others            The clock isn't supplied successfully.
 494
 495 **/
 496 EFI_STATUS
 497 SdMmcHcClockSupply (
 498   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 499   IN UINT8                  Slot,
 500   IN UINT64                 ClockFreq,
 501   IN UINT32                 BaseClkFreq,
 502   IN UINT16                 ControllerVer
 503   );
 504
 505 /**
 506   SD/MMC bus power control.
 507
 508   Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
 509
 510   @param[in] PciIo          The PCI IO protocol instance.
 511   @param[in] Slot           The slot number of the SD card to send the command to.
 512   @param[in] PowerCtrl      The value setting to the power control register.
 513
 514   @retval TRUE              There is a SD/MMC card attached.
 515   @retval FALSE             There is no a SD/MMC card attached.
 516
 517 **/
 518 EFI_STATUS
 519 SdMmcHcPowerControl (
 520   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 521   IN UINT8                  Slot,
 522   IN UINT8                  PowerCtrl
 523   );
 524
 525 /**
 526   Set the SD/MMC bus width.
 527
 528   Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
 529
 530   @param[in] PciIo          The PCI IO protocol instance.
 531   @param[in] Slot           The slot number of the SD card to send the command to.
 532   @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.
 533
 534   @retval EFI_SUCCESS       The bus width is set successfully.
 535   @retval Others            The bus width isn't set successfully.
 536
 537 **/
 538 EFI_STATUS
 539 SdMmcHcSetBusWidth (
 540   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 541   IN UINT8                  Slot,
 542   IN UINT16                 BusWidth
 543   );
 544
 545 /**
 546   Supply SD/MMC card with lowest clock frequency at initialization.
 547
 548   @param[in] PciIo          The PCI IO protocol instance.
 549   @param[in] Slot           The slot number of the SD card to send the command to.
 550   @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.
 551   @param[in] ControllerVer  The version of host controller.
 552
 553   @retval EFI_SUCCESS       The clock is supplied successfully.
 554   @retval Others            The clock isn't supplied successfully.
 555
 556 **/
 557 EFI_STATUS
 558 SdMmcHcInitClockFreq (
 559   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 560   IN UINT8                  Slot,
 561   IN UINT32                 BaseClkFreq,
 562   IN UINT16                 ControllerVer
 563   );
 564
 565 /**
 566   Supply SD/MMC card with maximum voltage at initialization.
 567
 568   Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
 569
 570   @param[in] PciIo          The PCI IO protocol instance.
 571   @param[in] Slot           The slot number of the SD card to send the command to.
 572   @param[in] Capability     The capability of the slot.
 573
 574   @retval EFI_SUCCESS       The voltage is supplied successfully.
 575   @retval Others            The voltage isn't supplied successfully.
 576
 577 **/
 578 EFI_STATUS
 579 SdMmcHcInitPowerVoltage (
 580   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 581   IN UINT8                  Slot,
 582   IN SD_MMC_HC_SLOT_CAP     Capability
 583   );
 584
 585 /**
 586   Initialize the Timeout Control register with most conservative value at initialization.
 587
 588   Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
 589
 590   @param[in] PciIo          The PCI IO protocol instance.
 591   @param[in] Slot           The slot number of the SD card to send the command to.
 592
 593   @retval EFI_SUCCESS       The timeout control register is configured successfully.
 594   @retval Others            The timeout control register isn't configured successfully.
 595
 596 **/
 597 EFI_STATUS
 598 SdMmcHcInitTimeoutCtrl (
 599   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 600   IN UINT8                  Slot
 601   );
 602
 603 /**
 604   Set SD Host Controller control 2 registry according to selected speed.
 605
 606   @param[in] ControllerHandle The handle of the controller.
 607   @param[in] PciIo            The PCI IO protocol instance.
 608   @param[in] Slot             The slot number of the SD card to send the command to.
 609   @param[in] Timing           The timing to select.
 610
 611   @retval EFI_SUCCESS         The timing is set successfully.
 612   @retval Others              The timing isn't set successfully.
 613 **/
 614 EFI_STATUS
 615 SdMmcHcUhsSignaling (
 616   IN EFI_HANDLE             ControllerHandle,
 617   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 618   IN UINT8                  Slot,
 619   IN SD_MMC_BUS_MODE        Timing
 620   );
 621
 622 /**
 623   Set driver strength in host controller.
 624
 625   @param[in] PciIo           The PCI IO protocol instance.
 626   @param[in] SlotIndex       The slot index of the card.
 627   @param[in] DriverStrength  DriverStrength to set in the controller.
 628
 629   @retval EFI_SUCCESS  Driver strength programmed successfully.
 630   @retval Others       Failed to set driver strength.
 631 **/
 632 EFI_STATUS
 633 SdMmcSetDriverStrength (
 634   IN EFI_PCI_IO_PROTOCOL      *PciIo,
 635   IN UINT8                    SlotIndex,
 636   IN SD_DRIVER_STRENGTH_TYPE  DriverStrength
 637   );
 638
 639 #endif