]>
git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.c
3 The UHCI register operation routines.
5 Copyright (c) 2007, Intel Corporation
6 All rights reserved. This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
23 @param Offset Register offset to USB_BAR_INDEX.
25 @return Content of register.
30 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
37 Status
= PciIo
->Io
.Read (
46 if (EFI_ERROR (Status
)) {
47 DEBUG ((EFI_D_ERROR
, "UhciReadReg: PciIo Io.Read error: %r at offset %d\n", Status
, Offset
));
57 Write data to UHCI register.
59 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
60 @param Offset Register offset to USB_BAR_INDEX.
61 @param Data Data to write.
68 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
75 Status
= PciIo
->Io
.Write (
84 if (EFI_ERROR (Status
)) {
85 DEBUG ((EFI_D_ERROR
, "UhciWriteReg: PciIo Io.Write error: %r at offset %d\n", Status
, Offset
));
91 Set a bit of the UHCI Register.
93 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
94 @param Offset Register offset to USB_BAR_INDEX.
95 @param Bit The bit to set.
102 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
109 Data
= UhciReadReg (PciIo
, Offset
);
110 Data
= (UINT16
) (Data
|Bit
);
111 UhciWriteReg (PciIo
, Offset
, Data
);
116 Clear a bit of the UHCI Register.
118 @param PciIo The PCI_IO protocol to access the PCI.
119 @param Offset Register offset to USB_BAR_INDEX.
120 @param Bit The bit to clear.
127 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
134 Data
= UhciReadReg (PciIo
, Offset
);
135 Data
= (UINT16
) (Data
& ~Bit
);
136 UhciWriteReg (PciIo
, Offset
, Data
);
141 Clear all the interrutp status bits, these bits
144 @param Uhc The UHCI device.
150 UhciAckAllInterrupt (
154 UhciWriteReg (Uhc
->PciIo
, USBSTS_OFFSET
, 0x3F);
157 // If current HC is halted, re-enable it. Host Controller Process Error
158 // is a temporary error status.
160 if (!UhciIsHcWorking (Uhc
->PciIo
)) {
161 DEBUG ((EFI_D_ERROR
, "UhciAckAllInterrupt: re-enable the UHCI from system error\n"));
162 Uhc
->Usb2Hc
.SetState (&Uhc
->Usb2Hc
, EfiUsbHcStateOperational
);
168 Stop the host controller.
170 @param Uhc The UHCI device.
171 @param Timeout Max time allowed.
173 @retval EFI_SUCCESS The host controller is stopped.
174 @retval EFI_TIMEOUT Failed to stop the host controller.
186 UhciClearRegBit (Uhc
->PciIo
, USBCMD_OFFSET
, USBCMD_RS
);
189 // ensure the HC is in halt status after send the stop command
190 // Timeout is in us unit.
192 for (Index
= 0; Index
< (Timeout
/ 50) + 1; Index
++) {
193 UsbSts
= UhciReadReg (Uhc
->PciIo
, USBSTS_OFFSET
);
195 if ((UsbSts
& USBSTS_HCH
) == USBSTS_HCH
) {
207 Check whether the host controller operates well.
209 @param PciIo The PCI_IO protocol to use.
211 @retval TRUE Host controller is working.
212 @retval FALSE Host controller is halted or system error.
217 IN EFI_PCI_IO_PROTOCOL
*PciIo
222 UsbSts
= UhciReadReg (PciIo
, USBSTS_OFFSET
);
224 if ((UsbSts
& (USBSTS_HCPE
| USBSTS_HSE
| USBSTS_HCH
)) != 0) {
225 DEBUG ((EFI_D_ERROR
, "UhciIsHcWorking: current USB state is %x\n", UsbSts
));
234 Set the UHCI frame list base address. It can't use
235 UhciWriteReg which access memory in UINT16.
237 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
238 @param Addr Address to set.
244 UhciSetFrameListBaseAddr (
245 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
252 Data
= (UINT32
) ((UINTN
) Addr
& 0xFFFFF000);
254 Status
= PciIo
->Io
.Write (
258 (UINT64
) USB_FRAME_BASE_OFFSET
,
263 if (EFI_ERROR (Status
)) {
264 DEBUG ((EFI_D_ERROR
, "UhciSetFrameListBaseAddr: PciIo Io.Write error: %r\n", Status
));
270 Disable USB Emulation.
272 @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.
278 UhciTurnOffUsbEmulation (
279 IN EFI_PCI_IO_PROTOCOL
*PciIo
289 USB_EMULATION_OFFSET
,