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git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.c
8bb0f2b19aa2c45523e5f994f316283dd2ed0ca7
3 Copyright (c) 2007, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 The UHCI register operation routines.
31 @param PciIo The EFI_PCI_IO_PROTOCOL to use
32 @param Offset Register offset to USB_BAR_INDEX
34 @return Content of register
39 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
46 Status
= PciIo
->Io
.Read (
55 if (EFI_ERROR (Status
)) {
56 UHCI_ERROR (("UhciReadReg: PciIo Io.Read error: %r at offset %d\n", Status
, Offset
));
66 Write data to UHCI register
68 @param PciIo The EFI_PCI_IO_PROTOCOL to use
69 @param Offset Register offset to USB_BAR_INDEX
70 @param Data Data to write
77 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
84 Status
= PciIo
->Io
.Write (
93 if (EFI_ERROR (Status
)) {
94 UHCI_ERROR (("UhciWriteReg: PciIo Io.Write error: %r at offset %d\n", Status
, Offset
));
100 Set a bit of the UHCI Register
102 @param PciIo The EFI_PCI_IO_PROTOCOL to use
103 @param Offset Register offset to USB_BAR_INDEX
104 @param Bit The bit to set
111 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
118 Data
= UhciReadReg (PciIo
, Offset
);
119 Data
= (UINT16
) (Data
|Bit
);
120 UhciWriteReg (PciIo
, Offset
, Data
);
125 Clear a bit of the UHCI Register
127 @param PciIo The PCI_IO protocol to access the PCI
128 @param Offset Register offset to USB_BAR_INDEX
129 @param Bit The bit to clear
136 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
143 Data
= UhciReadReg (PciIo
, Offset
);
144 Data
= (UINT16
) (Data
& ~Bit
);
145 UhciWriteReg (PciIo
, Offset
, Data
);
150 Clear all the interrutp status bits, these bits
153 @param Uhc The UHCI device
159 UhciAckAllInterrupt (
163 UhciWriteReg (Uhc
->PciIo
, USBSTS_OFFSET
, 0x3F);
166 // If current HC is halted, re-enable it. Host Controller Process Error
167 // is a temporary error status.
169 if (!UhciIsHcWorking (Uhc
->PciIo
)) {
170 UHCI_ERROR (("UhciAckAllInterrupt: re-enable the UHCI from system error\n"));
171 Uhc
->UsbHc
.SetState (&Uhc
->UsbHc
, EfiUsbHcStateOperational
);
178 Stop the host controller
180 @param Uhc The UHCI device
181 @param Timeout Max time allowed
183 @retval EFI_SUCCESS The host controller is stopped
184 @retval EFI_TIMEOUT Failed to stop the host controller
196 UhciClearRegBit (Uhc
->PciIo
, USBCMD_OFFSET
, USBCMD_RS
);
199 // ensure the HC is in halt status after send the stop command
200 // Timeout is in us unit.
202 for (Index
= 0; Index
< (Timeout
/ 50) + 1; Index
++) {
203 UsbSts
= UhciReadReg (Uhc
->PciIo
, USBSTS_OFFSET
);
205 if ((UsbSts
& USBSTS_HCH
) == USBSTS_HCH
) {
217 Check whether the host controller operates well
219 @param PciIo The PCI_IO protocol to use
221 @retval TRUE Host controller is working
222 @retval FALSE Host controller is halted or system error
227 IN EFI_PCI_IO_PROTOCOL
*PciIo
232 UsbSts
= UhciReadReg (PciIo
, USBSTS_OFFSET
);
234 if (UsbSts
& (USBSTS_HCPE
| USBSTS_HSE
| USBSTS_HCH
)) {
235 UHCI_ERROR (("UhciIsHcWorking: current USB state is %x\n", UsbSts
));
244 Set the UHCI frame list base address. It can't use
245 UhciWriteReg which access memory in UINT16.
247 @param PciIo The EFI_PCI_IO_PROTOCOL to use
248 @param Addr Address to set
254 UhciSetFrameListBaseAddr (
255 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
262 Data
= (UINT32
) ((UINTN
) Addr
& 0xFFFFF000);
264 Status
= PciIo
->Io
.Write (
268 (UINT64
) USB_FRAME_BASE_OFFSET
,
273 if (EFI_ERROR (Status
)) {
274 UHCI_ERROR (("UhciSetFrameListBaseAddr: PciIo Io.Write error: %r\n", Status
));
280 Disable USB Emulation
282 @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use
288 UhciTurnOffUsbEmulation (
289 IN EFI_PCI_IO_PROTOCOL
*PciIo
299 USB_EMULATION_OFFSET
,