]>
git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.c
3 The UHCI register operation routines.
5 Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
15 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
16 @param Offset Register offset to USB_BAR_INDEX.
18 @return Content of register.
23 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
30 Status
= PciIo
->Io
.Read (
39 if (EFI_ERROR (Status
)) {
40 DEBUG ((DEBUG_ERROR
, "UhciReadReg: PciIo Io.Read error: %r at offset %d\n", Status
, Offset
));
49 Write data to UHCI register.
51 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
52 @param Offset Register offset to USB_BAR_INDEX.
53 @param Data Data to write.
58 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
65 Status
= PciIo
->Io
.Write (
74 if (EFI_ERROR (Status
)) {
75 DEBUG ((DEBUG_ERROR
, "UhciWriteReg: PciIo Io.Write error: %r at offset %d\n", Status
, Offset
));
80 Set a bit of the UHCI Register.
82 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
83 @param Offset Register offset to USB_BAR_INDEX.
84 @param Bit The bit to set.
89 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
96 Data
= UhciReadReg (PciIo
, Offset
);
97 Data
= (UINT16
)(Data
|Bit
);
98 UhciWriteReg (PciIo
, Offset
, Data
);
102 Clear a bit of the UHCI Register.
104 @param PciIo The PCI_IO protocol to access the PCI.
105 @param Offset Register offset to USB_BAR_INDEX.
106 @param Bit The bit to clear.
111 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
118 Data
= UhciReadReg (PciIo
, Offset
);
119 Data
= (UINT16
)(Data
& ~Bit
);
120 UhciWriteReg (PciIo
, Offset
, Data
);
124 Clear all the interrutp status bits, these bits
127 @param Uhc The UHCI device.
131 UhciAckAllInterrupt (
135 UhciWriteReg (Uhc
->PciIo
, USBSTS_OFFSET
, 0x3F);
138 // If current HC is halted, re-enable it. Host Controller Process Error
139 // is a temporary error status.
141 if (!UhciIsHcWorking (Uhc
->PciIo
)) {
142 DEBUG ((DEBUG_ERROR
, "UhciAckAllInterrupt: re-enable the UHCI from system error\n"));
143 Uhc
->Usb2Hc
.SetState (&Uhc
->Usb2Hc
, EfiUsbHcStateOperational
);
148 Stop the host controller.
150 @param Uhc The UHCI device.
151 @param Timeout Max time allowed.
153 @retval EFI_SUCCESS The host controller is stopped.
154 @retval EFI_TIMEOUT Failed to stop the host controller.
166 UhciClearRegBit (Uhc
->PciIo
, USBCMD_OFFSET
, USBCMD_RS
);
169 // ensure the HC is in halt status after send the stop command
170 // Timeout is in us unit.
172 for (Index
= 0; Index
< (Timeout
/ 50) + 1; Index
++) {
173 UsbSts
= UhciReadReg (Uhc
->PciIo
, USBSTS_OFFSET
);
175 if ((UsbSts
& USBSTS_HCH
) == USBSTS_HCH
) {
186 Check whether the host controller operates well.
188 @param PciIo The PCI_IO protocol to use.
190 @retval TRUE Host controller is working.
191 @retval FALSE Host controller is halted or system error.
196 IN EFI_PCI_IO_PROTOCOL
*PciIo
201 UsbSts
= UhciReadReg (PciIo
, USBSTS_OFFSET
);
203 if ((UsbSts
& (USBSTS_HCPE
| USBSTS_HSE
| USBSTS_HCH
)) != 0) {
204 DEBUG ((DEBUG_ERROR
, "UhciIsHcWorking: current USB state is %x\n", UsbSts
));
212 Set the UHCI frame list base address. It can't use
213 UhciWriteReg which access memory in UINT16.
215 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
216 @param Addr Address to set.
220 UhciSetFrameListBaseAddr (
221 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
228 Data
= (UINT32
)((UINTN
)Addr
& 0xFFFFF000);
230 Status
= PciIo
->Io
.Write (
234 (UINT64
)USB_FRAME_BASE_OFFSET
,
239 if (EFI_ERROR (Status
)) {
240 DEBUG ((DEBUG_ERROR
, "UhciSetFrameListBaseAddr: PciIo Io.Write error: %r\n", Status
));
245 Disable USB Emulation.
247 @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.
251 UhciTurnOffUsbEmulation (
252 IN EFI_PCI_IO_PROTOCOL
*PciIo
262 USB_EMULATION_OFFSET
,