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git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h
3 The definition for UHCI register operation routines.
5 Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #ifndef _EFI_UHCI_REG_H_
11 #define _EFI_UHCI_REG_H_
14 // UHCI register offset
17 #define UHCI_FRAME_NUM 1024
20 // Register offset and PCI related staff
22 #define USB_BAR_INDEX 4
24 #define USBCMD_OFFSET 0
25 #define USBSTS_OFFSET 2
26 #define USBINTR_OFFSET 4
27 #define USBPORTSC_OFFSET 0x10
28 #define USB_FRAME_NO_OFFSET 6
29 #define USB_FRAME_BASE_OFFSET 8
30 #define USB_EMULATION_OFFSET 0xC0
35 #define SETUP_PACKET_ID 0x2D
36 #define INPUT_PACKET_ID 0x69
37 #define OUTPUT_PACKET_ID 0xE1
38 #define ERROR_PACKET_ID 0x55
41 // USB port status and control bit definition.
43 #define USBPORTSC_CCS BIT0 // Current Connect Status
44 #define USBPORTSC_CSC BIT1 // Connect Status Change
45 #define USBPORTSC_PED BIT2 // Port Enable / Disable
46 #define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change
47 #define USBPORTSC_LSL BIT4 // Line Status Low BIT
48 #define USBPORTSC_LSH BIT5 // Line Status High BIT
49 #define USBPORTSC_RD BIT6 // Resume Detect
50 #define USBPORTSC_LSDA BIT8 // Low Speed Device Attached
51 #define USBPORTSC_PR BIT9 // Port Reset
52 #define USBPORTSC_SUSP BIT12 // Suspend
55 // UHCI Spec said it must implement 2 ports each host at least,
56 // and if more, check whether the bit7 of PORTSC is always 1.
57 // So here assume the max of port number each host is 16.
59 #define USB_MAX_ROOTHUB_PORT 0x0F
62 // Command register bit definitions
64 #define USBCMD_RS BIT0 // Run/Stop
65 #define USBCMD_HCRESET BIT1 // Host reset
66 #define USBCMD_GRESET BIT2 // Global reset
67 #define USBCMD_EGSM BIT3 // Global Suspend Mode
68 #define USBCMD_FGR BIT4 // Force Global Resume
69 #define USBCMD_SWDBG BIT5 // SW Debug mode
70 #define USBCMD_CF BIT6 // Config Flag (sw only)
71 #define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64)
74 // USB Status register bit definitions
76 #define USBSTS_USBINT BIT0 // Interrupt due to IOC
77 #define USBSTS_ERROR BIT1 // Interrupt due to error
78 #define USBSTS_RD BIT2 // Resume Detect
79 #define USBSTS_HSE BIT3 // Host System Error
80 #define USBSTS_HCPE BIT4 // Host Controller Process Error
81 #define USBSTS_HCH BIT5 // HC Halted
83 #define USBTD_ACTIVE BIT7 // TD is still active
84 #define USBTD_STALLED BIT6 // TD is stalled
85 #define USBTD_BUFFERR BIT5 // Buffer underflow or overflow
86 #define USBTD_BABBLE BIT4 // Babble condition
87 #define USBTD_NAK BIT3 // NAK is received
88 #define USBTD_CRC BIT2 // CRC/Time out error
89 #define USBTD_BITSTUFF BIT1 // Bit stuff error
94 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
95 @param Offset Register offset to USB_BAR_INDEX.
97 @return Content of register.
102 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
107 Write data to UHCI register.
109 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
110 @param Offset Register offset to USB_BAR_INDEX.
111 @param Data Data to write.
118 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
124 Set a bit of the UHCI Register.
126 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
127 @param Offset Register offset to USB_BAR_INDEX.
128 @param Bit The bit to set.
135 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
141 Clear a bit of the UHCI Register.
143 @param PciIo The PCI_IO protocol to access the PCI.
144 @param Offset Register offset to USB_BAR_INDEX.
145 @param Bit The bit to clear.
152 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
158 Clear all the interrutp status bits, these bits
161 @param Uhc The UHCI device.
167 UhciAckAllInterrupt (
172 Stop the host controller.
174 @param Uhc The UHCI device.
175 @param Timeout Max time allowed.
177 @retval EFI_SUCCESS The host controller is stopped.
178 @retval EFI_TIMEOUT Failed to stop the host controller.
188 Check whether the host controller operates well.
190 @param PciIo The PCI_IO protocol to use.
192 @retval TRUE Host controller is working.
193 @retval FALSE Host controller is halted or system error.
198 IN EFI_PCI_IO_PROTOCOL
*PciIo
202 Set the UHCI frame list base address. It can't use
203 UhciWriteReg which access memory in UINT16.
205 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
206 @param Addr Address to set.
212 UhciSetFrameListBaseAddr (
213 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
218 Disable USB Emulation.
220 @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.
226 UhciTurnOffUsbEmulation (
227 IN EFI_PCI_IO_PROTOCOL
*PciIo